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WO2009103907A3 - Procede de gravure localisee de la surface d'un substrat - Google Patents

Procede de gravure localisee de la surface d'un substrat Download PDF

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Publication number
WO2009103907A3
WO2009103907A3 PCT/FR2008/001820 FR2008001820W WO2009103907A3 WO 2009103907 A3 WO2009103907 A3 WO 2009103907A3 FR 2008001820 W FR2008001820 W FR 2008001820W WO 2009103907 A3 WO2009103907 A3 WO 2009103907A3
Authority
WO
WIPO (PCT)
Prior art keywords
substrate
pad
local etching
plasma
patterns
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/FR2008/001820
Other languages
English (en)
Other versions
WO2009103907A2 (fr
Inventor
Laurent Jalabert
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Centre National de la Recherche Scientifique CNRS
Original Assignee
Centre National de la Recherche Scientifique CNRS
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Centre National de la Recherche Scientifique CNRS filed Critical Centre National de la Recherche Scientifique CNRS
Priority to US12/811,467 priority Critical patent/US8475671B2/en
Priority to JP2010541081A priority patent/JP5715421B2/ja
Priority to EP08872521A priority patent/EP2232532A2/fr
Publication of WO2009103907A2 publication Critical patent/WO2009103907A2/fr
Publication of WO2009103907A3 publication Critical patent/WO2009103907A3/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31058—After-treatment of organic layers
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
    • B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
    • B81C1/00206—Processes for functionalising a surface, e.g. provide the surface with specific mechanical, chemical or biological properties
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y40/00—Manufacture or treatment of nanostructures
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/0002—Lithographic processes using patterning methods other than those involving the exposure to radiation, e.g. by stamping
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065—Plasma etching; Reactive-ion etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3081—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their composition, e.g. multilayer masks, materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31127—Etching organic layers
    • H01L21/31133—Etching organic layers by chemical means
    • H01L21/31138—Etching organic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Nanotechnology (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Health & Medical Sciences (AREA)
  • Mathematical Physics (AREA)
  • Inorganic Chemistry (AREA)
  • Health & Medical Sciences (AREA)
  • Life Sciences & Earth Sciences (AREA)
  • Theoretical Computer Science (AREA)
  • Molecular Biology (AREA)
  • Plasma & Fusion (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Treatments Of Macromolecular Shaped Articles (AREA)
  • Drying Of Semiconductors (AREA)
  • Micromachines (AREA)

Abstract

L'Invention est relative à un procédé de gravure localisée d'une surface d'un substrat caractérisé en ce qu'il met en œuvre : a) réaliser un tampon en polymère perméable aux gaz qui comporte des motifs en relief sur l'une de ces faces; b) mettre en contact la face comportant les motifs du tampon avec le substrat; c) soumettre l'ensemble tampon/substrat à un plasma de sorte que des espèces présentes dans le plasma sont accélérées et diffusent à travers le tampon jusqu'atteindre le substrat.
PCT/FR2008/001820 2008-01-03 2008-12-23 Procede de gravure localisee de la surface d'un substrat. Ceased WO2009103907A2 (fr)

Priority Applications (3)

Application Number Priority Date Filing Date Title
US12/811,467 US8475671B2 (en) 2008-01-03 2008-12-23 Method for local etching of the surface of a substrate
JP2010541081A JP5715421B2 (ja) 2008-01-03 2008-12-23 基板の表面を局部エッチングする方法
EP08872521A EP2232532A2 (fr) 2008-01-03 2008-12-23 Procede de gravure localisee de la surface d'un substrat

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR0800035A FR2926162B1 (fr) 2008-01-03 2008-01-03 Procede de modification localisee de l'energie de surface d'un substrat
FR0800035 2008-01-03

Publications (2)

Publication Number Publication Date
WO2009103907A2 WO2009103907A2 (fr) 2009-08-27
WO2009103907A3 true WO2009103907A3 (fr) 2009-10-22

Family

ID=39689404

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/FR2008/001820 Ceased WO2009103907A2 (fr) 2008-01-03 2008-12-23 Procede de gravure localisee de la surface d'un substrat.

Country Status (5)

Country Link
US (1) US8475671B2 (fr)
EP (1) EP2232532A2 (fr)
JP (1) JP5715421B2 (fr)
FR (1) FR2926162B1 (fr)
WO (1) WO2009103907A2 (fr)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
ITBO20120695A1 (it) * 2012-12-20 2014-06-21 Organic Spintronics S R L Dispositivo di deposizione a plasma impulsato
EP3011390B1 (fr) 2013-06-19 2018-02-21 Ev Group E. Thallner GmbH Combinaison d'un tampon et d'une matière d'impression pour la lithographie par impression
US9460997B2 (en) 2013-12-31 2016-10-04 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect structure for semiconductor devices
EP3143401A4 (fr) * 2014-05-15 2017-10-11 Meso Scale Technologies, LLC Méthodes de dosage améliorées
CN104112819B (zh) * 2014-07-17 2017-06-20 东北师范大学 一种有机单晶场效应电路及其制备方法
CN104134749B (zh) * 2014-07-17 2017-03-01 东北师范大学 多层柔性平面内嵌迭片电极及其制备方法与在有机场单晶场效应晶体管中的应用
KR102287811B1 (ko) * 2014-10-31 2021-08-09 삼성전자주식회사 2개 표면을 결합시키는 방법 및 그에 의하여 제조된 구조체, 및 상기 구조체를 포함하는 미세유동 장치
CN110395690A (zh) * 2019-07-15 2019-11-01 北京交通大学 离子束刻蚀聚四氟乙烯材料表面微结构的方法
CN111092148B (zh) * 2019-12-27 2022-08-09 厦门市三安集成电路有限公司 一种压电材料复合基板的制造方法
FR3131433B1 (fr) * 2021-12-29 2023-12-22 Commissariat Energie Atomique Procédé d’activation d’une couche exposée
FR3152189B1 (fr) 2023-08-18 2025-07-18 Commissariat Energie Atomique Procédé de structuration d’un substrat
FR3152190B1 (fr) * 2023-08-18 2025-07-18 Commissariat Energie Atomique Procédé de réalisation de motifs sur un substrat

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060116001A1 (en) * 2002-07-09 2006-06-01 Xiangjun Wang Patterning method
US20070269883A1 (en) * 2006-05-16 2007-11-22 Kathryn Uhrich Micropatterning surfaces

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0091651B1 (fr) * 1982-04-12 1988-08-03 Nippon Telegraph And Telephone Corporation Procédé de réalisation de microimages
US4826564A (en) * 1987-10-30 1989-05-02 International Business Machines Corporation Method of selective reactive ion etching of substrates
US7087444B2 (en) * 2002-12-16 2006-08-08 Palo Alto Research Center Incorporated Method for integration of microelectronic components with microfluidic devices

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060116001A1 (en) * 2002-07-09 2006-06-01 Xiangjun Wang Patterning method
US20070269883A1 (en) * 2006-05-16 2007-11-22 Kathryn Uhrich Micropatterning surfaces

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
KOLARI K ET AL: "Tunable hydrophilicity on a hydrophobic fluorocarbon polymer coating on silicon", JOURNAL OF VACUUM SCIENCE AND TECHNOLOGY: PART A, AVS /AIP, MELVILLE, NY., US, vol. 24, no. 4, 9 June 2006 (2006-06-09), pages 1005 - 1011, XP012091024, ISSN: 0734-2101 *
NOCK V; BLAIKIE R J; DAVID T: "Micro-patterning of polymer-based optical oxygen sensors for lab-on-chip applications", PROCEEDINGS OF THE SPIE - THE INTERNATIONAL SOCIETY FOR OPTICAL ENGINEERING, vol. 6799, 21 December 2007 (2007-12-21), pages 67990Y-1 - 67990Y-10, XP002543150 *

Also Published As

Publication number Publication date
US20110017705A1 (en) 2011-01-27
EP2232532A2 (fr) 2010-09-29
JP2011512646A (ja) 2011-04-21
JP5715421B2 (ja) 2015-05-07
FR2926162A1 (fr) 2009-07-10
FR2926162B1 (fr) 2017-09-01
US8475671B2 (en) 2013-07-02
WO2009103907A2 (fr) 2009-08-27

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