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WO2009140299A2 - Circuit de détection autostabilisateur pour mémoires résistives - Google Patents

Circuit de détection autostabilisateur pour mémoires résistives Download PDF

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Publication number
WO2009140299A2
WO2009140299A2 PCT/US2009/043661 US2009043661W WO2009140299A2 WO 2009140299 A2 WO2009140299 A2 WO 2009140299A2 US 2009043661 W US2009043661 W US 2009043661W WO 2009140299 A2 WO2009140299 A2 WO 2009140299A2
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Prior art keywords
resistance
memory
state
current
circuit
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WO2009140299A3 (fr
Inventor
Jolanta Celinska
Carlos A. Paz De Araujo
Christopher Randolph Mcwilliams
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Symetrix Corp
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Symetrix Corp
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0007—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements comprising metal oxide memory material, e.g. perovskites
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/004—Reading or sensing circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0069—Writing or programming circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0069—Writing or programming circuits or methods
    • G11C2013/0078—Write using current through the cell
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/30—Resistive cell, memory material aspects
    • G11C2213/32—Material having simple binary metal oxide structure

Definitions

  • the invention relates generally to the field of resistive memories, and more particularly to a sensing circuit for such memories.
  • RRAM variable resistance memory
  • Typical materials vary and include GeSbTe, where Sb and Te can be exchanged with other elements of same properties on the periodic table. These materials are often referred to as chalcogenides. See, for example, Stephan Lai, "Current Status of the Phase Change Memory and Its Future", Intel Corporation,
  • variable resistance memory category includes materials that require an initial high "forming" voltage and current to activate the variable resistance function. These materials include Pr x Ca y Mn z O ⁇ , with x, y, z and e of varying stoichiometry, transition metal oxides, such as CuO, CoO, VO x , NiO, TiO 2 , Ta 2 Os, and some perovskites such as Cr; SrTi ⁇ 3. See, for example, "Resistive Switching Mechanisms Of TiO 2 Thin Films Grown By Atomic-Layer Deposition", B. J.
  • a suggested solution to the above problem for a resistance memory depends on filaments created by a forming circuit has been to use a limit the current using the saturation current of a MOSFET (metal oxide semiconductor field effect transistor). See “Sub-100- ⁇ A Reset Current of Nickel Oxide Resistive Memory Through Control of Filamentary Conductance by Current Limit of MOSFET", Yoshihiro Sato et al., IEEE Transactions on Electron Devices, Vol. 55, No. 5, May 2008, pp. 1 185-87.
  • the saturation current of a MOSFET is itself dependent on many variables.
  • the resistance change of the filament-type circuit is not as large as other resistance memories.
  • a current limiting transistor is utilized to regulate the current in the variable resistor.
  • a Wheatstone bridge is incorporated into the sensing circuit.
  • the memory is a chain cell memory with a Wheatstone bridge circuit provided for each column of the memory.
  • the resistance element in each cell forms one leg of the Wheatstone bridge.
  • resistance of the access resistor also is incorporated into this leg of the bridge.
  • the invention provides an integrated circuit resistance memory comprising: a memory cell comprising a variable resistance element capable of having a low resistance state and a high resistance state; and a sensing circuit for sensing the resistance of the variable resistance element; the resistance memory characterized by a current regulating circuit interconnected with the resistive switching cell, the current regulating circuit regulating the current through the resistance so that sufficient current to the resistance to switch the resistance when it is in the high resistance state and the current applied in the low resistance state is sufficiently limited to prevent damage to the variable resistance.
  • the current regulating circuit comprises a transistor.
  • the current regulating circuit includes a parameter analyzer for measuring an electrical parameter applied to the resistor.
  • the current regulating circuit comprises a Wheatstone bridge.
  • the variable resistance element comprises a correlated electron material.
  • the invention also provides a method of reducing reset current in a resistive memory, the method comprising: providing a resistive memory having a memory cell comprising a variable resistance element capable of having a low resistance state and a high resistance state; applying a reset voltage to the variable resistance element to change it from the low resistance state to the high resistance state; and applying a set voltage to the variable resistance element to change it from the high resistance state to the low resistance state; the method characterized by regulating the current flow through the variable resistance element so that sufficient current is applied to the resistance to switch the resistance when it is in the high resistance state and the current applied in the low resistance state is sufficiently limited to prevent damage to the variable resistance.
  • the regulating comprises adjusting the voltage across the variable resistance.
  • the regulating comprises limiting the current with a current limiting transistor.
  • the invention further provides a method of preventing snapback in a correlated electron random access memory cell, the method comprising: switching a resistive switching cell by applying a set-point voltage, wherein the resistive switching cell includes a correlated electron material (CEM), wherein the resistive switching cell is in a high resistance state before the switching and in a low resistance state after the switching; the method characterized by scaling the variable resistance element to reduce parasitic capacitance without significantly changing the resistance.
  • CEM correlated electron material
  • the invention also provides and integrated circuit resistance memory comprising: a memory cell comprising a variable resistance element capable of having a low resistance state and a high resistance state; and a sensing circuit for sensing the resistance of the variable resistance element; the resistance memory characterized by the sensing circuit comprising a Wheatstone bridge circuit; wherein the variable resistance element in the memory cell is electrically connectable to provide at least a portion of the resistance in one leg of the Wheatstone bridge circuit.
  • the variable resistance element comprises a correlated electron material.
  • the Wheatstone bridge comprises: a first leg and a second leg; the first leg having a first resistance, a second resistance, and a first node located between the first and second resistances, the first and second resistances being balanced; and the second leg including a resistance element and a third resistance, wherein RmO « R3 « Rm1 , where RmO is the resistance of the variable resistance element in the low resistance state and Rm1 is the resistance of the resistance element in the high resistance state.
  • the sensing circuit further comprises a shunt electrically connected in parallel with one leg of the Wheatstone bridge.
  • the shunt comprises an electronic component selected from the group consisting of a Schottky diode, a PN junction diode and a transistor.
  • the invention also provides a method of reading a resistance memory having a variable resistance element capable of existing in a low resistance state and a high resistance state, the method comprising: providing a Wheatstone bridge circuit having a first leg and a second leg; the first leg having a first resistance, a second resistance, and a first node located between the first and second resistances, the first and second resistances being balanced; and a second leg including the variable resistance element, a third resistance, and a second node located between the variable resistance element and the third resistance, wherein RmO « R3 « Rm1 , where RmO is the resistance of the resistance element in the low resistance state and Rm 1 is the resistance of the resistance element in the high resistance state; and reading the state of the variable resistance element by sensing an electrical parameter across the first node and the second node.
  • a method of preventing snapback in a correlated electron random access memory cell includes switching a resistive switching cell by applying a set-point voltage.
  • the resistive switching cell includes a correlated electron material (CEM).
  • CEM correlated electron material
  • the resistive switching cell is in a second state and in the second state the resistive switching cell has dielectric characteristics before the switching and in a first state exhibiting conductive characteristics after the switching.
  • the method further includes regulating the current applied to the resistive switching cell to maintain a low current level, such that during the second state the capacitance of the resistive switching cell in minimized.
  • the regulating of is accomplished using a transistor.
  • the resistive switching cell is designed in order to minimize the dielectric capacitance.
  • the size of the CEM material is minimized in order to reduce the dielectric capacitance.
  • the CEM material is approximately 100 micrometers squared.
  • FIG. 1 is a diagram a CeRAM memory cell with current compliance
  • FIG. 2 is a graph of CEM scaling and compliance
  • FIG. 3 is one embodiment of a 1T1 R NiO-CeRAM circuits
  • FIG. 4 is a graph of current vs. voltage for a 1T1 R CeRAM circuit
  • FIG. 5 is a diagram of a circuit diagram for a Wheatstone bridge
  • FIG. 6a shows the current in amperes versus bias voltage in volts curves for an NiO resistor
  • FIG. 6b is the same curves as shown in FIG. 6a except on a logarithmic scale which shows higher resolution at the smaller values of current;
  • FIG. 7a illustrates a silicon wafer with CEM "elements” comprising a CEM material sandwiched between two electrodes;
  • FIG. 7b shows a cross-sectional view of one of the "elements" of
  • FIG. 7a taken through the line 4-4 of FIG. 7a;
  • FIG. 8 shows an idealized current versus voltage curve for a resistive switching film with unipolar switching, illustrating the ON, OFF, RESET, and SET modes
  • FIG. 9 is an illustration of the energy bands of a Mott-Hubbard insulator taken from Introduction to the Electron Theory of Metals by Uichiro Mizutani;
  • FIG. 10 is a logic circuit diagram for an application of the CeRAM and Wheatstone Bridge
  • FIG. 1 1 is a logic circuit diagram for an application of the CeRAM and Wheatstone Bridge
  • FIG. 12 is a diagram of an array of logic circuits
  • FIG. 13 is a memory cell including a variable resistor and a transistor;
  • FIG. 14 is an example of an array of memory cells;
  • FIG. 15 is a graph of current vs. voltage for a 5um x 5um CeRAM;
  • FIG. 16 is a graph of the ON state resistance and OFF state resistance versus number of read/write cycles for a CeRAM memory element;
  • FIG. 17(a) illustrates one embodiment of a modified Wheatstone bridge circuit utilizing a pn-diode shunt;
  • FIG. 17(b) illustrates one embodiment of a modified Wheatstone bridge circuit utilizing a Shottky diode shunt
  • FIG. 18 is a hysteresis curve showing voltage versus current for a CeRAM memory element in the configuration of FIG. 17(b);
  • FIG. 19 is a hysteresis curve showing voltage versus current for a CeRAM memory element in the configuration of FIG. 17(a);
  • FIG. 20 is a graph of voltage versus current showing a SET pulse with a Wheatstone bridge current limiting circuit
  • FIG. 21 is a graph of voltage versus current showing a RESET pulse with a
  • FIG. 22 is a circuit diagram for one embodiment of a Wheatstone bridge with a NMOS.
  • the resistance value tells if we have a logical "1 " or "0". When we have a Logical “0” the resistance is very low and behaves as an electrical short circuit. When we have a logical “1 " the resistance is very high and behaves as an electrical open circuit.
  • the challenge is to implement a self-stabilizing sensing circuit that is also capable of limiting the current across the device during a write operation. For the purposes herein, the discussion will focus on, but is not limited to, the CeRAM device. 1.1. CeRAM Device Requirements
  • FIG. 1 shows an example of a configuration of a compliance circuit for a CEM memory device, TMO MIM cell 10.
  • a parameter analyzer 13 analyzes the incoming parameters and sends a response signal 14 accordingly by managing the resistance of the variable resistance resistor 17.
  • This current compliance mechanism is implemented in order to manage parasitic capacitance 16 resulting from cables and probes as well as dielectric capacitance in off state that causes a current "snapback" during set of the CEM material 15.
  • the scaling of the device will minimize parasitic capacitance while the on resistance stays constant. Good current compliance is needed for repeatable CEM operation.
  • the reset current may be controlled by imposing current compliance using a cell transistor. Reducing the stray capacitance between Pt/NiO/Pt and the cell transistor used as a current limiter may be desirable.
  • the parameter analyzer analyzes the current (and optionally the voltage) being applied to the circuit and adjusts the variable resistor accordingly in order to enable a low reset current for the CEM device.
  • FIG. 2 shows the results of scaling the CEM device to a very small size and applying a compliance mechanism.
  • a current compliance limit designated lcomp(A) the reset current of the CEM device can be reduced.
  • the size of the CEM device affects the achievable reset current.
  • a lower reset current can be achieved by imposing current compliance for a CEM device of 10um by 10um as compared to a 20um device.
  • FIG. 3 shows one embodiment of a 1T1 R CeRAM circuit including a transistor 32 and a CeRAM memory cell 31. It is of note that stray capacitance between Pt/NiO/Pt and a transistor in forms another current path which causes additional current, since it becomes short at the moment that the "forming" or "set” process takes place.
  • Ireset ⁇ lcomp means that the point 35, at which the "reset" process takes place, approaches to the point 34. Namely, additional current caused by an insufficient current limit results in notable difference between Ireset and lcomp observed before.
  • the dependence Ireset-lcomp characteristic is dependent on the stray capacitance between Pt/NiO/Pt and a transistor. Asymptotical approach of Ireset to lcomp with decreasing the stray capacitance enables low Ireset and the multi-level application of CeRAM possible. 1.4. Wheatstone Bridge
  • FIG. 5 shows the basic circuit diagram of the Wheatstone bridge.
  • output v1 is a output 23 and output v2 is at output 26.
  • a voltage source 21 provide voltage to the circuit.
  • Resistors, 22, 24, 25, 20 control the output Vout
  • the CeRAM resistor is resistor 20, however it could be located at any of the resistor areas.
  • NiO(Lx) a ligand element or compound
  • x indicates the number of units of the ligand for one unit of NiO.
  • One skilled in the art can determine the value of x for any specific ligand and any specific combination of ligand with NiO or any other transition metal, simply by balancing valences.
  • the preferred NiO variable resistance materials disclosed herein include at least a ligand containing carbon, which may indicated by NiO(Cx).
  • a Correlated Electron Material is a material that switches from a first resistive state to a second resistive state, with the second resistive state having a resistance at least one hundred times higher than the first resistance state, and the change in resistance is primarily due to correlations between the electrons.
  • the resistance of the second state is at least two hundred times the resistance of the first state, and most preferably, five hundred times.
  • these materials include any transition metal oxide, such as perovskites, Mott insulators, charge exchange insulators, and Anderson disorder insulators.
  • transition metal oxide such as perovskites, Mott insulators, charge exchange insulators, and Anderson disorder insulators.
  • Several embodiments representing switching materials are nickel oxide, cobalt oxide, iron oxide, yttrium oxide, and perovskites such as Cr doped strontium titanate, lanthanum titanate, and the manganate family including praesydium calcium manganate and praesydium lanthanum manganate.
  • oxides incorporating elements with incomplete d and f orbital shells exhibit CEM resistive switching properties.
  • resistance can be changed by setting at one voltage and resetting at a second voltage.
  • no electroforming is required to prepare a CEM.
  • transition metal compounds can be used.
  • M can be Pt, Pd, or Ni
  • chxn is 1 R,2R- cyclohexanediamine
  • other such metal complexes may be used.
  • G (q2pmpNiO/hm)T, where q is the electron charge, pm is the density of states in the electrode, pNiO is the density of states in the nickel oxide, m is the mass of the charge carrier, and T is the transmission probability through the film.
  • CEM memory materials A number of advances to the technology of CEM materials is explained below. Briefly, these advances relate to a number of aspects of CEM memory materials. The discussion herein, includes, but is not limited to the following advances: the usage of a capping layer, annealing in methane, filamentary carbon in the surface, the usage of a graded extrinsic ligand, and the choice of electrodes.
  • FIG. 6a shows the current in amperes (amps) versus bias voltage in volts curves for an NiO(Cx) CEM.
  • FIG. 6b shows the same curves except the absolute value of the current is plotted logarithmically to show more detail in the low current values.
  • RESET point the point at which the CEM changes in resistance from a conductor to an insulator
  • SET point the point at which the resistance changes from an insulator to a conductor
  • the CEMs are crystallized in the conducting state. We shall refer to this as the ON state and the insulative state will be called the OFF state.
  • the solid line 40 is the ON state curve for positive voltages and the solid line 60 is the ON curve for negative voltages.
  • the dotted line 54 is the OFF curve for positive voltages, while the dotted line 62 is the OFF curve for negative voltages.
  • the current rises at 47, until the RESET voltage is reached, which is about 0.65 volts, which is also the point at which critical electron density is reached, then, at point 48 the material suddenly becomes insulative and the current drops sharply along curve 49.
  • the current stays low along the line 52 as the voltage rises until the SET voltage is reached at about 1.65 volts, which corresponds to the Neel temperature for these materials, at which point the material again becomes conductive and the current rises along line 54.
  • FIG. 7a and 7b a silicon wafer 1 having CEM integrated circuit elements, such as 77 and 80 formed on it is shown.
  • FIG. 7b shows a cross- section through element 80 taken through line 4-4 of FIG. 7a.
  • Element 80 is formed on a silicon substrate 82 having a silicon dioxide coating 84.
  • a thin layer 86 of titanium or titanium oxide may be formed on oxide layer 84, though the elements reported on herein did not have such a layer.
  • a bottom electrode layer 88 is formed on either layer 86 or directly on oxide layer 84.
  • Layer 86 is an adhesion layer to assist the bottom electrode layer 88 in adhering to silicon dioxide layer 84.
  • CEM material 90 (composed of a transition metal oxide is formed on bottom electrode 88, preferably by a liquid deposition process, such as spin coating, misted deposition, CVD or atomic layer deposition. The deposition of the CEM material will be described in greater detail below.
  • top electrode 92 is formed on CEM layer 90.
  • the elements 77, 80, etc. are then patterned by etching down to bottom electrode 88.
  • the CEM material is subjected to a recovery annealing.
  • an inter-layer dielectric 94 is deposited. At this point a contact vias 96 is added.
  • CEM integrated circuit elements such as interconnect metallization, further interconnection etching, passivation, etc.
  • interconnect metallization such as interconnect metallization, further interconnection etching, passivation, etc.
  • passivation such as interconnect metallization, interconnection etching, passivation, etc.
  • the CEM integrated circuit element appears to have no fundamental issues with mainstream metallization processes and materials that are know to those skilled in the art.
  • the bottom electrode layer 88 may be formed of Titanium Nitride (TiN) and Tungsten (W).
  • the electrode is formed with a layer of TiN, followed by a layer of W, followed by a layer of TiN.
  • the bottom electrode layer 88 is formed by a 200 angstrom layer of TiN, a 200 angstrom layer of W, and a 200 angstrom layer of TiN.
  • the top electrode layer 92 may be formed of Titanium Nitride (TiN) and
  • the electrode is formed with a layer of TiN, followed by a layer of Al, followed by a layer of TiN.
  • the top electrode layer 92 is formed by a 200 angstrom layer of TiN, a 200 angstrom layer of Al, and a 200 angstrom layer of TiN.
  • the bottom electrode layer 88 and the top electrode layer 92 may be formed of platinum.
  • a stack configuration of Si/SiO2/TiOx/Pt/NiO/Pt is used.
  • the top and bottom electrodes are formed of platinum (top electrode 92 and bottom electrode 88).
  • the adhesion layer 86 is titanium oxide.
  • a stack configuration of Si/SiO2/ Pt/NiO/Pt is used, omitting the adhesion layer 86.
  • a top layer of TiN may be deposited over layer 92. This top layer is used as a hard mark. It may be in a range of thicknesses from 10nm to 200nm. In one alternative it is 60 nm thick.
  • the various elements 77, 88 can then be tested by attaching one probe to platinum surface 88 and touching a fine probe to the top electrode, such as 92, of the element to be tested, such as 80.
  • the various curves discussed below were generated in this manner.
  • FIG. 1 the term "metal" when referring to an electrode or other wiring layer generally means a conductor. As known in the art, such "metal" electrodes and/or wiring layers can be made of polysilicon or other conductive material and are not necessarily made of metal.
  • FIG. 8 shows an idealized current versus voltage curve for a resistive switching film with unipolar switching, to better illustrate the ON, OFF, RESET, and SET modes.
  • the material is crystallized in the ON state and the current rises along the ON curve as voltage is increased up VRESET. The current then drops to the OFF curve and increases gradually along the OFF curve until VSET is reached, at which point it increases toward the ON curve. However, in devices, the current is limited the dotted line, lset to prevent overcurrent. The read and write margins are shown in the figure. As shown by FIG. 8, the NiO(Cx) films follow these idealized curves better than any prior art material.
  • ligands may be less useful than others because they are not stabilizing under all circumstances.
  • ligands stabilize the orbital valence states, and particularly the 3d orbital states.
  • the complex [Ti(H2O)6]3+ is not stabilizing for conventional CMOS processing because when it is annealed the water evaporates leaving uncompensated titanium, which can take many different valence states. Such a material will require electroforming. However, it can be stabilizing in other processes.
  • the preferred ligands comprise one or more elements selected from the group consisting of oxygen, hydrogen, fluorine, carbon, nitrogen, chlorine, bromine, sulphur, and iodine.
  • Some useful ligands for various metals are shown in Table I. In this table, the metal of interest is given in bold, followed by the formula for the complex the metal forms with the ligand of interest.
  • Ligand field theory was developed in the 1930's and 1940's as an extension of crystal field theory. See for example, "Ligand Field Theory" in Wikepedia, the free encyclopedia at http://en.wikipedia.org/wik/Ligand _field theory, which is incorporated by reference herein to the same extent as though fully disclosed herein.
  • ⁇ O the energy difference between certain molecular orbitals
  • This size of this energy difference, ⁇ O determines the electronic structure of d orbitals.
  • the stability of the memory window between the OFF state and the on state is substantially proportional to the stability of ⁇ O.
  • the preferred dopant ligands are those which result in a large and stable ⁇ O.
  • Some useful dopant ligands in descending order of the size of the ⁇ O they create are: CO, CN-, PPh3, N02-, phen (1 ,10-phenanthroline, biby (2,2'-bipyridine), en (enthylenediamine), NH3, py (pyridine), CH3CN, NCS-, H20, C2O42-, OH-, F-, N3-, N03-, Cl-, SCN-, S2-, Br-, and I-.
  • the crystal field splitting energy ( ⁇ O) is not directly related to the Mott-charge transfer barrier or the Rice-Bhckman mass.
  • the stability of the metal-native ligand coordination sphere allows the electron-electron correlations inductive of these transitions to occur in a particular material as the nuances of the bonding and crystal structures are set in place.
  • the technical relevant effect is to control or stabilize the oxidation number (or coordination sphere) in such a way the local stoichiometry is "nominal" or otherwise suitable to induce the necessary electron correlation conditions.
  • Extrinsic ligand or “dopant ligand” is defined herein to be the ligand material added to transition metal complexes to stabilize the multiple valence states of the transition metals.
  • the ligand splits the d-orbitals.
  • extrinsic or “dopant” because the ligand complex is an extrinsic material added to the lattice that is not intrinsic to the lattice structure of the transition metal compound.
  • the oxygen is an intrinsic ligand
  • (CO)4 in forming Ni(CO)4, is the extrinsic ligand.
  • Ni5(CO)12 nickel carbonate
  • other variants such Ni5(CO)12 (nickel carbonate) include a form of CO as extrinsic ligands to the basic NiO lattice.
  • dopant in semiconductor technology adding a dopant to silicon, for example, does not change the silicon so much that we refer to it as another compound.
  • the dopant ligand added to say, nickel oxide does not change the fact that the material is nickel oxide.
  • the d-orbital thus behaves much like a metal, and the material is conducting. As the density of electrons becomes large, differences occur. When ⁇ t is larger then U, the d-orbitals split into a pair of separated bands 189 and 190, and the p-orbital 188 remains below the d-orbital bands. When ⁇ t is smaller than U, the p-orbital of the intrinsic ligand splits the d- orbital which tends to stabilize the d-orbital valence, yielding a net oxidation state of zero, for example, Ni+20-2. In such conditions, the insulator is a charge-transfer insulator, which leads to lower operating voltages.
  • this material will be an insulator with high resistance when the lower voltage induces a metal to insulator transition purely caused by increasing the local density of electrons.
  • the electric field created by the applied voltage becomes large enough, some electrons will begin to jump to the upper band 196. This creates an overlap of the upper empty band and lower filled d- bands, the condition of a highly conductive state with small coulomb repulsion, and the system collapses back to the state shown at the left in FIG. 9. From FIG.
  • transitions can be made from the p-orbital to the d-orbital which create "holes", which can be filled by electrons from filled d-bands.
  • the interaction of d-d orbital transitions is highly dependent on the existence of p-orbitals in these CEM compounds.
  • the absence of an oxygen atom in the lattice induces a +2 charge, i.e., a doubly charged vacancy, which would be neutralized if the oxygen would return with its -2 valence.
  • the Ni or other transition metal no longer coordinates or bonds normally with the oxygen, thus, the emission of up to two electrons into this positive potential, makes the Ni become +4, with the result that it is no longer useful for a Mott or charge transfer condition. It is at this point that mediation between the defect and an extrinsic ligand, re-establishes the oxidation state of the nickel. Without the ligand, the unbalanced, unstable insulative state is either heavily saturated with coordination destroying oxygen vacancies or equally detrimental and related excess nickel anions in interstitial sites in the lattice.
  • the metal-ligand-anion (MLA) bond which stabilizes the correlated electron material in some embodiments can be formed in many ways.
  • the CEMs may be annealed in a gas that contains the ligand chemical element, the anion element, and preferably also includes both the ligand element and the anion. Any gas incorporating any of the ligands above may be used. The gas may be formed through conventional precursor vaporization processes, such as heating and bubbling. As another example, the CEM may be reactive sputtered in a gas containing the ligand chemical element, the anion or both. Again, any of the ligands above may be used. As an example, for NiO, with a carbon ligand and an oxygen anion, CO and CO2 are possible annealing gases.
  • the anneal may be performed with one or more of these gases, or may be performed in a mixture of an inert gas, such as argon or nitrogen, with the gas containing either the ligand element, the anion element, or both.
  • an inert gas such as argon or nitrogen
  • Alternative explanations for the experimentally observed phenomenon may be available.
  • the resistance value tells if we have a logical "1 " or "0.” When we have a logical "0" the current is too high because the resistor is basically a short circuit (-60 ⁇ ). Current must be limited and the state detected at the same time.
  • R 2 FET circuit that provides a variable resistance, resistor 25
  • R x Resistor from the resistive memory array (of any architecture), resistor 20
  • V 2 ⁇ O ⁇ V 2 "V
  • R 1 could be set as equal to R Conductne - But that would be a high current and high power.
  • the truth table would be:
  • ⁇ R 2 is a function of the gate voltage of the FET (and peripheral biasing circuits). According to this embodiment, the swings in ⁇ R 2 and ⁇ R x are limited by the
  • each intersection point is a CeRAM memory cell.
  • each cell includes a variable resistor and a transistor.
  • FIG. 13 An example of such a configuration is shown in FIG. 13, where column 1310 represents the column, row 1340 represents the row, 1320 is a transistor, and 1330 is a variable resistor (CeRAM cell).
  • a row may have only 8 cells, i.e., there are 8 columns in a row. In a commercial example, there would clearly be exponentially more cells.
  • FIG. 14 shows an example of a memory unit with 8 cells. Each cell includes sense amplifiers 1445 (or Row Buffer), a bridge 1440 (Wheatstone bridge, see above FIG. 5 for more detail) and incoming voltage 1435 is "R 2 " or the voltage in the FET circuit which yields a resistance value.
  • Resistor 1430 is the variable resistor (CeRAM) corresponding to each column, e.g. Rx(i, 1 ), Rx(i, 2)... Rx(i, 8).
  • Row 1420 is denoted by i in the present example and the corresponding column is from 1-8 (Rx (row, column)).
  • Figure 14 can be easily generalized for N-cells.
  • V F FET circuit control voltage
  • R- l dI Ds /d V Ds
  • V Row turns on every "FET" in row
  • R 1 , R 3 or even R 2 can be put into each bridge to correct for the voltage drop. That is, in the chain cell memory, each time a cell further down the chain is read or written to, there is an additional resistance, i.e., the resistance of the access transistors above the cell in the column, that is added to the resistance of the variable resistance R x (i, j) of the cell.
  • the size of the memory window and the ability to set R 1 , R 3 , and R 2 provide sufficient flexibility in the design, that the voltage drop across the access transistors will not affect the ability to read and write to each cell in the column.
  • a bit counting circuit can keep track of which cell along a column is being read or written to, and the voltage Vcoiu mn can be adjusted to account for the voltage drop along the access transistors.
  • the read operation is so fast that a read can be performed before writing to a cell, and the cell is written to only if the state of the cell is different from the state to be written. Thus, the cell is not continually rewritten to the same state. This prevents imprinting of the cell.
  • a typical 5_m x 5_m CeRAM structure with Hysteresis shown in FIG. 15 was used to test the feasibility of using a self stabilizing Wheatstone bridge circuit to program the state as well as provide a reliable means to read the state of a CeRAM memory cell.
  • the ratio of Ron/Rofffor a 5um x 5um CeRAM cell (Rm) is approximately 1/10000. This ratio is used to determine the appropriate value for R3 which for this case was chosen to be 2k ⁇ . This value for R3 provides adequate series resistance for limiting the current of a Set operation as well as meet the requirements outlined in the previous section for maximum Vout.
  • the circuit includes a voltage source 1710, resistors, 1715, 1720, 1725, v1 output 1735 and v2 output 1740, CeRAM 1730, and pn-junction diode 1745.
  • the circuit includes a voltage source 1710, resistors, 1715, 1720, 1725, v1 output 1735 and v2 output 1740, CeRAM 1730, and Schottsky diode 1745.
  • the diode circuit successfully performs as a shunt leg to meet the basic requirements of the CeRAM, it also introduced two new factors into the behavior of the circuit. Firstly, by using the diode in the circuit it became necessary to use positive and negative voltages to switch the CeRAM from state to state. Though this is very doable, it would increase the complexity of the design of the peripheral drive circuitry needed for a memory array. Secondly, the threshold voltage in the diode, though relatively small, is large enough to increase the voltage necessary in performing a reset operation, closing the write margin. As a solution to the issues presented by the diode circuit, an n-channel
  • MOSFET transistor was used as the shunt device. From the circuit in FIG. 22, it was possible to hold the gate at a bias allowing current to flow between the source and drain of the transistor during a reset operation, and also bring the gate to ground pinching off current flow and forcing the current to move through R3for a set operation. With this configuration and the appropriate timing circuits, it was possible to achieve a hysteresis closely resembling that of Figure 15.
  • the circuit includes a voltage source 2210, resistors, 2215, 2220, 2225, v1 output 2235 and v2 output 2240, CeRAM 2230, and n-channel MOSFET transistor 2245.

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  • Chemical & Material Sciences (AREA)
  • Engineering & Computer Science (AREA)
  • Materials Engineering (AREA)
  • Semiconductor Memories (AREA)

Abstract

L'invention porte sur une mémoire résistive à circuit intégré qui comprend: une cellule mémoire renfermant un élément à résistance variable capable d'adopter un état de faible résistance et un état de résistance élevée; et un circuit de détection destiné à détecter la résistance de l'élément à résistance variable; le circuit de détection comprenant un circuit à pont Wheatstone, et l'élément à résistance variable contenu dans la cellule mémoire pouvant être électriquement relié à une branche du circuit à pont Wheatstone afin de fournir au moins une partie de la résistance.
PCT/US2009/043661 2008-05-12 2009-05-12 Circuit de détection autostabilisateur pour mémoires résistives Ceased WO2009140299A2 (fr)

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