[go: up one dir, main page]

WO2009037731A1 - 翻訳装置と翻訳方法および翻訳プログラムとプロセッサコアの制御方法およびプロセッサ - Google Patents

翻訳装置と翻訳方法および翻訳プログラムとプロセッサコアの制御方法およびプロセッサ Download PDF

Info

Publication number
WO2009037731A1
WO2009037731A1 PCT/JP2007/001028 JP2007001028W WO2009037731A1 WO 2009037731 A1 WO2009037731 A1 WO 2009037731A1 JP 2007001028 W JP2007001028 W JP 2007001028W WO 2009037731 A1 WO2009037731 A1 WO 2009037731A1
Authority
WO
WIPO (PCT)
Prior art keywords
translating
parallel
processor
code
control
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2007/001028
Other languages
English (en)
French (fr)
Inventor
Koichiro Yamashita
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP2009532967A priority Critical patent/JP5067425B2/ja
Priority to PCT/JP2007/001028 priority patent/WO2009037731A1/ja
Priority to EP07805864A priority patent/EP2202638A4/en
Publication of WO2009037731A1 publication Critical patent/WO2009037731A1/ja
Priority to US12/726,526 priority patent/US8543993B2/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F8/00Arrangements for software engineering
    • G06F8/40Transformation of program code
    • G06F8/41Compilation
    • G06F8/45Exploiting coarse grain parallelism in compilation, i.e. parallelism between groups of instructions
    • G06F8/451Code distribution
    • G06F8/452Loops
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F8/00Arrangements for software engineering
    • G06F8/40Transformation of program code
    • G06F8/41Compilation
    • G06F8/44Encoding
    • G06F8/443Optimisation
    • G06F8/4432Reducing the energy consumption
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46Multiprogramming arrangements
    • G06F9/50Allocation of resources, e.g. of the central processing unit [CPU]
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02DCLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00Energy efficient computing, e.g. low power processors, power management or thermal management

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Power Sources (AREA)
  • Devices For Executing Special Programs (AREA)
  • Multi Processors (AREA)

Abstract

 複数のプロセッサから構成されるシステムやマルチコアプロセッサチップにより並列処理を行う場合に、並列処理を行うプロセッサ数および各プロセッサの動作クロックを動的に変更することにより消費電力を低減可能とする技術を提供する。ソースコードから、予め設定された繰り返し回数だけ内部処理を実行するループ処理コードであり、繰り返しごとに実行される前記内部処理に互いに依存関係がない、並列処理可能な並列ループ処理コードを検出する並列ループ処理検出部と、並列ループ処理コードにおける前記繰り返し回数を制御するための制御コア用コードと、該制御コア用コード側からの制御に対応して繰り返し回数を変更するための並列処理用コードとを生成する動的並列変換部と、を具備する翻訳装置である。また、翻訳方法および翻訳プログラムとプロセッサコアの制御方法およびプロセッサである。
PCT/JP2007/001028 2007-09-21 2007-09-21 翻訳装置と翻訳方法および翻訳プログラムとプロセッサコアの制御方法およびプロセッサ Ceased WO2009037731A1 (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP2009532967A JP5067425B2 (ja) 2007-09-21 2007-09-21 翻訳装置と翻訳方法および翻訳プログラムとプロセッサコアの制御方法およびプロセッサ
PCT/JP2007/001028 WO2009037731A1 (ja) 2007-09-21 2007-09-21 翻訳装置と翻訳方法および翻訳プログラムとプロセッサコアの制御方法およびプロセッサ
EP07805864A EP2202638A4 (en) 2007-09-21 2007-09-21 TRANSLATION FACILITY, TRANSLATION PROCEDURE AND TRANSLATION PROGRAM AND PROCESSOR CONTROL SYSTEM AND PROCESSOR
US12/726,526 US8543993B2 (en) 2007-09-21 2010-03-18 Compiler, compile method, and processor core control method and processor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2007/001028 WO2009037731A1 (ja) 2007-09-21 2007-09-21 翻訳装置と翻訳方法および翻訳プログラムとプロセッサコアの制御方法およびプロセッサ

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US12/726,526 Continuation US8543993B2 (en) 2007-09-21 2010-03-18 Compiler, compile method, and processor core control method and processor

Publications (1)

Publication Number Publication Date
WO2009037731A1 true WO2009037731A1 (ja) 2009-03-26

Family

ID=40467564

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2007/001028 Ceased WO2009037731A1 (ja) 2007-09-21 2007-09-21 翻訳装置と翻訳方法および翻訳プログラムとプロセッサコアの制御方法およびプロセッサ

Country Status (4)

Country Link
US (1) US8543993B2 (ja)
EP (1) EP2202638A4 (ja)
JP (1) JP5067425B2 (ja)
WO (1) WO2009037731A1 (ja)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2012008019A1 (ja) * 2010-07-13 2012-01-19 富士通株式会社 情報処理装置、情報処理装置の制御方法及びプログラム
EP2519876A1 (en) * 2009-12-28 2012-11-07 Hyperion Core, Inc. Optimisation of loops and data flow sections
JP2013500515A (ja) * 2009-07-21 2013-01-07 マイクロソフト コーポレーション コンポーネントの電力監視およびワークロードの最適化
JP2013041437A (ja) * 2011-08-17 2013-02-28 Nec Corp 計算装置、計算装置の制御方法、及びプログラム
JP2015022574A (ja) * 2013-07-19 2015-02-02 富士通株式会社 並列処理最適化プログラム、並列処理最適化方法および情報処理装置
JP2017102790A (ja) * 2015-12-03 2017-06-08 富士通株式会社 情報処理装置、演算処理装置および情報処理装置の制御方法

Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7840914B1 (en) * 2005-05-13 2010-11-23 Massachusetts Institute Of Technology Distributing computations in a parallel processing environment
US9672019B2 (en) 2008-11-24 2017-06-06 Intel Corporation Systems, apparatuses, and methods for a hardware and software system to automatically decompose a program to multiple parallel threads
US9189233B2 (en) 2008-11-24 2015-11-17 Intel Corporation Systems, apparatuses, and methods for a hardware and software system to automatically decompose a program to multiple parallel threads
US10621092B2 (en) 2008-11-24 2020-04-14 Intel Corporation Merging level cache and data cache units having indicator bits related to speculative execution
US8726251B2 (en) * 2011-03-29 2014-05-13 Oracle International Corporation Pipelined loop parallelization with pre-computations
US9417855B2 (en) 2011-09-30 2016-08-16 Intel Corporation Instruction and logic to perform dynamic binary translation
US20120185714A1 (en) * 2011-12-15 2012-07-19 Jaewoong Chung Method, apparatus, and system for energy efficiency and energy conservation including code recirculation techniques
US9262139B2 (en) * 2013-01-07 2016-02-16 Advanced Micro Devices, Inc. Layered programming for heterogeneous devices
US9335803B2 (en) * 2013-02-15 2016-05-10 Intel Corporation Calculating a dynamically changeable maximum operating voltage value for a processor based on a different polynomial equation using a set of coefficient values and a number of current active cores
KR20140103569A (ko) * 2013-02-18 2014-08-27 한국전자통신연구원 적응적 계층 선택을 위한 장치 및 방법, 이를 구비한 서버
US9880842B2 (en) 2013-03-15 2018-01-30 Intel Corporation Using control flow data structures to direct and track instruction execution
US9891936B2 (en) 2013-09-27 2018-02-13 Intel Corporation Method and apparatus for page-level monitoring
JP2016532183A (ja) * 2013-10-03 2016-10-13 華為技術有限公司Huawei Technologies Co.,Ltd. ソフトウェアプログラムの計算ブロックをマルチプロセッサシステムのコアに割り当てるための方法及びシステム
US10326448B2 (en) 2013-11-15 2019-06-18 Scientific Concepts International Corporation Code partitioning for the array of devices
US9294097B1 (en) 2013-11-15 2016-03-22 Scientific Concepts International Corporation Device array topology configuration and source code partitioning for device arrays
US9698791B2 (en) 2013-11-15 2017-07-04 Scientific Concepts International Corporation Programmable forwarding plane
US10282275B2 (en) 2016-09-22 2019-05-07 Microsoft Technology Licensing, Llc Method and system for managing code
US10372441B2 (en) 2016-11-28 2019-08-06 Microsoft Technology Licensing, Llc Build isolation system in a multi-system environment
US11614941B2 (en) * 2018-03-30 2023-03-28 Qualcomm Incorporated System and method for decoupling operations to accelerate processing of loop structures
CN115291958B (zh) * 2022-10-10 2022-12-27 广州市保伦电子有限公司 一种主控与外围芯片的更换方法及装置

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02132526A (ja) * 1988-11-14 1990-05-22 Hitachi Ltd 並列計算機の処理平準化方法および自動並列化コンパイル方法

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6367071B1 (en) * 1999-03-02 2002-04-02 Lucent Technologies Inc. Compiler optimization techniques for exploiting a zero overhead loop mechanism
US7140010B2 (en) * 2001-03-30 2006-11-21 Sun Microsystems, Inc. Method and apparatus for simultaneous optimization of code targeting multiple machines
JP3801545B2 (ja) * 2002-08-02 2006-07-26 松下電器産業株式会社 コンパイラ用プログラム、コンパイラ装置及びコンパイル方法
US7093147B2 (en) * 2003-04-25 2006-08-15 Hewlett-Packard Development Company, L.P. Dynamically selecting processor cores for overall power efficiency
US7171544B2 (en) * 2003-12-15 2007-01-30 International Business Machines Corporation Run-time parallelization of loops in computer programs by access patterns
US7904893B2 (en) * 2004-03-17 2011-03-08 Marvell International Ltd. Power and/or energy optimized compile/execution
JP4740561B2 (ja) * 2004-07-09 2011-08-03 富士通株式会社 トランスレータプログラム、プログラム変換方法およびトランスレータ装置
US7487497B2 (en) * 2004-08-26 2009-02-03 International Business Machines Corporation Method and system for auto parallelization of zero-trip loops through induction variable substitution
US7493604B2 (en) * 2004-10-21 2009-02-17 Microsoft Corporation Conditional compilation of intermediate language code based on current environment
JP4082706B2 (ja) * 2005-04-12 2008-04-30 学校法人早稲田大学 マルチプロセッサシステム及びマルチグレイン並列化コンパイラ
JP4476876B2 (ja) * 2005-06-10 2010-06-09 三菱電機株式会社 並列計算装置
JP4936517B2 (ja) * 2006-06-06 2012-05-23 学校法人早稲田大学 ヘテロジニアス・マルチプロセッサシステムの制御方法及びマルチグレイン並列化コンパイラ
JP4231516B2 (ja) * 2006-08-04 2009-03-04 株式会社日立製作所 実行コードの生成方法及びプログラム
US20080127146A1 (en) * 2006-09-06 2008-05-29 Shih-Wei Liao System and method for generating object code for map-reduce idioms in multiprocessor systems
US8024714B2 (en) * 2006-11-17 2011-09-20 Microsoft Corporation Parallelizing sequential frameworks using transactions
US7962906B2 (en) * 2007-03-15 2011-06-14 International Business Machines Corporation Compiler method for employing multiple autonomous synergistic processors to simultaneously operate on longer vectors of data
US8635606B2 (en) * 2009-10-13 2014-01-21 Empire Technology Development Llc Dynamic optimization using a resource cost registry
US8572359B2 (en) * 2009-12-30 2013-10-29 International Business Machines Corporation Runtime extraction of data parallelism
US8949808B2 (en) * 2010-09-23 2015-02-03 Apple Inc. Systems and methods for compiler-based full-function vectorization

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02132526A (ja) * 1988-11-14 1990-05-22 Hitachi Ltd 並列計算機の処理平準化方法および自動並列化コンパイル方法

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013500515A (ja) * 2009-07-21 2013-01-07 マイクロソフト コーポレーション コンポーネントの電力監視およびワークロードの最適化
EP2519876A1 (en) * 2009-12-28 2012-11-07 Hyperion Core, Inc. Optimisation of loops and data flow sections
US9672188B2 (en) 2009-12-28 2017-06-06 Hyperion Core, Inc. Optimization of loops and data flow sections in multi-core processor environment
US10331615B2 (en) 2009-12-28 2019-06-25 Hyperion Core, Inc. Optimization of loops and data flow sections in multi-core processor environment
WO2012008019A1 (ja) * 2010-07-13 2012-01-19 富士通株式会社 情報処理装置、情報処理装置の制御方法及びプログラム
JP5435133B2 (ja) * 2010-07-13 2014-03-05 富士通株式会社 情報処理装置、情報処理装置の制御方法及びプログラム
JP2013041437A (ja) * 2011-08-17 2013-02-28 Nec Corp 計算装置、計算装置の制御方法、及びプログラム
JP2015022574A (ja) * 2013-07-19 2015-02-02 富士通株式会社 並列処理最適化プログラム、並列処理最適化方法および情報処理装置
JP2017102790A (ja) * 2015-12-03 2017-06-08 富士通株式会社 情報処理装置、演算処理装置および情報処理装置の制御方法

Also Published As

Publication number Publication date
US8543993B2 (en) 2013-09-24
EP2202638A1 (en) 2010-06-30
US20100235611A1 (en) 2010-09-16
JP5067425B2 (ja) 2012-11-07
EP2202638A4 (en) 2011-12-14
JPWO2009037731A1 (ja) 2010-12-24

Similar Documents

Publication Publication Date Title
WO2009037731A1 (ja) 翻訳装置と翻訳方法および翻訳プログラムとプロセッサコアの制御方法およびプロセッサ
WO2008152790A1 (ja) マルチプロセッサ制御装置、マルチプロセッサ制御方法及びマルチプロセッサ制御回路
WO2007089499A3 (en) Power consumption management
TW201714103A (en) Application scheduling in heterogeneous multiprocessor computing platforms for maximal predicted performance gains
WO2010043401A3 (en) Sequential processor comprising an alu array
WO2010037177A8 (en) Scheduling an application for performance on a heterogeneous computing system
GB2429554A (en) Method and apparatus to vectorize multiple input instructions
WO2007092528A9 (en) Thread optimized multiprocessor architecture
TW200632742A (en) Method and apparatus for varying energy per instruction according to the amount of available parallelism
ATE554443T1 (de) Anweisungsgesteuerte datenverarbeitungseinrichtung und -verfahren
WO2011090673A3 (en) Shared memories for energy efficient multi-core processors
WO2013065004A3 (en) Electronic device power saving mode, associated apparatus and methods
WO2006004710A3 (en) Execution of hardware description language (hdl) programs
WO2009120981A3 (en) Vector instructions to enable efficient synchronization and parallel reduction operations
ATE514998T1 (de) Getaktete ports
WO2010008955A3 (en) Method and system for executing applications using native code modules
FR2937439B1 (fr) Procede d'execution deterministe et de synchronisation d'un systeme de traitement de l'information comportant plusieurs coeurs de traitement executant des taches systemes.
WO2013070425A3 (en) Conserving power through work load estimation for a portable computing device using scheduled resource set transitions
WO2007078913A3 (en) Cross-architecture execution optimization
EA201390868A1 (ru) Способ и система для вычислительного ускорения обработки сейсмических данных
TW200731739A (en) Cryptography system and elliptic curve operation method involved thereof
EA201070298A1 (ru) Усовершенствованная система ввода данных
GB0921776D0 (en) Payment device
WO2013114277A3 (en) A deformable apparatus, method and computer program
EP2518630A4 (en) SIGNAL DECODER SWITCHING, LATCH SETUP SWITCH, MEMORY CONTROL, PROCESSOR, COMPUTER, SIGNAL DECODING METHOD, AND LATENCE SETTING METHOD

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 07805864

Country of ref document: EP

Kind code of ref document: A1

WWE Wipo information: entry into national phase

Ref document number: 2009532967

Country of ref document: JP

NENP Non-entry into the national phase

Ref country code: DE

WWE Wipo information: entry into national phase

Ref document number: 2007805864

Country of ref document: EP