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WO2009001564A1 - 半導体素子の実装構造体及びその製造方法、半導体素子の実装方法、並びに加圧ツール - Google Patents

半導体素子の実装構造体及びその製造方法、半導体素子の実装方法、並びに加圧ツール Download PDF

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Publication number
WO2009001564A1
WO2009001564A1 PCT/JP2008/001669 JP2008001669W WO2009001564A1 WO 2009001564 A1 WO2009001564 A1 WO 2009001564A1 JP 2008001669 W JP2008001669 W JP 2008001669W WO 2009001564 A1 WO2009001564 A1 WO 2009001564A1
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WO
WIPO (PCT)
Prior art keywords
semiconductor element
element mounting
semiconductor chip
mounting structure
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2008/001669
Other languages
English (en)
French (fr)
Inventor
Teppei Iwase
Yoshihiro Tomura
Kazuhiro Nobori
Yuichiro Yamada
Kentaro Kumazawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Corp
Original Assignee
Panasonic Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Panasonic Corp filed Critical Panasonic Corp
Priority to CN2008800220112A priority Critical patent/CN101689516B/zh
Priority to JP2009520355A priority patent/JP5084829B2/ja
Priority to US12/666,860 priority patent/US8264079B2/en
Publication of WO2009001564A1 publication Critical patent/WO2009001564A1/ja
Anticipated expiration legal-status Critical
Priority to US13/567,112 priority patent/US8426965B2/en
Ceased legal-status Critical Current

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    • H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
    • H01L24/75—Apparatus for connecting with bump connectors or layer connectors
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B30—PRESSES
    • B30B—PRESSES IN GENERAL
    • B30B5/00—Presses characterised by the use of pressing means other than those mentioned in the preceding groups
    • B30B5/02—Presses characterised by the use of pressing means other than those mentioned in the preceding groups wherein the pressing means is in the form of a flexible element, e.g. diaphragm, urged by fluid pressure
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  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

　半導体チップのパッド上に形成されたバンプと、表面にシート状の封止接着用樹脂を貼り付けた基板を対向させ、ツールで押し付けることで、半導体チップと基板の間に封止接着樹脂が充填され、かつ半導体チップのパッドと基板の電極がバンプを介して接続されて形成される半導体チップの実装構造において、半導体チップのコーナー部分における側面全体が封止接着用樹脂によって覆われるようにする。これにより、実装時の加熱、冷却処理によって生じる各部材の熱膨張、収縮差および実装後の機械的な負荷に対する基板のたわみによる半導体チップのコーナー部分に発生する負荷を軽減し、チップ内部の破壊を回避できる。
PCT/JP2008/001669 2007-06-28 2008-06-26 半導体素子の実装構造体及びその製造方法、半導体素子の実装方法、並びに加圧ツール Ceased WO2009001564A1 (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
CN2008800220112A CN101689516B (zh) 2007-06-28 2008-06-26 半导体元件的安装构造体的制造方法及加压工具
JP2009520355A JP5084829B2 (ja) 2007-06-28 2008-06-26 半導体素子の実装構造体の製造方法、半導体素子の実装方法、及び加圧ツール
US12/666,860 US8264079B2 (en) 2007-06-28 2008-06-26 Semiconductor device mounted structure and its manufacturing method, semiconductor device mounting method, and pressing tool
US13/567,112 US8426965B2 (en) 2007-06-28 2012-08-06 Semiconductor device mounted structure and its manufacturing method, semiconductor device mounting method, and pressing tool

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2007169975 2007-06-28
JP2007-169975 2007-06-28

Related Child Applications (2)

Application Number Title Priority Date Filing Date
US12/666,860 A-371-Of-International US8264079B2 (en) 2007-06-28 2008-06-26 Semiconductor device mounted structure and its manufacturing method, semiconductor device mounting method, and pressing tool
US13/567,112 Division US8426965B2 (en) 2007-06-28 2012-08-06 Semiconductor device mounted structure and its manufacturing method, semiconductor device mounting method, and pressing tool

Publications (1)

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WO2009001564A1 true WO2009001564A1 (ja) 2008-12-31

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PCT/JP2008/001669 Ceased WO2009001564A1 (ja) 2007-06-28 2008-06-26 半導体素子の実装構造体及びその製造方法、半導体素子の実装方法、並びに加圧ツール

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US (2) US8264079B2 (ja)
JP (1) JP5084829B2 (ja)
CN (1) CN101689516B (ja)
WO (1) WO2009001564A1 (ja)

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011054867A (ja) * 2009-09-04 2011-03-17 Lintec Corp Ｉｃチップの接続構造、ｉｃインレット及びｉｃタグ
US20120222808A1 (en) * 2009-11-20 2012-09-06 Sony Chemical & Information Device Corporation Mounting device and method for manufacturing electronic module
JP2012168708A (ja) * 2011-02-14 2012-09-06 Lintec Corp Ｉｃタグ
JP2013514664A (ja) * 2009-12-29 2013-04-25 インテル コーポレイション リセス埋込ダイを備えるコアレスパッケージ
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