WO2009084570A1 - Compiler embedded function adding device - Google Patents

Abstract

This object aims to provide a device, program or method that adds an embedded function corresponding to an additional command to a compiler in the form that is possible to reflect information of a command word length or latency of the additional command on the compiler. An embedded function adding program (30) reads in an additional command specification description file (40) and a compiler source code (50) for a base processor from a memory device (20), generates a definition sentence of the embedded function corresponding to the additional command described in the additional command specification description file, and outputs to the memorydevice (20) a compiler source code for a base processor to which the definition sentence of the embedded function corresponding to the additional command is added as a compiler source code (60) for an expanded processor where the additional command is provided in a command set.

Description

Built-in function addition device

[Description of related applications]
The present invention is based on the priority claim of Japanese patent application: Japanese Patent Application No. 2007-340532 (filed on Dec. 28, 2007), the entire contents of which are incorporated herein by reference. Shall.
The present invention relates to a compiler technique for a processor, and more particularly to a technique for adding an embedded function corresponding to a new instruction (additional instruction) added to an instruction set of a basic processor (base processor) to a compiler.

Various tools have been developed for efficient processor design. One of these types of tools is a tool that generates the hardware configuration of the processor and software development tools (compiler, assembler, simulator, etc.) from the design specifications of the processor, and is provided as a program that runs on a computer. . The computer on which the tool operates is also called a “processor design support device”.

Non-Patent Document 1, Patent Documents 1 to 3 and the like disclose a processor design support apparatus that generates an assembler and compiler for a processor based on a processor instruction set defined by a designer.

The processor design support apparatus disclosed in Non-Patent Document 1, Patent Documents 1 to 3, and the like can add a new instruction to a basic processor (referred to as a “base processor”). In order to make the built-in function corresponding to the instruction added to the base processor available from the compiler, the processor design support apparatus generates a header file that defines the function described in the inline assembler as the built-in function. Regarding the generation of the header file, the descriptions in Patent Document 1 (paragraph number 0329), Patent Document 2 (paragraph number 0056), Patent Document 3 (paragraph number 0052), and the like are also referred to.

∙ Built-in functions are functions that correspond one-to-one with processor instructions.

By using built-in functions, program developers can let the compiler use instructions that the compiler does not normally use.

∙ The compiler handles built-in functions as one of the normal functions, so the compiler performs register allocation for arguments and return values of built-in functions.

The inline assembler is, for example, an assembler language described in C language source code. By using an inline assembler, assembler language can be inserted into the source code.

Tensilica, USP-6477683, “Automatedmprocessor generation system for designing a configurable processor and method for the same.” Richard M. Stallman and the GCC Developer Community, “GNU Compiler Collection Internals (GCC),” Internet <URL: ＜ http://gcc.gnu.org/onlinedocs/gccint.pdf> (page 239, “14 Machine Description”) , Page 241, “14.4 RTL Template”, page 327 “14.19.8 Specifying processor processor, pipeline description”) Free Software Foundation, Inc., Yoichi Yabuki, “GNU Compiler Collection (GCC) Usage and Porting” (“Machine Description” on page 178, “RTL Template” on page 180)) Internet <URL: http: //www.sra.co.jp/public/sra/product/wingnut/gcc/gcc-j.html> GNU Project-Free Software Foundation, Inc., "Installing GCC," Internet <URL: http://gcc.gnu.org/install/> ("Configuration" on page 7 and "Building" on page 21) Special table 2003-518280 gazette JP 2003-323463 A Japanese Patent Laid-Open No. 2002-24029

The disclosures of Non-Patent Documents 1 to 4 and Patent Documents 1 to 3 described above are incorporated herein by reference. The following is an analysis of the related art according to the present invention.

In the related technologies such as Patent Documents 1 to 3, the addition of the compiler built-in function uses the built-in function for the additional instruction by adding only the header file without changing the compiler for the base processor. enable.

That is, there is an advantage that no compiler change is required since only the header file is added to the compiler.

However, when a compiler built-in function is added by the related technology, there is a problem that information such as instruction word length of an additional instruction and latency is not reflected in the compiler at all.

The instruction word length is information indicating how many bytes the additional instruction is.

Latency is information indicating how many cycles the operation result of the additional instruction is obtained.

* When adding a compiler built-in function using the above related technology, the instruction word length of the additional instruction cannot be notified to the compiler. For this reason, the compiler must assume that the word lengths of the additional instructions are all the same and have known values.

This means that additional commands with different word lengths cannot be created.

Furthermore, in the addition of the compiler built-in function according to the related technology, the compiler cannot inform the compiler of the latency of the additional instruction, so the compiler cannot schedule the additional instruction efficiently. There is a possibility that the compiler can efficiently schedule additional instructions using the control flow and data flow information of the target source code, but this is not possible with the related technology.

As described above, when adding a compiler built-in function according to related technology, information such as the instruction word length and latency of the additional instruction is not reflected in the compiler at all.

Therefore, a main object of the present invention is to provide an apparatus, a method, and a program that allow specification information such as the instruction word length and latency of an additional instruction to be reflected in the compiler when a compiler built-in function is added.

In one aspect of the present invention, for an additional instruction added to the instruction set of the basic processor (base processor), an embedded function corresponding to the additional instruction is added to the compiler of the base processor. In the present invention, an intrinsic function is added to the compiler by adding source code for enabling the compiler to understand the instruction word length and latency information of the additional instruction to the source code of the base compiler.

According to the present invention, based on the specification description of an additional instruction newly added to the instruction set of the base processor with respect to the source code of the compiler for the base processor, the extended processor which is a base processor having the additional instruction By generating the source code of the compiler for use, an apparatus for executing an embedded function addition process for adding an embedded function corresponding to the additional instruction to the compiler is provided.

According to the present invention, the source code of the compiler for the base processor is input, and based on the specification description of the additional instruction newly added to the instruction set of the base processor, the source code of the compiler for the base processor A program for generating a source code of a compiler for an extended processor having an additional instruction in an instruction set and causing the computer to execute an embedded function adding process for adding an embedded function corresponding to the additional instruction to the compiler for the extended processor. Provided.

According to the present invention, the source code of the compiler for the base processor is input, and based on the specification description of the additional instruction newly added to the instruction set of the base processor, the source code of the compiler for the base processor A method for generating a compiler source code for an extended processor having an additional instruction in an instruction set and executing an embedded function adding process for adding an embedded function corresponding to the additional instruction to the compiler for the extended processor is provided. The

In the present invention, the built-in function adding process is:
Processing to read the specification description of the additional instruction;
Processing for generating a configuration definition statement of an additional instruction based on the specification description;
Processing for generating a relationship definition statement between an additional instruction and a corresponding built-in function based on the specification description;
Processing for generating a compiler source code for the extension processor by adding the configuration definition statement and the relationship definition statement to the source code of the compiler for the base processor.

In the present invention, the configuration definition statement includes an additional instruction template expressed in an intermediate language of a compiler, and a latency definition statement that defines the number of cycles required to execute the additional instruction, and the configuration definition statement is The generating process generates the template based on the name of the additional instruction, the input operand, and the output operand included in the specification description, and further, based on the number of cycles necessary for executing the additional instruction included in the specification description. The latency definition sentence may be generated.

In the present invention, the relationship definition statement includes a prototype declaration of an embedded function corresponding to an additional instruction and an embedded function expansion function for replacing the embedded function with the additional instruction, and the process of generating the relationship definition statement includes Generating a prototype declaration of the built-in function based on the name of an additional instruction included in the specification description, an input operand, and an output operand, and further generating the built-in function expansion function based on a predetermined format of a compiler It is also good.

In the present invention, when generating the template in the configuration definition statement, the first compiler built-in function adding device,
Determining the operand number in the intermediate language definition statement of the additional instruction by arranging the output operand and the input operand of the additional instruction of the specification description in order;
Generating a name for the template based on the name of the additional instruction in the specification description;
Generating a description of the output operand of the template based on the type of the output operand of the additional instruction of the specification description;
Generating a description of the input operand of the template based on the type of the input operand of the additional instruction of the specification description;
Generate an action description of the additional instruction in the template using an operator that indicates that the additional instruction performs an operation unknown to the compiler,
Generating a template syntax by replacing an operand included in the syntax of the additional instruction in the specification description with the operand number;
Generating an instruction word length definition statement in the template based on the instruction word length of the additional instruction in the specification description;
A configuration may be adopted in which a series of processes of generating a mnemonic definition sentence in the template based on the name of the additional instruction in the specification description is performed.

According to the present invention, when a compiler built-in function is added, information such as instruction word length and latency of the additional instruction can be reflected in the compiler.

It is a figure which shows the structure of one Example of this invention. It is a figure which shows the input / output relationship of the compiler intrinsic | native function addition program of one Example of this invention. It is a figure which shows the process sequence of one Example of this invention. It is a figure which shows the procedure of the RTL template production | generation process in FIG. It is a figure which shows the procedure of the determination of the operand number of the RTL template in a RTL template production | generation process. It is a figure which shows the process sequence of the latency definition sentence production | generation process of FIG. It is a figure which shows the correspondence of the attribute width of the <operand> tag in the specification description of an additional command, and the character string modemshort which represents the word length of the operand of an RTL template. It is a figure showing the format of the definition statement for defining the name of the function which tells a compiler the prototype declaration of a built-in function. It is a figure which shows the correspondence with the attribute width of the <operand> tag in the specification description of an additional instruction, the return value in the prototype declaration of a built-in function, and the argument type specifier modelnamelong_type_node. It is a figure which shows the content of the function which tells a compiler the prototype declaration of an intrinsic function. It is a figure which shows the format of the definition statement of the intrinsic | native function prototype declaration produced | generated by the intrinsic | native function prototype declaration production | generation process. It is a figure which shows the format of the definition sentence for defining the name of the expansion function of a built-in function. It is a figure which shows the content of the expansion function of a built-in function. It is a figure which shows the specific content of the additional instruction specification description file of one Example of this invention. FIG. 15 is a diagram showing an RTL template for an additional instruction mac32 generated based on the specification description of FIG. 14 in the RTL template generation process (step 200). FIG. 15 is a diagram showing an RTL template for an additional instruction avg2 generated based on the specification description of FIG. 14 in the RTL template generation process (step 200). FIG. 15 is a diagram showing a latency definition sentence generated based on the specification description of FIG. 14 in step 310 and step 320 of FIG. 6. FIG. 15 is a diagram showing a latency definition statement for an additional instruction mac32 generated based on the specification description of FIG. 14 in step 330 of FIG. FIG. 15 is a diagram showing a latency definition sentence of an additional instruction avg2 generated based on the specification description of FIG. 14 in step 330 of FIG. FIG. 15 is a diagram showing an embedded function prototype declaration for an additional instruction mac32 generated based on the specification description of FIG. 14 in the embedded function prototype declaration generation process (step 400). FIG. 15 is a diagram showing an embedded function prototype declaration for an additional instruction avg2 generated based on the specification description of FIG. 14 in the embedded function prototype declaration generation process (step 400). FIG. 15 is a diagram showing the contents of a function generated based on the specification description of FIG. 14 in the built-in function prototype declaration generation process (step 400).

Explanation of symbols

10 CPU
DESCRIPTION OF SYMBOLS 20 Storage device 30 Compiler built-in function additional program 40 Additional instruction specification description file 50 Base processor compiler source code 60 Extended processor compiler source code 61 Additional instruction configuration definition statement 62 Additional instruction template 63 Latency for defining additional instruction latency Definition 64 Definition statement of relationship between additional instruction and built-in function 65 Prototype declaration of built-in function 66 Built-in function expansion function 70 Compiler built-in function adding device

Embodiments of the present invention will be described in detail with reference to the drawings. The compiler built-in function adding device according to the present invention is a device that adds a built-in function corresponding to the additional instruction to the compiler for the base processor based on the specification description regarding the additional instruction to the base processor.

The built-in function is also called “intrinsic”. Built-in functions are functions that correspond one-to-one with processor instructions.

Generally, when an embedded function is used in the source code of a program, it is replaced by the compiler with the corresponding instruction.

When an embedded function corresponding to an additional instruction to the base processor is added to the compiler, the program developer can use the additional instruction from the compiler in the form of a function call.

In one embodiment of the present invention, it is assumed that a compiler for a base processor already exists and that the source code of the compiler can also be used.

Based on this premise, the source code of the compiler for the base processor is modified so that the compiler can handle the built-in functions corresponding to the additional instructions. In the modification of the source code, a modification is performed in which a fragment of the source code necessary for handling the built-in function for the additional instruction is added to the source code of the compiler. According to the present invention, information such as the instruction word length and latency of the additional instruction can be reflected in the compiler. As a result, the compiler can correctly calculate the word length of the program including the additional instruction and can appropriately schedule the additional instruction.

FIG. 1 is a diagram showing a configuration of a compiler built-in function adding device in an exemplary embodiment of the present invention. The compiler built-in function adding device 70 includes a CPU 10, a storage device 20, a compiler built-in function adding means (compiler built-in function adding program) 30, an additional instruction specification description file 40, a compiler source code 50 for a base processor, and an extended processor. Compiler source code 60. The compiler built-in function adding unit 30 is also referred to as a compiler built-in function adding program 30 because processing and functions are realized by a program executed by the CPU 10.

When the CPU 10 executes the compiler built-in function addition program 30, the additional instruction specification description file 40 and the base processor compiler source code 50 are read from the storage device 20 and correspond to the additional instructions described in the additional instruction specification description file 40. An extension function compiler source code 60 is generated by generating an embedded function definition statement corresponding to the additional instruction to the base processor compiler source code 50 and generating the extension processor compiler source code 60. Is stored in the storage device 20.

The compiler built-in function adding device 70 can be realized using a general computer (for example, a personal computer). The user (user) can also build an extended processor compiler using the extended processor compiler source code 60. Furthermore, the construction function can be added to the compiler built-in function adding device 70.

FIG. 2 is a diagram showing details of the input / output relationship of the compiler built-in function addition program 30 of FIG. The input files of the compiler built-in function adding program 30 are an additional instruction specification description file 40 and a base processor compiler source code 50.

The final output file of the compiler built-in function addition program 30 is the compiler source code 60 for the extended processor.

The extended processor compiler source code 60 includes a base processor compiler source code 50, a configuration definition statement 61 of an additional instruction, and a relationship definition statement 64 of the additional instruction and an embedded function.

By executing the compiler built-in function addition program 30, the CPU 10 generates a configuration definition statement 61 of an additional instruction and a relationship definition statement 64 between the additional instruction and the built-in function based on the additional instruction specification description file 40.

Further, the CPU 10 adds the configuration definition statement 61 of the additional instruction and the relationship definition statement 64 between the additional instruction and the built-in function to the compiler source code 50 for the base processor. Then, the CPU 10 outputs the configuration definition statement 61 of the additional instruction, the relationship definition statement 64 between the additional instruction and the built-in function, and the added source code as the extended processor compiler source code 60.

The additional instruction configuration definition statement 61 includes an additional instruction template 62 defined in an intermediate language of the compiler, and a latency definition sentence 63 that defines the latency of the additional instruction.

The template 62 is generally described in an intermediate language of a compiler called “RTL (register transfer language)”. Hereinafter, a specific example of the template 62 will be referred to as an “RTL template”.

The latency definition statement 63 defines the number of cycles (latency) necessary for executing the additional instruction.

The relation definition statement 64 between the additional instruction and the built-in function includes a prototype declaration 65 of the built-in function corresponding to the additional instruction and an expansion function 66 of the built-in function.

The prototype declaration 65 of the built-in function defines the return value and argument type of the built-in function.

The built-in function prototype declaration 65 allows the compiler for the extended processor to know the name of the built-in function, the return value, and the argument type.

The expansion function 66 of the built-in function is a function used by the compiler for the extended processor in order to detect an additional instruction corresponding to the built-in function.

FIG. 3 is a flowchart showing the processing procedure of the compiler built-in function addition program 30. Referring to FIG. 3, the compiler built-in function addition program 30 is
A step 100 for reading the specification description;
Step 200 for performing processing for generating an RTL template;
Step 300 for performing processing for generating a latency definition statement;
A step 400 of performing a process of generating a built-in function prototype declaration;
Step 500 for performing processing for generating an embedded function expansion function;
Step 600 for performing additional processing of compiler source code;
including.

In this embodiment, a computer program for causing the computer to execute the processing procedure of the flowchart shown in FIG. 3 is supplied to the compiler built-in function adding device 70 via a predetermined medium or the like, and the computer program is added to the compiler built-in function. The CPU 10 of the device 70 may be loaded into the main memory and executed. The computer program supplied to the compiler built-in function adding device 70 may be stored in a readable / writable memory or a storage medium such as a hard disk device. The present invention is constituted by such a computer program or a storage medium.

In the following, first, the specification description regarding the additional instruction will be described, and then each step of FIG. 3 will be described.

[Specification description for additional instructions to base processor]
As described above, the input to the compiler built-in function addition program 30 is the specification description file 40 regarding the additional instruction to the base processor. Although not particularly limited, in the present embodiment, the specification description of the additional instruction is based on XML (extensible markup language). By describing the specification of the additional instruction in XML, it is possible to analyze or convert the specification description of the additional instruction using an existing lexical analyzer or syntax analyzer that supports XML. This facilitates the analysis and conversion of the specification description of the additional instruction. Even if a language other than XML is used, it is possible to describe the specifications of additional instructions.

The following describes the specification description of the additional instruction based on XML.

XML tags for specification description of additional instructions are <nickname> and <insn>.

The <nickname> tag is a tag that defines a nickname of a target processor. The number of characters in the nickname is arbitrary, and the characters that can be used as the nickname are alphabets and numbers. The nickname defined by the <nickname> tag is used as a part of the name of a variable, function, or the like generated by the compiler built-in function addition program 30.

<Example of <nickname> tag description is shown below.

<Nickname> foo </ nickname>

The <insn> tag is a tag that defines an instruction of the target processor.
The value of the <insn> tag is another tag for defining instruction syntax, word length, and input operand.

FIG. 14 shows a description example of the <insn> tag. As illustrated in FIG. 14, the following six tags can be described as values of the <insn> tag.

<Mnemonic> is a tag that defines the mnemonic of the instruction.

<Syntax> is a tag that defines the syntax of an instruction.

<Length> is a tag that defines the word length of the instruction.

<Latency> is a tag that defines the latency of the instruction.

<Output> is a tag that defines an output operand into which an instruction writes a value.

<Input> is a tag that defines an input operand used by the instruction.
Hereinafter, tags that can be described as values of the <insn> tag will be described in detail.

The <mnemonic> tag is a tag that defines a mnemonic of an instruction. The number of mnemonic characters is arbitrary, and the characters that can be used as mnemonics are alphabets and numbers (mac32 in FIG. 14).

The mnemonic of one instruction must not be the same as the mnemonic of any other instruction. Mnemonics are not case sensitive. For example, mnemonic Foo and mnemonic foo are considered to be the same. An instruction mnemonic is used as part of the name of the built-in function corresponding to the instruction.

The <syntax> tag is a tag that defines the syntax of an instruction.

The value of the <syntax> tag is an arbitrary character string (“mac32% rd% ra% rb% rc” in FIG. 14) representing the syntax of the instruction. This character string can include a format character string. The format character string is a character string for designating the output position of the instruction operand. The format string begins with a% symbol. A character string (for example, rd) following the% symbol must match a value of an <operand> tag described later. The <operand> tag will be described later.

The format string is replaced with an appropriate string representing the operand. For example, a format character string corresponding to an <operand> tag representing a register is replaced with a register name, and a format character string corresponding to an <operand> tag representing an immediate value is replaced with a register name.

The <length> tag is a tag that defines the word length of an instruction in bits. However,
The instruction word length is a multiple of 8 (in FIG. 14, 32 bits, that is, 4 bytes).

The <latency> tag is a tag that defines the latency of an instruction. Latency is the number of cycles it takes for an instruction to execute after the instruction is executed. The instruction latency may vary depending on the program context. In such cases, this tag defines the longest possible latency.

The <output> tag is a tag that defines an output operand of an instruction. The value of the <output> tag is an <operand> tag that represents an operand.

The <input> tag is a tag that defines an input operand of an instruction. The value of the <input> tag is an <operand> tag that represents an operand.

The <operand> tag is a tag that defines an operand of an additional instruction. The <operand> tag is used as a value of an <output> tag or an <input> tag. The value of the <operand> tag is the name of the operand. This name is associated with the format string (eg% rd) of the <syntax> tag.

Only the name of the operand defined by the <operand> tag can be used as a format character string in the syntax of the instruction defined by the <syntax> tag.

* Operand names not defined in the <operand> tag cannot be used as format strings. The <operand> tag has two attributes, type and width.

Attribute type is an attribute that represents the operand type. The names that can be used as the value of this attribute are register and immediate.

Register indicates that the operand is a register.

Immediate indicates that the operand is an immediate value.

Attribute width is an attribute that represents the bit width of the operand.

[Loading specification description of additional instructions]
Processing for reading the specification description of the additional instruction in the compiler built-in function adding device 70 (FIG. 1) will be described. This process is step 100 in FIG. In this process, the CPU 10 in FIG. 1 reads the specification description of the additional instruction described in XML and replaces it with a data structure that can be understood by the computer program.

The specification description of the additional instruction is described by a <nickname> tag or an <insn> tag based on the XML language specification. Therefore, using a general lexical analyzer and syntax analyzer for XML, the CPU 10 in FIG. 1 replaces the specification description of the additional instruction with a data structure understandable by the computer program. The replaced data structure corresponds to the tags described in the additional instruction specification description file 40 on a one-to-one basis. Therefore, hereinafter, the operation of FIG. 1 will be described with reference to a tag instead of the data structure.

[RTL template generation processing]
An RTL template generation process for an additional instruction in the compiler built-in function adding device 70 will be described. This process is step 200 in FIG.

RTL (register transfer language) is an intermediate language in the compiler. The compiler converts source code described in a high-level language such as C / C ++ into an intermediate language called RTL, and outputs a processor instruction based on the RTL. There is a one-to-one correspondence between RTL and processor instructions. An RTL template is a representation of processor instructions in RTL. Generally, RTL templates are written so that the compiler can understand the operation of the processor instructions.

However, in this embodiment, the exact operation of the additional instruction is not described in the RTL template. In this embodiment, the RTL template is output so that the compiler can correctly understand only the input / output operands of the additional instruction. By doing so, the complicated problem of correctly expressing the operation of the additional instruction with the RTL template is avoided.

FIG. 15 shows an example of the RTL template for the additional instruction. FIG. 15 is an RTL template for a product-sum operation instruction.

The RTL template is described by an expression “define_insn”. The define_insn expression is similar to an expression in the Lisp language. For a detailed description of the define_insn formula, refer to the description on page 239 of Non-Patent Document 2, “14 Machine Description”, or “Machine Description” on page 178 of Non-Patent Document 2.

The RTL template for additional instructions in this example is
(1) RTL template name,
(2) Output operand,
(3) input operands,
(4) Action description of additional instructions,
(5) Additional instruction syntax,
(6) Word length of the additional instruction,
(7) Additional instruction mnemonics,
7 elements are included.

FIG. 4 is a flowchart showing the procedure of the RTL template generation process (200 in FIG. 3) in the present embodiment. In order to generate the above seven elements, the RTL template generation process
A step 210 of determining input / output operand numbers;
Generating a name of the RTL template 220;
Generating 230 an output operand;
Generating an input operand 240;
Generating an operation description of the additional instruction 250;
Generating 260 additional instruction syntax;
Generating a word length definition sentence of the additional command; 270;
Generating a mnemonic definition statement of the additional instruction, 280;
including.

First, the determination of the input / output operand number (step 210) will be described.

According to “14.4 RTL Template” on page 241 of Non-Patent Document 2 or “RTL Template” on page 180 of Non-Patent Document 3, in the RTL template, each operand such as an output operand or input operand starts from 0. It is to be given a number that begins.

In this embodiment, in the RTL template generation process (step 200 in FIG. 3), the CPU 10 in FIG. 1 assigns a number to each operand based on the specification description of the additional instruction. Step 210 is a process for determining the number.

In the present embodiment, in the RTL template generation process (step 200 in FIG. 3), the CPU 10 in FIG. 1 determines the output operand and input operand in the RTL template of the additional instruction based on the <operand> tag in the specification description of the additional instruction. To do.

The output operand is determined by the <operand> tag described inside the <output> tag, and the input operand is determined by the <operand> tag described inside the <input> tag.

The compiler built-in function addition program 30 determines the operand number op_index of the RTL template according to the following procedure.

FIG. 5 is a flowchart for explaining the procedure for determining the operand number op_index of the RTL template.

Suppose that the number of <operand> tags described inside the <output> tag is P (step 211).

Next, let the number of <operand> tags described inside the <input> tag be Q (step 212).

<A number op_index from 0 to P-1 is assigned to all <operand> tags described inside the <output> tag (step 213).

<Numbers op_index from P to P + Q-1 are assigned to all <operand> tags described inside the <input> tag (step 214).

Next, name generation (step 220) of the RTL template will be described.

Step 220 is a process for determining the name of the RTL template corresponding to the additional command. In the RTL template generation process, the compiler built-in function addition program 30 determines the name of the RTL template based on the <nickname> tag and the <mnemonic> tag in the specification description of the additional instruction.

The format of the name of the RTL template is builtin_nkname_mnem. Here, nkname is the nickname of the processor defined by the <nickname> tag. mnem is a mnemonic of an additional instruction defined by the <mnemonic> tag.

Next, the generation of the output operand (step 230) in FIG. 4 will be described. Step 230 in FIG. 4 is processing for generating an output operand of the RTL template corresponding to the additional instruction.

Since the output operand represents an operand that stores the operation result of the additional instruction, the output operand is generally a register.

In the specification description of the additional instruction, if the value of the attribute type of the <operand> tag described inside the <output> tag is a register, the compiler built-in function addition program 30 corresponds to the <operand> tag. The format of the output operand to
(match_operand: modenameshort op_index “register_operand” “= r”) (1)
And

(1) “modenameshort” is a character representing the word length of the output operand.

“Modenameshort” is determined based on the attribute width of the <operand> tag. FIG. 7 shows the relationship between the attribute width and the modemshort.

Op_index is a number representing the number of the output operand. This op_index is the number determined in step 210.

Next, the generation of the input operand (step 240) in FIG. 4 will be described. Step 240 in FIG. 4 is processing for generating an input operand of the RTL template corresponding to the additional instruction.

Step 240 handles two types of input operands: registers and immediate values.

In the specification description of the additional instruction, when the attribute type of the <operand> tag described inside the <input> tag is a register, the compiler built-in function addition program 30 inputs corresponding to the <operand> tag. Operand format
(match_operand: modenameshort op_index “register_operand” “r”) (2)
And

This format is similar to the output operand of register (1).

The part that becomes “= r” in the format of the output operand becomes “r” in the format of the input operand.

Next, immediate input operands are explained.

When the attribute type of the <operand> tag described inside the <input> tag is an immediate value, the compiler built-in function addition program 30 sets the format of the output operand corresponding to the <operand> tag to (match_operand: SI op_index “immediate_operand” “n”) (3)
And

Next, the generation (step 250) of the operation description of the additional instruction in FIG. 4 will be described. Step 250 in FIG. 4 is processing for generating a description representing the operation of the additional instruction in the RTL template.

In step 250, the compiler built-in function addition program 30 generates an operation description of the additional instruction on the assumption that the additional instruction performs an unknown operation.

The format of the operation description of the additional instruction generated by step 250 is as follows.

(Set output_operand (unspec: VOID [all_input_operands] unspec_insn_id)) (4)

This format represents that all_input_operands is used as an input operand, and an operation result of an unknown operation represented by the number unspec_insn_id is assigned to the output operand output_operand.

In (4), unspec is an operator representing an operation unknown to the compiler.

Output_operand represents an output operand.

All_input_operands represents all input operands.

Unspec_insn_id represents a number for distinguishing an unknown operation of an additional instruction. The value of unspec_insn_id differs for each additional instruction.

Next, generation of the syntax of the additional instruction in FIG. 4 (step 260) will be described. Step 260 in FIG. 4 is a process for generating the syntax of the additional instruction in the RTL template.

Based on the syntax defined by the <syntax> tag in the specification description of the additional instruction, the compiler built-in function addition program 30 generates the syntax of the additional instruction in the RTL template.

The syntax defined by the <syntax> tag includes a format character string. The format character string is a character string that has a one-to-one correspondence with the operand of the additional instruction defined by the <operand> tag.

The compiler built-in function addition program 30 replaces the format character string included in the syntax defined by the <syntax> tag with a number (op_index described above) representing the operand of the RTL template, and adds an additional instruction in the RTL template. Use syntax. Since the number op_index is a number determined by the RTL template generation process based on the <operand> tag, the number op_index has a one-to-one correspondence with the format character string.

Next, generation of a word length definition sentence (step 270) of the additional instruction in FIG. 4 will be described. Step 270 in FIG. 4 is processing for generating a description that defines the word length of the additional instruction in the RTL template.

Based on the word length defined by the <length> tag in the specification description of the additional instruction, the compiler built-in function addition program 30 outputs the word length of the additional instruction in the RTL template in the following format.

(set_attr “length” “len”) (5)
Here, len is a number representing the word length defined by the <length> tag. The word length of the additional instruction in the RTL template is used by the compiler to calculate the code size.

Next, generation of a mnemonic definition sentence (step 280) of the additional instruction in FIG. 4 will be described. Step 280 in FIG. 4 is processing for generating a description that defines the mnemonic of the additional instruction in the RTL template.

Based on the mnemonic defined by the <mnemonic> tag in the specification description of the additional instruction, the compiler built-in function addition program 30 outputs the mnemonic definition statement of the additional instruction in the RTL template in the following format.

(set_attr “mnemonic” “mnem”) (6)
Here, mnem is a character string representing a mnemonic defined by the <mnemonic> tag.

The compiler built-in function addition program 30 uses the mnemonic of the additional instruction in the RTL template as the identification code of the additional instruction in the latency definition sentence generation process to generate the latency definition sentence of the additional instruction.

[Latency definition statement generation processing]
A latency definition statement generation process (step 300 in FIG. 3) for an additional instruction in the compiler built-in function adding device of this embodiment will be described. The latency definition statement is a definition statement for informing the instruction scheduler of the compiler of the latency of the additional instruction. The latency definition sentence generation process uses the following three types of expressions.

define_automaton (7)
define_cpu_unit (8)
define_insn_reservation (9)

The define_automaton expression defines the name of the state transition machine used by the compiler instruction scheduler.

The define_cpu_unit expression defines an execution unit of a processor to be managed by the state transition machine.

The define_insn_reservation expression defines an instruction train and an execution unit used by the instruction.

That is, the execution unit of the processor is notified to the instruction scheduler of the compiler by the define_cpu_unit expression.

It tells the instruction scheduler of the compiler which instruction uses which execution unit by the define_insn_reservation expression.

The state transition machine with the name defined by the define_automaton expression manages the usage status of the execution unit and the latency of the instruction.

For a detailed description of these equations, refer to the description of “14.19.8 Specifying processor pipeline description” on page 327 of Non-Patent Document 2.

FIG. 6 is a flowchart showing a processing procedure of the latency definition sentence generation process (step 300) of FIG. Latency definition statement generation processing
generating 310 a define_automaton expression;
generating a define_cpu_unit expression 320;
generating 330 a define_insn_reservation expression;
including.

Step 330 is executed for all additional instructions.

In the latency definition statement generation process for the additional instruction, the compiler built-in function additional program 30
One define_automaton expression,
One define_cpu_unit expression,
Define_insn_reservation expression for the number of additional instructions,
Is generated.

The specification description of the additional instruction does not include information on the execution unit of the processor or information on which execution unit the additional instruction uses.

In the latency definition statement generation process for the additional instruction, the compiler built-in function addition program 30 generates the above three expressions on the assumption that all the additional instructions use the same execution unit.

Step 310 and step 320 will be described together. The format of the define_automaton expression generated by the latency definition sentence generation processing for the additional instruction is given by the following (10).

(Define_automaton “dfa_builtin_insns”) (10)

The first argument of this expression represents the name of the state transition machine.

The format of the define_cpu_unit expression generated by the latency definition sentence generation process for the additional instruction is given by the following (11).

(Define_cpu_unit “unit_builtin” “dfa_builtin_insns”) (11)

The first argument of this expression represents the name of the processor execution unit, and the second argument represents the name of the state transition machine.

The latency definition statement generation process for the additional instruction defines a fictitious execution unit “unit_builtin”.

These two formats are used in common for all additional instructions and do not depend on the specification description of any additional instructions.

Next, step 330 will be described. The format of the define_insn_reservation expression generated by the latency definition sentence generation process for the additional instruction is given by the following expression.

(Define_insn_reservation “mnem” ltcy (eq_attr “mnemonic” “mnem”) “unit_builtin, nothing * ltcy_minus_1”)) (12)

The first argument of this expression is the name given to this whole expression,
The second argument is the number of latency cycles,
The third argument is the condition of the additional command to which this expression applies,
The fourth argument is the execution unit used by the additional instruction,
Respectively.

Here, mnem is a mnemonic of the additional instruction defined in the <mnemonic> tag in the specification description of the additional instruction.

Ltcy is a value representing the latency of the additional instruction defined by the <latency> tag.

Ltcy_minus_1 is a value obtained by subtracting 1 from ltcy.

In this format, the condition of the additional instruction that applies to this expression is specified by using the attribute mnemonic defined in the define_insn expression of the additional instruction.

Further, the execution unit used by the additional instruction uses only the execution unit “unit_builtin” defined by the define_cpu_unit expression in the first cycle, and does not use any execution unit in the subsequent cycles.

When the latency of the additional instruction is 1, the compiler built-in function adding program 30 sets the fourth argument of the define_insn_reservation expression as “unit_builtin” to indicate that only the execution unit used in the first cycle is used. To do.

In the latency definition statement generation process for the additional instruction, the compiler built-in function addition program 30 generates a define_insn_reservation expression for all the additional instructions according to this format.

[Built-in function prototype declaration generation processing]
An embedded function prototype declaration generation process (step 400 in FIG. 3) for an additional instruction in the compiler embedded function adding device will be described. The built-in function prototype declaration generation process for the additional instruction is a process of generating a built-in function prototype declaration for the compiler.

The prototype declaration of the built-in function is information indicating what arguments the built-in function has and what the return value of the built-in function is.

* By incorporating the prototype declaration of an embedded function into the compiler, the compiler can recognize the embedded function as an embedded function.

In the built-in function prototype declaration generation process, the compiler built-in function addition program 30 generates a definition statement that defines the name of a function that tells the compiler the prototype declaration of the built-in function and the contents of the function.

The format of a function name definition statement that tells the compiler the prototype declaration of an embedded function is shown below (FIG. 8).
#undef TARGET_INIT_BUILTINS
#define TARGET_INIT_BUILTINS target_init_builtins (13)

This definition statement does not depend on the specification description of the additional instruction. This definition statement is used for any additional command.

The contents of the function target_init_builds () corresponding to this definition statement are as shown in FIG.

The function target_init_builds () is a function having no argument and no return value, and executes a prototype declaration of a built-in function corresponding to each additional instruction described therein.

Furthermore, in the built-in function prototype declaration generation process, the compiler built-in function addition program 30 generates a definition statement of the prototype declaration of the built-in function corresponding to all the additional instructions as the contents of the function target_init_builds ().

Describes how to generate definition statements for built-in function prototype declarations. In the built-in function prototype declaration generation process, the compiler built-in function addition program 30 determines a return value and an argument of the built-in function corresponding to the additional instruction based on the number of output operands of the additional instruction.

When the number of output operands of the additional instruction is one, the compiler built-in function additional program 30 causes the built-in function prototype declaration generation processing to use the output operand as the return value of the built-in function, and to set all input operands of the additional instruction as built-in functions As an argument.

When the number of output operands of the additional instruction is 0 or 2 or more, the compiler intrinsic function additional program 30 determines that the intrinsic function prototype declaration generation process does not have a return value for the intrinsic function, and outputs all the additional instructions. Operands and input operands are built-in function arguments.

Next, the order of arguments of built-in functions will be described. After determining what arguments the intrinsic function has based on the return value of the intrinsic function and the method of determining the argument, the compiler intrinsic function addition program 30 performs the above-mentioned in the intrinsic function prototype declaration generation process (step 400 in FIG. 3). Based on the operand number op_index in the define_insn expression, the arguments are arranged in order from the smallest operand number op_index corresponding to the argument.

In other words, in the built-in function prototype declaration generation process, the compiler built-in function addition program 30 sets the argument corresponding to the operand having the smallest number op_index as the first argument, and the argument corresponding to the operand having the next smaller number op_index as the first argument. It takes two arguments, and so on, determines the order of the arguments of the built-in function.

The format of the definition statement of the built-in function prototype declaration generated in the built-in function prototype declaration generation process (step 400 in FIG. 3) is shown in (14) below (see FIG. 11).

Here, mnem is a mnemonic of the additional instruction defined by the <mnemonic> tag in the specification description of the additional instruction. nkname is the nickname of the processor defined by the <nickname> tag. “modenamelong” is a character string representing the type of the argument of the built-in function.

{
tree ftype_mnem = build_function_type_list (
modenamelong_type_node, / * operand 0 * /
modenamelong_type_node, / * operand 1 * /
modenamelong_type_node, / * operand 2 * / ..
. NULL_TREE);
builtin_function (“__ builtin_nkname_mnem”, / * name of intrinsic * /
ftype_mnem, / * prototype * /
CODE_FOR_builtin_nkname_mnem, / * RTL template name * /
BUILT_IN_MD, NULL, NULL_TREE);
} ・ ・ ・ (14)

This form first creates a list ftype_mnem representing the return value and argument type of a built-in function using the function build_function_type_list (), and then uses the function built_function () to give the name of the built-in function and the list ftype_mnem to the compiler. It means to register.

The argument of the function build_function_type_list () is a type specifier “modenamelong_type_node” representing the return value type of the built-in function and the argument type.

The first argument of the function build_function_type_list () is a type specifier of the return value of the built-in function, and the second and subsequent arguments are type specifiers of the argument of the built-in function.

If the built-in function has no return value, the compiler built-in function adding program 30 sets void_type_node as the first argument of the function build_function_type_list ().

The type specifier modelnamelong_type_node representing the return value type and argument type of the built-in function will be described.

The return values and arguments of built-in functions correspond one-to-one with the <operand> tag in the specification description of additional instructions.

<Modelnamelong> in the type specifier modelnamelong_type_node is determined based on the attribute width of the <operand> tag.

FIG. 9 is a diagram showing the relationship between the attribute width and modernalong.

If the attribute width is 8, then modemalong is char,
If the attribute width is 16, then modemamelong is short_integer,
If the attribute width is 32, modemalong is an integer.

Function “function_function ()” is a function for registering an embedded function in the compiler.

This registration allows the compiler to know the name of the built-in function, the return value type and argument type of the built-in function, and the name of the RTL template corresponding to the built-in function.

The built-in function name format is __builtin_nkname_mnem (15)
It is.

The name of the built-in function includes the nickname nkname of the processor and the mnemonic mnem of the additional instruction. The return value type and argument type of the built-in function are expressed as a list of type specifiers, ftype_mnem.

This list ftype_mnem is generated by the function build_function_type_list ().

The format of the name of the RTL template corresponding to the built-in function is CODE_FOR_builtin_nkname_mnem. This is obtained by adding CODE_FOR_ to the head of the name of the RTL template in the define_insn expression.

[Built-in function expansion function generation processing]
An expansion function generation process (step 500 in FIG. 3) of the embedded function in the compiler embedded function adding device will be described. In this process, the compiler built-in function addition program 30 generates a definition statement that defines the name of the expansion function of the built-in function and the contents of the function.

The expansion function of the built-in function analyzes which additional instruction corresponds to the given built-in function, and generates an RTL expression representing the additional instruction corresponding to the given built-in function.

The expansion function of the built-in function generated in this process is called by the compiler.

The format of a definition statement for the name of a built-in function expansion function is shown below. By this definition statement, the name of the expansion function of the built-in function becomes target_expand_buildin ().
#undef TARGET_EXPAND_BUILTIN
#define TARGET_EXPAND_BUILTIN target_expand_builtin
... (16)

Furthermore, the expansion function generation process of the built-in function generates the contents of the expansion function of the built-in function. The expansion function of the built-in function includes three steps of step 510, step 520, and step 530. Step 510 is a step of checking the argument type of the built-in function. Step 520 is a step of acquiring the return type of the built-in function. Step 530 is a step of generating an RTL expression corresponding to the built-in function.

FIG. 13 is a diagram showing an example of the contents of the expansion function of the built-in function. All the built-in functions corresponding to the additional instruction are processed by the expansion function of the built-in function in FIG. The detailed processing contents of each step are shown below.

In the argument type check (step 510), based on the RTL template defined by the define_insn expression corresponding to the embedded function, the expansion function of the embedded function arranges the argument of the embedded function in an appropriate storage location.

If the operand of the RTL template corresponding to the argument is a register, the built-in function expansion function stores the argument in the virtual register.

If the operand of the RTL template corresponding to the argument is an immediate value, the expansion function of the built-in function treats the argument as an immediate value as it is.

In the return type acquisition (step 520), the expansion function of the built-in function acquires the return value type of the built-in function based on the RTL template defined by the define_insn expression corresponding to the built-in function. If a built-in function has a return value, the expansion function of the built-in function creates a virtual register corresponding to the return value. If the built-in function has no return value, the built-in function expansion function does nothing with the return value.

In the generation of the RTL expression corresponding to the built-in function (step 530), the expansion function of the built-in function generates the RTL expression corresponding to the built-in function based on the name, return value, and argument of the built-in function. A macro function called GEN_FCN (X) is used to generate the RTL expression. The macro function GEN_FCN (X) is a function provided by the compiler, and is a function that returns a function pointer of an RTL expression generation function corresponding to the built-in function X. Using the function returned by the macro function GEN_FCN (X), the expansion function of the built-in function generates an RTL expression corresponding to the built-in function.

[Compiler source code addition processing]
Compiler source code addition processing in the compiler built-in function addition apparatus 70 (step 600 in FIG. 3 will be described. This addition processing is based on the source code fragment of the compiler generated in steps 200, 300, 400, and 500 in FIG. This is processing to be added to the compiler source code for the processor (compiler source code 50 for the base processor).

In step 600, the compiler built-in function addition program 30 determines which source code of the compiler to add the fragment based on the <nickname> tag in the specification description of the additional instruction. If the nickname defined by the <nickname> tag is nkname, the source code of the compiler to which the fragment is added is nkname.com in the directory gcc / config / nkname. c and nkname. There are two files named md. These two files become the base processor compiler source code 50. Source code fragments are the following four.

RTL template (generated by step 200 of FIG. 3),
Latency definition statement (generated by step 300),
Built-in function prototype declaration (generated by step 400),
Built-in function expansion function (generated by step 500)

In step 600, the compiler built-in function addition program 30 stores the RTL template and the latency definition statement in the file nkname. Append to the end of md.

Further, in step 600, the compiler built-in function addition program 30 stores the built-in function prototype declaration and the built-in function expansion function in the file nkname. Append to the end of c. By this addition, a fragment of the source code generated by the processing from step 200 to step 500 is added to the compiler source code 50 for the base processor. The source code to which the fragments are added becomes the compiler source code 60 for the extended processor in FIG.

The procedure for building a compiler using the compiler source code 60 for the extended processor is exactly the same as a general compiler build procedure. Regarding the build procedure of the compiler, refer to the description of “Configuration” on page 7 and “Building” on page 21 of Non-Patent Document 4.

The operation of this embodiment will be described below based on a specific example. An example of the additional instruction specification description file 40 is shown in FIG. A description will be given of how the compiler built-in function adding apparatus operates using the XML file shown in FIG.

First, in step 100 of FIG. 3, the compiler built-in function addition program 30 reads the contents of the XML file of FIG.

In step 100, the compiler built-in function addition program 30 replaces the content shown in FIG. 14 with a data structure understandable by the computer program.

Next, in step 200 of FIG. 3, the compiler built-in function addition program 30 generates an RTL template corresponding to the additional instruction described in FIG.

FIG. 14 describes the specifications of two additional instructions using the <insn> tag. In FIG. 14, the first <insn> tag is an additional instruction called mac32. The second <insn> tag is an additional instruction avg2.

In step 200, the compiler built-in function addition program 30 generates an RTL template for one additional instruction at a time. Step 200 is performed twice to generate an RTL template for two additional instructions.

Step 200 includes eight steps from Step 210 to Step 280. In each step, the compiler built-in function addition program 30 generates RTL template components and combines them as one RTL template.

FIG. 15 shows the RTL template of the additional instruction mac32 generated in step 200. FIG. 16 shows an RTL template for the additional instruction avg2. The following describes what the CPU 10 of FIG. 1 generates for the additional instruction mac32 and the additional instruction avg2 in each step.

The operation of step 210 in FIG. 4 will be described. Step 210 is a process of determining the input / output operand number of the additional instruction.

First, in step 210, the compiler built-in function addition program 30 determines the number of the input / output operand based on the <operand> tag of the additional instruction mac32.

According to the <output> tag of the additional instruction mac32, the number of output operands of the additional instruction mac32 is one.

According to the <input> tag of the additional instruction mac32, the number of input operands of the additional instruction mac32 is three.

In step 210, the compiler built-in function adding program 30 assigns a number first from the output operand, and assigns a number first to the operand described earlier in FIG.

Therefore, the compiler built-in function addition program 30 relates to the input / output operand of the additional instruction mac32.
The number of the output operand rd is 0,
The number of the input operand ra is 1,
The number of the input operand rb is 2,
The number of the input operand rc is 3,
And

Furthermore, in the same manner, for the additional instruction avg2, the number of the input / output operand is determined based on the <operand> tag.

For the input / output operands of the additional instruction avg2,
The number of the output operand rd is 0,
The number of the input operand rm is 1,
The number of the input operand rn is 2,
It is decided.

The operation of step 220 in FIG. 4 will be described. Step 220 is a process of determining the name of the RTL template based on the <nickname> tag and the <mnemonic> tag of the additional instruction.

The format of the name of the RTL template is builtin_nkname_mnem. Therefore, the compiler built-in function addition program 30 is
The name of the RTL template of the additional instruction mac32 is defined as buildin_mycpu_mac32.
The name of the RTL template of the additional instruction avg2 is builtin_mycpu_avg2
And

Next, the operation of step 230 in FIG. 4 will be described. Step 230 is a process of generating an output operand description of the RTL template based on the <operand> tag of the additional instruction.

The format of the output operand is given by (17) below.
(match_operand: modenameshort op_index "register_operand""=r") (17)

The output operand of the additional instruction mac32 is only rd. According to step 210, since the number of the output operand rd is determined to be 0, the op_index of rd is 0.

And, since the output operand rd is a 32-bit wide register, the mode's modemshort is SI.

Therefore, the compiler built-in function addition program 30 sets the output operand of the RTL template of the additional instruction mac32 as (18) below.

(Match_operand: SI 0 "register_operand" "= r") (18)

Similarly, the output operand of the RTL template is determined for the additional instruction avg2.

The output operand of the RTL template of the additional instruction avg2 is
(match_operand: SI 0 “register_operand” “= r”) (19)
It is decided.

Next, the operation of step 240 in FIG. 4 will be described. Step 240 is a process for generating an output operand description of the RTL template based on the <operand> tag of the additional instruction. The input operand format of the register is
(match_operand: modenameshort op_index "register_operand""r") (20)
It is.

The input instruction mac32 has three input operands, ra, rb, and rc, all of which are 32-bit registers.

In step 210 of FIG. 4, the numbers of the input operands ra, rb, and rc are already determined as 1, 2, and 3, respectively. Therefore, the compiler built-in function addition program 30 sets the three input operands ra, rb, and rc of the RTL template of the additional instruction mac32 as follows.
Input operand ra: (match_operand: SI 1 “register_operand” “r”) (21)
Input operand rb: (match_operand: SI 2 “register_operand” “r”) (22)
Input operand rc: (match_operand: SI 3 “register_operand” “r”) (23)

Similarly, the input operand of the RTL template is determined for the additional instruction avg2. The two input operands rm and rn of the RTL template of the additional instruction avg2 are set as follows.
Input operand rm: (match_operand: SI 1 “register_operand” “r”) (24)
Input operand rn: (match_operand: SI 2 “register_operand” “r”) (25)

Next, the operation of step 250 in FIG. 4 will be described. Step 250 is a process of generating an operation description of the RTL template of the additional instruction. The format of the behavior description of the RTL template for additional instructions is
(set output_operand (unspec: VOID [all_input_operands] unspec_insn_id)) (26)
It is.

Output_operand represents an output operand. This was generated in step 230.

All_input_operand represents all input operands. This was generated in step 240.

Unspec_insn_id is an appropriate number, and each additional instruction has a different value of unspec_insn_id.

Here, the compiler built-in function addition program 30 is
10000 unspec_insn_id of the additional instruction mac32
Unspec_insn_id of the additional instruction avg2 is set to 10001,
And

Next, the operation of step 260 in FIG. 4 will be described. Step 260 is a process of generating the syntax of the RTL template based on the <syntax> tag of the additional instruction.

According to the <syntax> tag of the additional instruction mac32, the syntax of the additional instruction mac32 is “mac32% rd% ra% rb% rc”. This syntax includes a format character string (% rd,% ra,% rb,% rc). These format character strings correspond to input / output operands.

In step 260, the compiler built-in function addition program 30 replaces these format character strings with the operand numbers of the RTL template. % Rd is replaced with% 0,% ra is replaced with% 1,% rb is replaced with% 2, and% rc is replaced with% 3.

Accordingly, the compiler built-in function addition program 30 uses the syntax of the RTL template of the additional instruction mac32 as follows:
“Mac32% 0% 1% 2% 3” (27)
And

Similarly, the syntax of the RTL template is determined for the additional instruction avg2. The syntax of the RTL template for the additional instruction avg2 is
“Avg2% 0% 1% 2” (28)
It is decided.

Next, the operation of step 270 in FIG. 4 will be described. Step 270 is processing for generating a word length definition sentence of the RTL template based on the <length> tag of the additional instruction. The format of the word length definition sentence in the RTL template is
(set_attr “length” “len”) (29)
It is.

According to the <length> tag of the additional instruction mac32, the word length of the additional instruction mac32 is 32 bits (4 bytes). Therefore, the compiler built-in function addition program 30 changes the word length definition sentence of the RTL template of the additional instruction mac32 to (set_attr “length” “4”) (30)
And

Similarly, a word length definition sentence of the RTL template is generated for the additional instruction avg2. The word length definition sentence of the RTL template of the additional instruction avg2 is
(set_attr "length""4") (31)
It is decided.

Next, the operation of step 280 in FIG. 4 will be described. Step 280 is processing for generating a mnemonic definition sentence of the RTL template based on the <mnemonic> tag of the additional instruction.

The format of the mnemonic definition statement in the RTL template is
(set_attr “mnemonic” “mnem”) (32)
It is.

According to the <mnemonic> tag of the additional instruction mac32, the mnemonic of the additional instruction mac32 is mac32. Therefore, the compiler built-in function adding program 30 converts the mnemonic definition statement of the RTL template of the additional instruction mac32 into
(set_attr “mnemonic” “mac32”) (33)
And

Similarly, a mnemonic definition sentence of the RTL template is generated for the additional instruction avg2. The mnemonic definition statement of the RTL template for the additional instruction avg2 is
(set_attr "mnemonic""avg2") (34)
It is decided.

Finally, in step 200, the compiler built-in function adding program 30 combines the ones generated in steps 210 to 230 into an RTL template (FIG. 15) of the additional instruction mac32 and an RTL template (FIG. 16) of the additional instruction avg2. ) And generate.

Next, in step 300 of FIG. 3, the compiler built-in function addition program 30 generates a latency definition statement corresponding to the additional instruction described in FIG. As described above, step 300 is composed of three steps: step 310, step 320, and step 330. Steps 310 and 320 are processes for generating a definition sentence common to all additional instructions. FIG. 17 shows an example of a common definition sentence generated in step 310 and step 320.

Subsequently, the compiler built-in function addition program 30 executes Step 330 for the two additional instructions described in FIG.

In step 330, the compiler built-in function addition program 30 generates a latency definition statement for each additional instruction.

The format of the latency definition statement is
(define_insn_reservation "mnem" ltcy (eq_attr "mnemonic""mnem")"unti_builtin, nothing * ltcy_minus_1")) (35)
It is.

According to the <mnemonic> tag and the <latency> tag of the additional instruction mac32, the mnemonic of the additional instruction mac32 is mac32, and the word length of the additional instruction mac32 is 32 bits (4 bytes). Therefore, the compiler built-in function addition program 30 sets the latency definition statement of the additional instruction mac32 as shown in FIG.

Similarly, a latency definition statement is also generated for the additional instruction avg2. The latency definition statement of the additional instruction avg2 is as shown in FIG.

Next, in step 400 of FIG. 3, the compiler built-in function addition program 30 generates a built-in function prototype declaration corresponding to the additional instruction described in FIG. In step 400, first, the compiler built-in function addition program 30 generates a definition statement that defines the name of the function that tells the compiler the prototype declaration of the built-in function. This definition sentence is as shown in FIG.

In step 400, the compiler built-in function addition program 30 generates a prototype declaration of the built-in function corresponding to the additional instruction mac32 and the additional instruction avg2 described in FIG. The format of the prototype declaration of the built-in function is as shown in FIG.

There are four operands in the RTL template of the additional instruction mac32, and the number op_index of these operands is determined in step 210 of FIG. The number of the output operand rd is 0, the number of the input operand ra is 1, the number of the input operand rb is 2, and the number of the input operand rc is 3.

According to the <operand> tag in FIG. 14, the bit widths of these operands are all 32 bits.

According to FIG. 9, the operand of the 32-bit width operand is an integer. Accordingly, the compiler built-in function addition program 30 sets all arguments of the function build_function_type_list () for the additional instruction mac32 to be integer_type_node.

According to the <nickname> tag in FIG. 14, the nickname of the processor is mycpu. According to the <mnemonic> tag of the additional instruction mac32, the mnemonic of the additional instruction mac32 is mac32. Finally, the compiler built-in function addition program 30 makes the prototype declaration of the built-in function corresponding to the add instruction mac32 as shown in FIG.

Similarly, a prototype declaration of an embedded function is generated for the additional instruction avg2. The prototype declaration of the built-in function of the additional instruction avg2 is as shown in FIG. Finally, as shown in FIG. 22, the compiler built-in function addition program 30 arranges the prototype declaration of the built-in function corresponding to the add instruction mac32 and the add instruction avg2 in the function target_init_builds ().

Next, in step 500 of FIG.
A definition statement that defines the name of a built-in function expansion function,
The contents of the expansion function of the built-in function,
Is generated. These do not depend on the specification description of the additional instruction.

The definition statement that defines the name of the expansion function of the built-in function is as shown in FIG. The contents of the expansion function of the built-in function are as shown in FIG.

Next, in step 600 of FIG. 3, the compiler built-in function addition program 30 adds a source code fragment to the compiler source code for the base processor (base processor compiler source code 50).

The source code fragments are the following four items generated from step 200 to step 500.

RTL template (generated in step 200 of FIG. 3: FIGS. 15 and 16);
Latency definition statement (generated in step 300 of FIG. 3: FIGS. 17, 18 and 19);
Built-in function prototype declaration (generated in step 400 of FIG. 3: FIGS. 8 and 22);
Built-in function expansion function (generated in step 500 of FIG. 3: FIGS. 12 and 13)

According to the <nickname> tag in FIG. 14, the nickname of the processor is mycpu. Therefore, in step 600, the source code of the compiler to which the CPU 10 of FIG. 1 adds the above source code fragment is mycpu. c and mycpu. There are two files named md. These two files become the base processor compiler source code 50.

3 In step 600 of FIG. 3, the compiler built-in function addition program 30 stores the RTL template (FIGS. 15 and 16) and the latency definition statement (FIGS. 17, 18, and 19) in the file mycpu. Append to the end of md.

Further, in step 600 of FIG. 3, the compiler built-in function addition program 30 stores the built-in function prototype declaration (FIGS. 8 and 22) and the built-in function expansion function (FIGS. 12 and 13) in the file mycpu. Append to the end of c.

As a result of this addition, a fragment of the source code generated in the processing from step 200 to step 500 in FIG. 3 is added to the compiler source code 50 for the base processor. The source code to which the fragments are added becomes the compiler source code 60 for the extended processor in FIG.

The procedure for building a compiler using the compiler source code 60 for the extended processor is exactly the same as a general compiler build procedure. Reference is made to the description of Non-Patent Document 4 (page 7, “Configuration” and “Building” on page 21) for the build procedure of the compiler.

According to the present invention, in addition to simply adding an intrinsic function corresponding to the additional instruction to the compiler based on the specification description of the additional instruction, the compiler correctly calculates the word length of the program including the additional instruction. Or additional instructions can be scheduled appropriately. By using the compiler, program developers can develop programs using built-in functions. The processor designer can take advantage of the present invention in designing a processor instruction set for a specific application.

The disclosures of Patent Documents 1-3 and Non-Patent Documents 1-4 above are incorporated herein by reference. Within the scope of the entire disclosure (including claims) of the present invention, the embodiments and examples can be changed and adjusted based on the basic technical concept. Various combinations and selections of various disclosed elements are possible within the scope of the claims of the present invention. That is, the present invention of course includes various variations and modifications that could be made by those skilled in the art according to the entire disclosure including the claims and the technical idea.

Claims (23)

Based on the specification description of the additional instruction newly added to the instruction set of the base processor, the source code of the compiler for the extended processor having the additional instruction in the instruction set is compared with the source code of the compiler for the base processor. Generate
A compiler built-in function adding device, comprising: a built-in function adding unit that adds a built-in function corresponding to the additional instruction to the compiler for the extension processor. The built-in function adding means reads the specification description of the additional instruction and the source code of the compiler for the base processor from the storage device, and defines the definition statement of the built-in function corresponding to the additional instruction described in the specification description of the additional instruction. And the definition statement of the built-in function corresponding to the additional instruction added to the source code of the compiler for the base processor is used as the source code of the compiler for the extended processor. Item 3. The compiler built-in function adding device according to Item 1. The built-in function adding means is
Read the specification description of the additional instruction,
Generate a configuration definition statement of the additional instruction based on the specification description,
Generating a relationship definition statement between the additional instruction and a built-in function corresponding to the additional instruction based on the specification description;
The configuration definition statement and the relationship definition statement are added to a source code of the compiler for the base processor, and a source code of the compiler for the extension processor is generated. The compiler built-in function addition device described. The configuration statement is
A template for additional instructions expressed in the intermediate language of the compiler;
A latency definition statement that defines the number of cycles required to execute the additional instruction;
Including
The built-in function adding means generates the configuration definition statement of the additional instruction.
Generating the template based on a name of the additional instruction included in the specification description, an input operand, and an output operand;
4. The compiler built-in function adding device according to claim 3, wherein the latency definition statement is generated based on a number of cycles necessary for executing the additional instruction included in the specification description. The relationship definition statement is
A prototype declaration of a built-in function corresponding to the additional instruction;
A built-in function expansion function for replacing the built-in function with an additional instruction;
Including
The built-in function adding means generates the relationship definition statement.
Generating a prototype declaration of the built-in function based on the name of the additional instruction, the input operand, and the output operand included in the specification description;
5. The compiler built-in function adding device according to claim 4, wherein the built-in function expansion function is generated based on a predetermined format of the compiler. When the built-in function adding means generates the template,
By arranging the output operand and the input operand of the additional instruction included in the specification description in order, the number of the operand in the intermediate language definition sentence of the additional instruction is determined;
Generating a name for the template based on the name of the additional instruction included in the specification description;
Generating a description of the output operand of the template based on the type of the output operand of the additional instruction included in the specification description;
Generating a description of the input operand of the template based on the type of the input operand of the additional instruction included in the specification description;
Generating an action description of the additional instruction in the template using an operator indicating that the additional instruction performs an operation unknown to the compiler;
Generating the syntax of the template by replacing an operand included in the syntax of the additional instruction included in the specification description with the operand number;
Generating an instruction word length definition sentence in the template based on an instruction word length of the additional instruction included in the specification description;
Generating a mnemonic definition sentence in the template based on the name of the additional instruction included in the specification description;
The compiler built-in function adding device according to claim 4 or 5, characterized in that: A compiler built-in function adding device according to any one of claims 1 to 6,
A compiler construction apparatus comprising means for constructing the compiler based on generated source code. Enter the compiler source code for the base processor
Based on the specification description of the additional instruction newly added to the instruction set of the base processor, the compiler source code for the extended processor having the additional instruction in the instruction set is generated from the source code of the compiler for the base processor And
A program for causing a computer to execute an embedded function addition process for adding an embedded function corresponding to the additional instruction to the compiler for the extension processor. The built-in function adding process reads the specification description of the additional instruction and the source code of the compiler for the base processor from the storage device, and defines the definition statement of the built-in function corresponding to the additional instruction described in the specification description of the additional instruction. Is generated, and the definition statement of the built-in function corresponding to the additional instruction is added to the source code of the compiler for the base processor, and is output to the storage device as the source code of the compiler for the extended processor. The program according to claim 8. The built-in function addition process
A process of reading the specification description of the additional instruction;
Processing for generating a configuration definition statement of the additional instruction based on the specification description;
Processing for generating a relationship definition statement between the additional instruction and a built-in function corresponding to the additional instruction based on the specification description;
9. The process of adding the configuration definition statement and the relationship definition statement to a source code of the compiler for the base processor to generate a source code of the compiler for the extension processor. Or the program of 9. The configuration statement is
A template for additional instructions expressed in the intermediate language of the compiler;
A latency definition statement that defines the number of cycles required to execute the additional instruction;
Including
The built-in function adding process is:
In the process of generating the configuration definition statement,
Generating the template based on a name of the additional instruction included in the specification description, an input operand, and an output operand;
The program according to claim 10, wherein the latency definition sentence is generated based on the number of cycles necessary for executing the additional instruction included in the specification description. The relationship definition statement is
A prototype declaration of a built-in function corresponding to the additional instruction;
A built-in function expansion function for replacing the built-in function with an additional instruction,
The built-in function adding process is:
In the process of generating the relationship definition statement,
Generating a prototype declaration of the built-in function based on the name of the additional instruction, the input operand, and the output operand included in the specification description;
12. The program according to claim 11, wherein the built-in function expansion function is generated based on a predetermined format of a compiler. In the built-in function adding process, when generating the template,
Determining the number of the operand in the intermediate language definition statement of the additional instruction by arranging the output operand and the input operand of the additional instruction in the specification description in order;
Generating a name for the template based on the name of the additional instruction included in the specification description;
Generating a description of the output operand of the template based on the type of the output operand of the additional instruction included in the specification description;
Generating a description of the input operand of the template based on the type of the input operand of the additional instruction included in the specification description;
Generate an action description of the additional instruction in the template using an operator that indicates that the additional instruction performs an operation unknown to the compiler;
Generating a template syntax by replacing an operand included in the syntax of the additional instruction included in the specification description with the operand number;
Generating an instruction word length definition sentence in the template based on an instruction word length of the additional instruction included in the specification description;
Generating a mnemonic definition sentence in the template based on the name of the additional instruction included in the specification description;
The program according to claim 11 or 12, characterized in that: Enter the compiler source code for the base processor
Based on the specification description of the additional instruction newly added to the instruction set of the base processor, the compiler source code for the extended processor having the additional instruction in the instruction set is generated from the source code of the compiler for the base processor And
A method for adding a compiler built-in function, comprising a step of adding a built-in function corresponding to the additional instruction to a compiler for the extension processor. The built-in function adding step includes
Read the specification description of the additional instruction and the source code of the compiler for the base processor from the storage device,
A definition statement of an embedded function corresponding to the additional instruction described in the specification description of the additional instruction;
The definition statement of the built-in function corresponding to the additional instruction added to the source code of the compiler for the base processor is output to the storage device as the source code of the compiler for the extension processor. 14. A method for adding a compiler built-in function according to 14. The built-in function adding step includes
Read the specification description of the additional instruction,
Generate a configuration definition statement of the additional instruction based on the specification description,
Generating a relationship definition statement between the additional instruction and a built-in function corresponding to the additional instruction based on the specification description;
16. The source code of the compiler for the extension processor is generated by adding the configuration definition statement and the relationship definition statement to the source code of the compiler for the base processor. To add a built-in compiler function. The configuration statement is
A template for additional instructions expressed in the intermediate language of the compiler;
A latency definition statement that defines the number of cycles required to execute the additional instruction;
Including
In generating the configuration statement of the additional instruction,
Generating the template based on a name of the additional instruction included in the specification description, an input operand, and an output operand;
17. The method for adding a compiler built-in function according to claim 16, wherein the latency definition statement is generated based on the number of cycles required for executing the additional instruction included in the specification description. The relationship definition statement is
A prototype declaration of a built-in function corresponding to the additional instruction;
A built-in function expansion function for replacing the built-in function with an additional instruction,
In generating the relationship definition statement,
Generating a prototype declaration of the built-in function based on the name of the additional instruction, the input operand, and the output operand included in the specification description;
18. The method for adding a compiler built-in function according to claim 17, wherein the built-in function expansion function is generated based on a predetermined format of the compiler. In the built-in function adding step, the template is generated.
Determining the number of the operand in the intermediate language definition statement of the additional instruction by arranging the output operand and the input operand of the additional instruction in the specification description in order;
Generating a name for the template based on the name of the additional instruction included in the specification description;
Generating a description of the output operand of the template based on the type of the output operand of the additional instruction included in the specification description;
Generating a description of the input operand of the template based on the type of the input operand of the additional instruction included in the specification description;
Generate an action description of the additional instruction in the template using an operator that indicates that the additional instruction performs an operation unknown to the compiler;
Generating a template syntax by replacing an operand included in the syntax of the additional instruction included in the specification description with the operand number;
Generating an instruction word length definition sentence in the template based on an instruction word length of the additional instruction included in the specification description;
19. The method for adding a compiler built-in function according to claim 17, wherein a mnemonic definition sentence in the template is generated based on a name of the additional instruction included in the specification description. The compiler built-in function adding device according to any one of claims 1 to 3, wherein the specification description of the additional instruction includes an instruction word length and latency of the additional instruction. The program according to any one of claims 8 to 10, wherein the specification description of the additional instruction includes an instruction word length and latency of the additional instruction. The method for adding a compiler built-in function according to any one of claims 14 to 16, wherein the specification description of the additional instruction includes an instruction word length and latency of the additional instruction. A new compiler is automatically generated by adding built-in functions corresponding to new instructions added to the instruction set of the base processor (called "additional instructions") from the compiler of the basic processor (called "base processor") The additional instruction mnemonic, the additional instruction syntax, the input instruction and output operands of the additional instruction, the instruction word length information of the additional instruction, and the additional instruction A storage device storing an additional instruction specification description file including latency information, and a source code of the compiler for the base processor;
The additional instruction specification description file and the source code of the base processor compiler are input from the storage device, and the additional instruction configuration definition information, the additional instruction, and the embedded instruction are input from the additional instruction specification description file. Generating the relationship definition information with the function, and adding the configuration definition information of the additional instruction and the relationship definition information of the additional instruction and the built-in function to the source code of the compiler for the base processor, Built-in function adding means for generating source code of the new compiler for a processor having an additional instruction in an instruction set and outputting the generated source code to a storage device;
The configuration definition information is
A template for the additional instruction expressed in an intermediate language of the compiler;
A latency definition that defines the number of cycles required to execute the additional instruction;
Including
The built-in function adding means includes
In generating the configuration definition information of the additional instruction,
Generating the template including the mnemonic of the additional instruction, the input and output operands, the operation of the additional instruction, the word length and syntax of the additional instruction from the specification description of the additional instruction;
Based on the latency information of the additional instruction included in the specification description, the latency definition is generated,
The relationship definition information is
A prototype declaration of an embedded function including information on arguments of the embedded function corresponding to the additional instruction, information on a return value of the embedded function, and causing the compiler to recognize the embedded function as an embedded function;
A built-in function expansion function for replacing the built-in function with an additional instruction;
Including
The built-in function adding means includes
In generating the relationship definition information,
Generating a prototype declaration of the built-in function based on the additional instruction mnemonic, the input operand, and the output operand included in the specification description;
In the expansion function generation of the built-in function, the argument type of the built-in function is checked, the return type of the built-in function is obtained, and an RTL (Register Transfer Level) expression that is an intermediate language expression corresponding to the built-in function. A compiler built-in function adding device characterized by generating.

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