WO2009081326A1

WO2009081326A1 - Device for receiving an rf signal and method for correcting for inaccuracies of a clock circuit specific reference frequency in such a device

Info

Publication number: WO2009081326A1
Application number: PCT/IB2008/055311
Authority: WO
Inventors: Johannes H. A. Brekelmans; Erwin Janssen; Konstantinos Doris; Pascal Philippe
Original assignee: NXP BV
Current assignee: NXP BV
Priority date: 2007-12-20
Filing date: 2008-12-15
Publication date: 2009-07-02
Anticipated expiration: 2010-06-20

Abstract

A device for receiving an RF input signal (2) and for processing the received RF input signal (2) is provided. The device comprises: an input (3) receiving the RF input signal (2); a clock circuit (34) generating a reference clock signal having a clock circuit specific reference frequency (fclock); and a frequency feedback control loop (17, 18, 20, 21, 22, 23; 35, 37, 38). The frequency feedback control loop is adapted to extract frequency information from the RF input signal (2), to put the clock circuit specific reference frequency (fclock) into relation with the extracted frequency information and to correct for inaccuracies of the clock circuit specific reference frequency based on this relation.

Description

Device for receiving an RF signal and method for correcting for inaccuracies of a clock circuit specific reference frequency in such a device

FIELD OF THE INVENTION

The invention relates to a device for receiving an RF signal and to a method for correcting for inaccuracies of a clock circuit specific reference frequency in such a device.

BACKGROUND OF THE INVENTION

In the context of the present application, RF signals (radio frequency signals) will be understood to mean analog signals comprising a plurality of frequencies, e.g. frequencies in the frequency band between 45 and 1040 MHz, such as for example TV signals or AM or FM radio signals. The term acoustic wave piezoelectric resonator encompasses bulk acoustic wave piezoelectric resonators such as BAW (bulk acoustic wave) or FBAR (film bulk acoustic wave) resonators as well as surface acoustic wave resonators (SAW). A large number of different devices for receiving RF signals can be found on the market. Examples for such devices are TV tuners for cable modems, DVD recorders, Set Top Boxes, USB-dongles, PC add-on-cards, TVs and other RF apparatuses. In such devices designed to receive an RF signal, the RF input signal is applied to an input of the device. The RF input signal comprises a plurality of frequencies and channels and a required channel selection and frequency conversion is performed in the device in order to provide a user with specific signals corresponding to particular channels.

Recently, concepts for further improving such devices for receiving RF signals have been developed. According to such recent concepts, the RF signal spectrum applied at an input of a device for receiving an RF signal, for example at the input of a DVD recorder, is sampled in its entirety and the channel selection and frequency conversion is done in the digital domain, i.e. in a digital signal processing unit (DSP). A main advantage of such a concept is that a plurality of channels contained in the RF input signal can be received concurrently, e.g. for simultaneously watching a TV channel while recording another one. The reception and subsequent signal processing in such devices requires a fixed- frequency reference clock signal. To tune an RF channel contained in the signal spectrum of the applied RF input signal with sufficient frequency accuracy and sufficient signal-to-noise ratio (SNR) places stringent requirements on the frequency accuracy and on the phase jitter of the clock signal. In particular, in order to ensure the frequency accuracy, changes due to temperature variation, variations in supply voltage and aging have to be taken into account. In order to fulfill these requirements, a reference clock signal used for receiving and processing the signals is commonly generated by means of a Phase Lock Loop (PLL) from a quartz-crystal based reference oscillator. Further, also in conventional devices which are not highly digitized, a reference clock signal is generated in this way in order to provide the required frequency accuracy.

However, a quartz crystal is an expensive and rather large size component which is difficult to integrate on an integrated circuit. The cost for this way of generating the reference clock signal is relatively high which is promoted by the fact that the resonance frequency of the crystal has to be mechanically adjusted to a specified value during the manufacturing process of the device in order to meet the required absolute frequency tolerance.

Recently, resonator devices more suitable for small size integration have appeared in form of miniature bulk acoustic wave (BAW or FBAR) piezoelectric resonators. These piezoelectric resonators are more suitable, for example for meeting the needs of modern wireless communication equipment, than conventional quartz crystals in view of size and production process. Due to the small size of these piezoelectric resonators, the resonance frequency is much higher than that of a quartz crystal, i.e. in the GHz range as compared to the range of tens of MHz. Taking into account the frequency difference, they feature Q factors (quality factors) which are a little lower than those of quartz crystals but much higher those of e.g. on-chip LC tanks. A further advantage of the piezoelectric resonators over e.g. quartz, ceramic or SAW (surface acoustic wave) devices is that they can be fabricated above silicon integrated circuits, since the required materials and processing techniques are compatible with those of an IC manufacturing back-end process.

A further advantage of the piezoelectric resonators of the kind described above is that the new concepts of devices for receiving RF signals, e.g. direct-sampling multichannel RF tuners, need a fixed- frequency reference clock signal in the GHz range. Since the piezoelectric resonators of the kind described above feature frequencies in this range, an oscillator based on such a resonator could be directly applied in the device for receiving an RF signal without a Phase Lock Loop (PLL). Thus, the need for a Phase Lock Loop would be eliminated. As a consequence, the circuit complexity could be reduced by using such a resonator. Further, due to the high quality factor of the piezoelectric resonator and the removal of the Phase Lock Loop jitter contribution, an excellent phase jitter performance can be achieved. Therefore, the application of such resonators for generating a reference clock signal would be preferable under many aspects.

However, the problem arises that the piezoelectric resonators of the kind described above cannot be manufactured with a small tolerance on the resonance frequency. This is typical for the manufacturing processes of integrated circuits. Furthermore, the piezoelectric resonators comprising high Q factors normally comprise a very small tuning range over which the resonance frequency is tunable. For example, the largest frequency tuning range of a FBAR oscillator known to the applicant is only 0.13%. Since the differences in resonance frequency resulting from the manufacturing process are about 1%, the tuning range is much smaller than the spread on the resonance frequency. Therefore, the frequency cannot easily be adjusted to within the tolerances achievable with a quartz crystal resonator.

As a consequence, there is a main disadvantage with respect to such piezoelectric resonators that a sufficient frequency accuracy needed to directly tune a certain RF channel is not provided.

OBJECT AND SUMMARY OF THE INVENTION

It is an object of the present invention to provide a device for receiving an RF signal and a method for correcting for inaccuracies of a clock circuit specific reference frequency in such a device which allow operating with a resonator providing a clock signal of reduced frequency accuracy.

This object is solved by a device for receiving an RF input signal and for processing the received RF input signal according to claim 1. The device comprises: an input receiving the RF input signal; a clock circuit generating a reference clock signal having a clock circuit specific reference frequency; and a frequency feedback control loop. The frequency feedback control loop is adapted to extract frequency information from the RF input signal, to put the clock circuit specific reference frequency into relation with the extracted frequency information and to correct for inaccuracies of the clock circuit specific reference frequency based on this relation. The correction for inaccuracies can be achieved by providing a (corrected) reference frequency. This reference frequency can be provided as a direct (physical) signal or in form of a calculation result in the case of a digital implementation. In the latter case the correction for inaccuracies is realized by carrying out the calculations by digital signal processing in such a way that any deviation from the nominal value of the clock frequency is taken into account as if the clock frequency would have been precise. Since the frequency feedback control loop is provided, the frequency inaccuracy of the reference clock signal can be taken into account on the basis of the frequency information contained in the RF input signal. Thus, a resonator comprising less frequency accuracy, such as a bulk acoustic wave piezoelectric resonator, can be used for generating the reference clock signal. Thus, the device does not require a quartz crystal with associated Phase Lock Loop.

Preferably, the frequency information is based on statistics derived from a plurality of RF input signals. According to an aspect, the frequency feedback control loop is adapted to periodically store results for the correction in memory for purpose of retrieval of results whenever the device needs to be rebooted. In this way long term variations in the clock circuit specific reference frequency are tracked and rebooting becomes quicker as a good estimate for the reference frequency error available from a previous iteration can be retrieved from memory.

If the clock circuit comprises an acoustic wave piezoelectric resonator or an LC or RC resonator, the resonator can be fabricated above silicon integrated circuits and size and complexity of the device can be reduced.

According to an aspect, the device further comprises an analog-digital converter converting the RF input signal to a digital signal and a digital signal processing unit digitally processing the digital signal. Preferably, the device is a direct-sampling multichannel RF tuner. In this case, a plurality of channels contained in the RF input signal can be received and processed concurrently. The analog-digital converter converts the continuous RF signal into a time-discrete series of amplitude quantized samples. The analog-digital converter and the digital signal processing unit are clocked based on the clock circuit specific reference clock signal. The process of digitizing the RF input signal with the reference clock signal converts the absolute frequencies of the RF input spectrum into corresponding time discrete frequencies that are relative to the reference clock frequency. According to further aspects, the frequency information is formed by at least one pre-determined carrier tone present in the RF input signal or, in case the RF input signal comprises a plurality of channels having fixed frequency spacing, the frequency information is formed by the fixed frequency spacing. In these cases, the frequency information can be easily identified and extracted from the digitized RF input signal. Thus, the frequency of the reference clock signal can be conveniently corrected in the device.

According to another aspect, the RF input signal is a received digitally modulated signal comprising a pre-determined symbol rate at which symbols contained in the RF input signal are recovered and the frequency information is formed by the symbol rate. In particular with respect to TV signals, this allows a reliable and accurate extraction of the frequency information contained in the RF signal spectrum as the symbol rate is generated on the transmitter side with tight tolerances.

The object is further solved by a method according to claim 10. The method is for correcting for inaccuracies of a clock circuit specific reference frequency in a device for receiving an RF input signal and processing the received RF input signal. The method comprises the steps: applying an RF input signal at an input of the device; generating a reference clock signal by a clock circuit, the reference clock signal having a clock circuit specific reference frequency; extracting frequency information from the RF input signal; putting the clock circuit specific reference frequency into relation with the extracted frequency information; and correcting for inaccuracies of the clock circuit specific reference frequency based on this relation. Correcting for inaccuracies can be achieved by providing a (corrected) reference frequency. The reference frequency can be provided as a direct (physical) signal or in form of a calculation result in the case of a digital implementation. In the latter case the correction for inaccuracies is then realized by carrying out calculations in the digital signal processing in such a way that any deviation from the nominal value of the clock frequency is taken into account as if the clock frequency would have been precise.

According to this method, a resonator having less frequency accuracy can be used for generating the reference clock signal, since an inaccuracy in the frequency of the reference clock signal is taken into account on the basis of the extracted frequency information.

Long term frequency variations of the reference clock signal over time can be tracked and taken into account if results for the correction are stored in memory periodically and retrieved from memory every time the device is powered on again. Further features and advantages will become apparent from the following detailed description of embodiments with reference to the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention will be described in greater detail hereinafter, by way of non- limiting examples, with reference to the embodiments shown in the drawings.

Fig. 1 schematically shows a device for receiving an RF signal.

Fig. 2 schematically illustrates the consequences of a frequency error of a reference clock signal in the time discrete domain.

Fig. 3 schematically shows a conceptual schematic of an RF receiver comprising a resonator of reduced frequency accuracy and a frequency feedback control loop.

Fig. 4 schematically illustrates the operation of an IF filter. Fig. 5 schematically shows a conventional receiver structure.

Fig. 6 schematically shows the structure of a device for receiving an RF signal according to a second embodiment.

DESCRIPTION OF EMBODIMENTS

FIRST EMBODIMENT

A first embodiment will now be described with reference to Figs. 1 to 3. In the embodiment of Fig. 1, the device for receiving an RF signal 1 is an RF receiver which could be used in a DVD recorder, for example.

The device for receiving an RF signal 1 illustrated in Fig. 1 is implemented as a direct-sampling multi-channel RF tuner. As can be seen in Fig. 1, an RF input signal 2 is applied to an input 3. For example, the RF input signal 2 is an analog antenna signal received through a cable network, from a satellite antenna or TV antenna. The RF input signal 2 is buffered with an input amplifier 4 which is formed by a low-noise amplifier (LNA) in the shown device. The signal output from the input amplifier 4 is provided to a loop-through output 5 to which a further device for receiving RF signals can be connected, e.g. in the case that the device for receiving an RF signal 1 is formed by a tuner of a DVD recorder, a TV apparatus can be connected to the loop-through output 5. Instead of one a plurality of loop- through outputs can be provided. Further, after passing the input amplifier 4, the RF input signal 2 is passed to a Variable Gain Amplifier circuit (VGA) 6, an anti-aliasing circuit 7, and an Analog-Digital Converter (ADC) 8 converting the RF input signal 2 into a digital signal 9.

The implementation of input amplifiers, variable gain amplifier circuits, anti- aliasing circuits, and analog-digital converters is known to the skilled person and will not be described in detail. The digital signal 9 is provided to a digital signal processing unit (DSP) 10 digitally processing the signal. The analog-digital converter 8 and the digital signal processing unit 10 are clocked by a reference clock signal 13 having a clock circuit specific reference frequency fclock. The reference clock signal 13 determines the sampling moments of the pre-processed RF input signal 2 by the analog-digital converter 8. Thus, sampling is performed in the analog-digital converter 8 with a sampling frequency corresponding to the specific reference frequency fclock or a fraction or multiple thereof.

Since the device 1 according to the first embodiment is a highly-digitized direct-sampling multi-channel RF tuner, the RF signal spectrum applied at the input 3 is sampled in its entirety. The digital signal processing unit (DSP) 10 performs channel selection, frequency conversion, and decimation and outputs signals 12 corresponding to particular channels to a plurality of channel decoders (not shown), as is schematically indicated. Thus, the various required filtering and frequency conversion operations are done in the digital domain using high precision numerical computations. The reference clock signal 13 to the digital signal processing unit 10 forms the time basis for all these computations. Since the RF input signal 2 has been digitized to become the digital signal 9, it is present in the sampled, time discrete domain. Thus, no absolute frequencies are used in the digital signal processing unit 10 for tuning to a channel contained in the frequency spectrum of the RF input signal 2. In the time discrete domain, all frequencies are mapped between 0 and Pi (π) as a result of the analog-digital conversion in the analog-digital converter 8, wherein Pi is equal to half the sampling frequency. Since the sampling frequency is directly linked to the clock circuit specific reference frequency fclock, the specific reference frequency fclock determines at which time discrete frequency a channel contained in the RF input signal 2 is present.

If, for example, a channel is present at a frequency of 400 MHz in the RF input signal 2 and the sampling frequency (specific reference frequency fclock or fraction or multiple thereof) is 2.4 GHz (= 2400 MHz), then the time discrete frequency of this channel is 400 400

-xπ = ^■ xπ = 1.0472 rad/s.

(2400/2) 1200

If however the sampling frequency is 2.5 GHz (2500 MHz) for example, then the time discrete frequency of this channel is

-xπ = xπ = 1.0053 rad/s.

(2500/2) 1250

Thus, the frequency to tune to in digital signal processing in the digital signal processing unit 10 is dependent on the sampling frequency with which the RF input signal 2 is sampled. Thus, the sampling frequency has to be known to unambiguously relate the frequency of a channel in the RF input signal 2 to a specific time discrete frequency. However, once the sampling frequency is known, it can be fully accounted for in the digital channel selection process and as such variations in the sampling frequency are tolerable. In a device using a quartz crystal and a Phase-Lock-Loop for generating the reference clock signal, a sufficiently high accuracy of the sampling frequency can be achieved. However, as described above, a bulk acoustic wave piezoelectric resonator such as a BAW or FBAR would be advantageous compared to a quartz crystal in many respects. However, if such a piezoelectric resonator is used, the problem has to be dealt with that a large tolerance in the resonance frequency results from the manufacturing process.

In the following it will be described how the problems caused by the lack of absolute frequency accuracy of such a piezoelectric resonator can be overcome. According to the disclosed solution, the problems are overcome by providing a frequency feedback control loop which extracts frequency information from the RF input signal, puts the clock circuit specific reference frequency fclock of the reference clock signal 13 in relation with the extracted frequency information, and provides the reference frequency for processing the received RF input signal based on this relation.

The principle of this will now be described in the following. According to the first embodiment, a bulk acoustic wave piezoelectric resonator 14 is used as a resonator, for example a BAW or a FBAR. The piezoelectric resonator 14 is coupled to an oscillator 15 for generating a reference clock signal 13. The resonator 14 and the oscillator 15 form a clock circuit 34. Due to the effects described above, the initial reference clock signal 13 associated with this resonator has a frequency which differs from an intended frequency, i.e. it has an inaccurate frequency. In this embodiment, the reference clock signal 13 is shared between all circuits in the device for receiving an RF signal, and in particular used by the analog-digital converter 8 and the digital signal processing unit 10. The other circuits sharing the reference clock signal 13 include for example a frequency converter circuits for channel decoding/demodulating, circuits for source decoding, etc. As a consequence, the frequency measurement performed in the digital signal processing unit 10 based on the clock circuit specific reference frequency fclock (inaccurate frequency) of the reference clock signal 13 will not be correct, since an inaccurate time reference is used. This will be schematically explained with reference to Fig. 2.

Fig. 2 schematically shows frequencies in the time discrete domain in the digital signal processing unit 10. If the clock circuit specific reference frequency fclock was exactly the intended accurate reference frequency, the time discrete frequency corresponding to a specific frequency of the RF input signal 2 would be at F_corr as shown in Fig. 2. However, since the inaccurate reference clock frequency 13 is used, the measured time discrete frequency is at F_meas in Fig. 2. Thus, the measured time discrete frequency F_meas differs from the correct time discrete frequency F_corr by an error Δ. If the specific frequency applied at the input 3 was accurately known, the correct time discrete frequency F_corr would be known. Thus, the difference Δ could be determined from the correct time discrete frequency F_corr and the measured time discrete frequency F_meas. This difference Δ could then be used to correct the clock circuit specific reference frequency fclock of the reference clock signal 13 to the intended accurate frequency. As a consequence, if the RF input signal 2 applied at the input 3 contains frequency information which can be reliably identified in the digital signal processing unit 10, the frequency of the reference clock signal 13 can be corrected based on this frequency information.

As has been described above, the RF input signal 2 applied at the input 3 during normal use of the device for receiving an RF signal 1 is a TV signal or an AM or FM radio signal, for example. Such RF input signals usually comprise characteristic frequencies or other information which can be used as frequency information to provide a (corrected) reference frequency fREF based on the clock circuit specific reference frequency fclock and the frequency information. The correction of the reference frequency fREF is performed by means of a frequency feedback control loop.

First, the frequency feedback control loop according to the first embodiment will be described with reference to Fig. 3. In the example, the frequency information contained in the RF input signal 2 is a specific characteristic channel and the frequency feedback control loop is using a digital mixer and a digital mixer oscillator signal generator.

In this digital implementation, a mixing signal fLO is determined by incremental phase step per reference clock signal, as will be described. In this case, by changing the incremental phase step, the frequency can be set directly and corrected by just writing a different number in a register, for example. As can be seen in Fig. 3, a resonator 14, e.g. an acoustic wave piezoelectric resonator, is coupled to an oscillator 15 such that a clock circuit is formed. The clock circuit generates a reference clock signal 13 having a clock circuit specific reference frequency fclock. The reference clock signal 13 is then provided to a frequency translator 17 in which the clock circuit specific reference frequency fclock is multiplied by a factor r to generate a frequency f2 (f2 = r x fclock). Initially, the factor r is set equal to 1 (r₀ = 1) such that, at the start, f2 = fclock. The signal output by the frequency translator 17 having the frequency f2 is then provided to a second frequency translator 18 dividing the frequency by an integer N to output a signal having a reference frequency fREF. This reference frequency is used as a time base for measuring the frequency of the downconverted RF signal or the frequency of any other characteristics signal contained in the downconverted RF input signal 2. As a BAW or FBAR is generating a high frequency reference signal and in baseband (after down conversion) the frequencies are much lower, as an example a baseband reference signal is derived from the high frequency clock signal by frequency division. Alternatively but less preferred, a reference frequency generation circuit could be added or shared from another autonomous circuit block, for example from a crystal oscillator.

Further, according to the embodiment the signal output by the frequency translator 17 is provided to a third frequency translator unit 20 multiplying the frequency with (N+l)/N and outputting a mixing signal fLO which is provided to a mixer 21. The second frequency translator is not needed when the RF signal is downconverted directly to zero (Fif=0). It is present to generate a frequency offset equal to the receiver IF frequency. In an analogue implementation, the combination of the first and second and the first and third frequency translators could for example be implemented in form of two fraction-N PLL frequency synthesizers.

The mixer 21 receives an RF input signal 2 containing a frequency fRF and mixes this input signal and the mixing signal fLO. The mixed signal is provided to an IF filter 22 generating a down-converted IF signal fIF. The IF filter filters the wanted signal thereby removing all other signals like for example an image frequency. Fig. 4 schematically illustrates the filtering of the IF filter 22 over frequency. As indicated by the thick line in Fig. 4, the IF filter 22 is adapted to filter all frequencies except those in a range around the IF filter frequency fjf; this range being indicated by a bracket in Fig. 4. One channel having a characteristic frequency distribution contained in the mixed signal is shown as the hatched box in Fig. 4. As can be seen from Fig. 4, the frequencies corresponding to the channel in the mixed signal will be all present in the down-converted IF signal fIF if they lie within the filter range of the IF filter 22. If not, they will be filtered out by the IF filter 22. This is the case for those frequencies on the right of the hatched box in Fig. 4. As a consequence, the channel will be present undistorted in the down-converted IF signal only if its frequencies in the mixed signal lie within the filtering range of the IF filter 22.

Further, the down-converted IF signal fIF and the signal having the reference frequency fREF are provided to a frequency comparator 23 comparing the frequencies of these two signals. The frequency comparator 23 outputs a value corresponding to the frequency difference between the frequency of the down-converted IF signal fIF and the reference frequency fREF as the frequency error (error). This error value (erroro in the 0^th iteration) is then fed back to the first frequency translator 17 for correcting the frequency of the base reference clock signal 16. The feedback is implemented by providing a modified factor r (T₁ since this is the first iteration) to the frequency translator according to the equation Ti = To - (erroro/fclock). Then, in the 1^st iteration, f2 is determined by fclock x Ti, and so on. Thus, in the first iteration a modified error value (errori) is output by the frequency comparator 23 and fed back to the frequency translator 17. In the (i+l)-th iteration, the factor r₁₊₁ is calculated based on the values of the preceding iteration according to the equation r₁₊₁ = T₁ - (error^fclock) and f2 is determined according to the equation f2 = r₁₊₁ x fclock. As a consequence, the reference frequency fREF is refined from one iteration to the next. The accuracy of a frequency measurement of a received signal (or a signal component thereof) will be depending on the signal to noise ratio of that signal. A number of refining iterations will be required in case the signal is weak, the signal to noise ratio therefore not very good and accuracy of the frequency measurement consequently not very high. The constraint is fundamental and it does not matter whether the receiver uses an analogue and digital implementation.

Functioning of the frequency feedback control loop will now be explained with respect to the following first table. In the non- limiting example of the table, it is assumed that the intended resonance frequency of the bulk acoustic wave piezoelectric resonator is 1 GHz (1000 MHz) and that the actual resonance frequency of this resonator was 950 MHz, thus deviating by 5.00% from the intended frequency. Further, as an example a test signal comprising a characteristic frequency at 1 GHz is applied as the input signal fRF. The integer N is assumed to be 100, i.e. the IF frequency and the reference frequency fREF output by the divider was intended to be 10 MHz (1000 MHz/100). The values in first table are based on the assumption of a noise-free signal.

It should be noted that the values contained in the table are rounded, while the computations are performed keeping more digits. As can be seen from the table, the factor r is 1 at the beginning, i.e. in the 0^th iteration (r₀ = 1). Thus, the first frequency translator outputs a signal f2 having a frequency of 950 MHz (950 MHz * r = 950 MHz * 1 = 950 MHz). As a consequence, the resulting reference frequency is 9.5 MHz (950 MHz/N = 950 MHz/ 100). The mixing signal fLO results to 959.5 MHz (950 MHz * (N+l)/N = 950 MHz * 101/100). The down-converted IF signal fIF consequently has a frequency of- 40.5 MHz (fLO - fRF = 959.5 MHz - 1000

MHz) and the error value output by the frequency comparator 23 is erroro = - 50 MHz (fIF - fREF = - 40.5 MHz - 9.5 MHz). This error is then fed back to the first frequency translator 17 as explained above. In the case of the noiseless signal, the error becomes zero in the first iteration. However, in a real system, the signal will never be absolutely noiseless. In the real system, the accuracy of a frequency measurement of a received signal (or a signal component thereof) will be depending on the signal to noise ratio of that signal. A number of refining iterations will be required in case the signal is weak, the signal to noise ratio therefore being not very good and accuracy of the frequency measurement consequently not very high. The constraint is fundamental and it does not matter whether the receiver uses a digital implementation or an analogue implementation. The following table shows an example in which the signal is not noise-free.

As can be seen from this table, even if the signal comprises noise, as long as the signal to noise ratio is not to low, the value of the error diminishes quickly in the iterations. Thus, the frequency of the reference clock signal is reliably corrected based on the frequency information contained in the RF input signal 2 which in this first example is formed by the specific frequency of the RF input signal 2. In this specific example the RF input signal 2 has been chosen as a test signal having a specific frequency applied to the input 3. In practice, the RF input signal 2 is for example an antenna signal comprising a plurality of channels. If the signal is being received with sufficient signal-to-noise ratio (SNR), a characteristic frequency in the down-converted channel or group of channels can be measured. Due to the presence of the channel IF filter, the frequency feedback is only available once the IF signal is sufficiently enclosed in the IF filter pass band. Otherwise, for making an accurate frequency measurement the signal-to-noise ratio may be insufficient or the signal could be disturbed by adjacent channels. This means that a sufficiently accurate guess of fLO is initially needed. To obtain a good guess may require a one-time calibration with a known input frequency. The RF input signal 2 can in that case be a test signal from a signal generator for the calibration procedure. Normally, i.e. in the intended use of the device, the RF input signal 2 will be received via an antenna or through a cable network.

As an alternative, in the case that the received RF input signal 2 can provide an absolute frequency, a searching algorithm can be envisaged which searches in the proximity of the frequency at which the channel is expected, until the channel is caught. Once the channel is being received, changes in the clock circuit specific reference frequency fclock can be tracked, corrected, and stored. In this way, frequency changes caused by aging, temperature changes, or changes in supply voltage can be taken care of. It should be noted that the device for receiving an RF input signal according to the first embodiment is a highly digitized direct-sampling multi-channel tuner. In such a highly digitized device, the first, second and third frequency translators 17, 18 and 20 respectively, the mixer 21, the IF filter 22, and the frequency comparator 23 which form the frequency feedback control loop can be implemented as software functions realized in the digital signal processing unit 10.

However, the invention is not limited to this but can also be applied to conventional devices for receiving an RF signal in which the RF input signal 2 is processed by analog circuitry, i.e. an analog mixer, decimation unit etc. In these more conventional devices an amount of software computations may be needed to determine the frequency error and to correct for it by means of e.g. fractional PLL. In this case, it may be necessary to provide additional hardware capable of performing these computations. In case of highly- digitized devices for receiving an RF signal, these computations can be performed in the digital signal processing unit without necessitating further additional hardware. Further, in case of a highly-digitized receiver, the determination of the frequency error may not require the frequency conversion step, since after sampling of the RF input signal 2, the signals contained in the input spectrum are available in the digital domain and frequencies and their deviation could also be determined directly, e.g. by means of Fast Fourier Transform (FFT). Applied to the highly-digitized direct-sampling RF tuner as in the first embodiment, the extraction of a frequency feedback signal is preferably not restricted to the information contained in a single channel as explained above but based on statistics derived from a plurality of channels. The statistical analysis that can be applied when deriving feedback from a plurality of channels will provide an increased accuracy. Several methods to recover and correct the reference frequency can be devised which allow tuning to an absolute frequency in the sampled domain. For example if known carrier tones (having a frequency f_tone) are present in the RF input signal, these can be used to determine the sampling frequency (f_sampie). By searching for the known tone or tones and measuring their time discrete frequency (fmeasured), the sampling frequency (and thus the clock circuit specific reference frequency) can be calculated back (according to f_measured = ttone/ tsample ) ■

If there are no fixed carrier tones in the RF input signal 2 but channels having a certain fixed spacing (e.g. in case of some TV signals), this spacing can be used to derive (estimate) the sampling frequency and thus the reference clock frequency. Even in the case that the exact channel distribution is not known, the known relationship between channel spacing can be used to derive the sampling frequency.

Further, the sampling frequency could be determined based on knowledge of the symbol rate of the transmitted signals, i.e. the rate at which symbols are recovered. In this case, by selecting any available signal and decoding this signal (using a carrier recovery loop), the relative rate at which symbols are recovered (as a fraction of the sampling rate) can be used to determine the sampling rate.

MODIFICATION As opposed to a low frequency reference signal from a quartz crystal in the range of tens of MHz, a high frequency reference signal in the GHz-range also has benefits for synthesis of spur- free LO signals in more traditional RF tuners with analog mixer. In this case, the high frequency reference signal is first divided down with a programmable division ratio M and then multiplied with a PLL using a feedback division ratio N in order to produce an LO frequency fLO according to the equation fLO = (N/M) x fclock without a need for a more complex fractional N synthesizer with a sigma-delta modulator. The crystal oscillator and associated PLL in such a device can be replaced by a resonator having lower accuracy as a reference source, e.g. by a bulk acoustic wave resonator. As described with respect to the first embodiment, the reference frequency inaccuracy can be dealt with by one-time calibration and a frequency feedback control loop.

SECOND EMBODIMENT

A second embodiment will now be described with respect to Figs. 5 and 6. First, a device for receiving an RF input signal will be described with respect to Fig. 5. Fig. 5 schematically shows the structure of a device for receiving a RF signal having an accurate frequency reference generated in a more traditional way. Elements which are identical to those of the first embodiment will be designated by the same reference numerals. As can be seen in Fig. 5, the analog RF input signal 2 is first sampled by the analog-digital converter 8 and then provided to a digital signal processing unit 10. The analog-digital converter 8 and the digital signal processing unit 10 are clocked by a reference clock signal having a clock circuit specific reference frequency fclock. This clock circuit specific reference frequency fclock is provided by a clock circuit 32 providing an accurate frequency reference such as a quartz crystal with PLL. A digital mixer 30 performing a digital mixing operation is provided in the digital signal processing unit 10. The sampled signal is frequency translated using the digital mixer 30. A digital mixer is comparable to an analog mixer. For example, a standard solution can be based on the CORDIC operation. Input signals are the output of the analog-digital converter and the time-discrete mixing frequency. A frequency translated version of the input signal is output. A decimation unit 31 is provided behind the digital mixer 30 for reducing the sampling rate, wherein the decimation factor is a constant. The decimation unit 31 outputs a digital output signal 33. Since the mixing is performed in the time-discrete domain, the mixing frequency is a function of the wanted channel frequency fch, the desired output frequency, and the clock frequency fclock. If the used clock frequency is incorrect, e.g. has a frequency offset, the digital mixer 30 performs incorrect frequency translation, resulting in an incorrect output frequency. Also for the decimation step to function correctly, the reference frequency fclock needs to be accurate. Thus, the receiving device with traditional clock generation circuitry requires a clock circuit 32 providing a reference clock signal having high frequency accuracy such as a quartz crystal and PLL.

In contrast, according to the second embodiment a device for receiving an RF input signal is provided which can operate with a clock circuit which does not provide high frequency accuracy. The device according to the second embodiment will be described with reference to Fig. 6. In the second embodiment, a clock circuit 34 generating a clock circuit specific reference frequency fclock with unknown frequency offset is provided. The analog digital converter 8 and the digital post-processing logic in the digital signal processing unit 10 are driven by this clock circuit specific reference frequency fclock. The digital logic contains a digital mixer 39, a sampling rate conversion block 37, a clock frequency extraction block 35, and a frequency remapping block 38. Now, the functioning of the device according to the second embodiment will be described. The analog-digital converter 8 samples the analog RF input signal 2 with an initially unknown clock circuit specific reference frequency fclock provided by the clock circuit 34. The sampled signal is passed to the digital mixer 39 as in the conventional case. However, the mixing frequency fcor supplied to the digital mixer 39 is equal to a frequency remapped version of the channel frequency fch. The function of the frequency remapping block 38 is to adjust the channel frequency fch such to account for the deviation in the clock circuit specific reference frequency fclock from an intended, ideal reference frequency.

The output of the digital mixer 39 is passed to the sampling rate conversion block 37 which is adapted to reduce the sampling rate of the signal in a way comparable to decimation in order to adjust for inaccuracies in the clock circuit specific reference frequency fclock.

A combination of the signals coming from the analog-digital converter 8, from the digital mixer 39, from the sampling rate conversion block 37, and an externally supplied frequency estimate 36 are passed to a clock frequency extraction block 35. The estimate could be a one-time measured value of the actual resonator frequency. Since the resonator frequency can vary with e.g. temperature or supply voltage etc., it is only an estimate. The clock frequency extraction block 35 is adapted to monitor these signals and extract frequency information from the signals in order to compute the actual clock frequency. To this end, all the examples mentioned with respect to the first embodiment could be used. The estimation of the clock circuit specific reference frequency can be a one-time process, i.e. a calibration, or an iterative process that refines the result over time such as that described with respect to the first embodiment.

The clock frequency extraction block 35 outputs a signal, e.g. an estimated clock frequency, which is used to control the frequency remapping block 38 and to control the sampling rate conversion block 37. Thus, by monitoring the signals which are sampled using the unknown clock circuit specific reference frequency fclock, post-correction can be applied to correct for the incorrect or inaccurate sampling frequency. The only requirement on the clock circuit specific reference frequency fclock is that the frequency has to be high enough to sample the complete incoming RF input signal 2 without aliasing distortions.

As a consequence, by allowing for an inaccurate frequency reference, increased design freedom and reduced costs are achieved. Typical examples of such frequency references which can be used in the clock circuit 34 are BAW and SAW resonators but also fully integrated LC or (R) C based oscillators could be envisioned. According to an alternative, the clock frequency extraction block 35 need not monitor all the signals from the analog-digital converter 8, from the digital mixer 39, from the sampling rate conversion block 37, and the externally supplied frequency estimate 36 but can also monitor only one or a plurality of these in order to extract the frequency information. Thus, the extracted frequency information is used to adapt the parameters of the frequency remapping block 38 and of the sampling rate conversion block 37. As a result, the final output of the device is corrected for the error in the clock circuit specific reference frequency and equals to the output that would have been obtained using a clock circuit providing an accurate frequency reference.

Claims

CLAIMS:

1. A device for receiving an RF input signal (2) and for processing the received RF input signals (2), the device comprising: an input (3) receiving the RF input signal (2); a clock circuit (34) generating a reference clock signal having a clock circuit specific reference frequency (fclock); and a frequency feedback control loop (17, 18, 20, 21, 22, 23; 35, 37, 38); wherein the frequency feedback control loop is adapted to extract frequency information from the RF input signal (2), to put the clock circuit specific reference frequency (fclock) into relation with the extracted frequency information and to correct for inaccuracies of the clock circuit specific reference frequency based on this relation.

2. The device according claim 1, wherein the frequency information is based on statistics derived from a plurality of RF input signals.

3. The device according to claim 1 or 2 adapted such that long term frequency variations of the reference clock signal are tracked by periodically storing correction results in non- volatile memory and retrieving these correction results from memory when the device is restarted.

4. The device according to any one of claims 1 to 3, wherein the clock circuit

(34) comprises an acoustic wave piezoelectric resonator or an LC or RC resonator (14).

5. The device according to any one of claims 1 to 4, the device further comprising: - an analog-digital converter (8) converting the RF input signal (2) to a digital signal; and a digital signal processing unit (10) digitally processing the digital signal; the analog-digital converter (8) and the digital signal processing unit (10) being clocked based on the clock circuit specific reference clock signal.

6. The device according to any one of claims 1 to 5, wherein the device is a direct-sampling multi-channel RF tuner.

7. The device according to any one of claims 1 to 6, wherein the frequency information is formed by at least one pre-determined carrier tone present in the RF input signal (2).

8. The device according to any one of claims 1 to 6, wherein the RF input signal (2) comprises a plurality of channels having fixed frequency spacing and the frequency information is formed by the fixed frequency spacing.

9. The device according to any one of claims 1 to 6, wherein the RF input signal (2) is a received digitally modulated signal comprising a pre-determined symbol rate at which symbols contained in the RF input signal are recovered and the frequency information is formed by the symbol rate.

10. A method for correcting for inaccuracies of a clock circuit specific reference frequency in a device for receiving an RF input signal and processing the received RF input signal; the method comprising the steps: applying an RF input signal (2) at an input (3) of the device; generating a reference clock signal by a clock circuit, the reference clock signal having a clock circuit specific reference frequency (fclock); extracting frequency information from the RF input signal (2); - putting the clock circuit specific reference frequency (fclock) into relation with the extracted frequency information; and correcting for inaccuracies of the clock circuit specific reference frequency based on this relation.

11. The method according to claim 10, wherein results for the correction are stored in memory periodically and retrieved from memory every time the device is powered on again.