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WO2009075257A1 - Substrat de silicium et son procédé de fabrication - Google Patents

Substrat de silicium et son procédé de fabrication Download PDF

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Publication number
WO2009075257A1
WO2009075257A1 PCT/JP2008/072311 JP2008072311W WO2009075257A1 WO 2009075257 A1 WO2009075257 A1 WO 2009075257A1 JP 2008072311 W JP2008072311 W JP 2008072311W WO 2009075257 A1 WO2009075257 A1 WO 2009075257A1
Authority
WO
WIPO (PCT)
Prior art keywords
silicon substrate
concentration
manufacturing
same
type silicon
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2008/072311
Other languages
English (en)
Japanese (ja)
Inventor
Shuichi Omote
Kazunari Kurita
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sumco Corp
Original Assignee
Sumco Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sumco Corp filed Critical Sumco Corp
Priority to JP2009545405A priority Critical patent/JPWO2009075257A1/ja
Publication of WO2009075257A1 publication Critical patent/WO2009075257A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/322—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
    • H01L21/3221—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering
    • H01L21/3225—Thermally inducing defects using oxygen present in the silicon body for intrinsic gettering
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/10—Integrated devices
    • H10F39/12—Image sensors
    • H10F39/15—Charge-coupled device [CCD] image sensors
    • H10F39/153—Two-dimensional or three-dimensional array CCD image sensors
    • H10F39/1532—Frame-interline transfer
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/10—Integrated devices
    • H10F39/12—Image sensors
    • H10F39/18—Complementary metal-oxide-semiconductor [CMOS] image sensors; Photodiode array image sensors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F77/00—Constructional details of devices covered by this subclass
    • H10F77/10—Semiconductor bodies
    • H10F77/14—Shape of semiconductor bodies; Shapes, relative sizes or dispositions of semiconductor regions within semiconductor bodies
    • H10F77/147—Shapes of bodies

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Solid State Image Pick-Up Elements (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
  • Recrystallisation Techniques (AREA)

Abstract

L'invention concerne un substrat de silicium pour un élément d'imagerie à l'état solide. Dans le substrat de silicium, sur un substrat de silicium de type p dopé par B est formée une couche épitaxiale contenant B à une concentration inférieure à celle du substrat de silicium de type p de façon à assurer et améliorer une performance de piégeage ('gettering'). Le substrat de silicium de type p a une concentration en B équivalente à une résistivité comprise entre 1 et 30 mΩcm, une concentration en C de 0,1 × 1016 à 15 × 1016 atomes/cm3 et une concentration en oxygène de 6,0 × 1017 à 18,0 × 1017 atomes/cm3.
PCT/JP2008/072311 2007-12-11 2008-12-09 Substrat de silicium et son procédé de fabrication Ceased WO2009075257A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2009545405A JPWO2009075257A1 (ja) 2007-12-11 2008-12-09 シリコン基板とその製造方法

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2007-320094 2007-12-11
JP2007320094 2007-12-11

Publications (1)

Publication Number Publication Date
WO2009075257A1 true WO2009075257A1 (fr) 2009-06-18

Family

ID=40755499

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2008/072311 Ceased WO2009075257A1 (fr) 2007-12-11 2008-12-09 Substrat de silicium et son procédé de fabrication

Country Status (3)

Country Link
JP (1) JPWO2009075257A1 (fr)
TW (1) TW200936825A (fr)
WO (1) WO2009075257A1 (fr)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2015190026A1 (fr) * 2014-06-11 2015-12-17 ソニー株式会社 Élément capteur d'image à semi-conducteur et son procédé de fabrication
JP2019192808A (ja) * 2018-04-26 2019-10-31 学校法人東北学院 半導体装置
US10693023B2 (en) 2015-06-12 2020-06-23 Canon Kabushiki Kaisha Imaging apparatus, method of manufacturing the same, and camera
JP7306536B1 (ja) 2022-06-14 2023-07-11 信越半導体株式会社 エピタキシャルウェーハの製造方法
CN120797198A (zh) * 2025-09-16 2025-10-17 金瑞泓微电子(嘉兴)有限公司 一种重掺硅单晶衬底制备硅外延片的方法及形成的外延片

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11164746B2 (en) 2018-06-26 2021-11-02 Taiwan Semiconductor Manufacturing Co., Ltd. Method of manufacturing semiconductor devices and a semiconductor device
JP7318518B2 (ja) * 2019-11-26 2023-08-01 信越半導体株式会社 固体撮像素子用のシリコン単結晶基板及びシリコンエピタキシャルウェーハ、並びに固体撮像素子
KR102847759B1 (ko) * 2021-11-04 2025-08-18 가부시키가이샤 사무코 실리콘 웨이퍼 및 에피택셜 실리콘 웨이퍼

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001322893A (ja) * 2000-05-09 2001-11-20 Shin Etsu Handotai Co Ltd シリコンエピタキシャルウェーハの製造方法
JP2002353146A (ja) * 2001-05-23 2002-12-06 Sony Corp 半導体基板の製造装置およびそれによる半導体基板を使用する半導体装置の製造方法
JP2007001847A (ja) * 2005-05-25 2007-01-11 Sumco Corp シリコンウェーハ及びその製造方法、並びにシリコン単結晶育成方法
JP2007149799A (ja) * 2005-11-25 2007-06-14 Shin Etsu Handotai Co Ltd アニールウェーハの製造方法およびアニールウェーハ
JP2007273959A (ja) * 2006-03-06 2007-10-18 Matsushita Electric Ind Co Ltd 光検出素子及びその製造方法

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1050715A (ja) * 1996-07-29 1998-02-20 Sumitomo Sitix Corp シリコンウェーハとその製造方法
JP4656788B2 (ja) * 2001-11-19 2011-03-23 信越半導体株式会社 シリコンエピタキシャルウェーハの製造方法
JP2006073580A (ja) * 2004-08-31 2006-03-16 Sumco Corp シリコンエピタキシャルウェーハ及びその製造方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001322893A (ja) * 2000-05-09 2001-11-20 Shin Etsu Handotai Co Ltd シリコンエピタキシャルウェーハの製造方法
JP2002353146A (ja) * 2001-05-23 2002-12-06 Sony Corp 半導体基板の製造装置およびそれによる半導体基板を使用する半導体装置の製造方法
JP2007001847A (ja) * 2005-05-25 2007-01-11 Sumco Corp シリコンウェーハ及びその製造方法、並びにシリコン単結晶育成方法
JP2007149799A (ja) * 2005-11-25 2007-06-14 Shin Etsu Handotai Co Ltd アニールウェーハの製造方法およびアニールウェーハ
JP2007273959A (ja) * 2006-03-06 2007-10-18 Matsushita Electric Ind Co Ltd 光検出素子及びその製造方法

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2015190026A1 (fr) * 2014-06-11 2015-12-17 ソニー株式会社 Élément capteur d'image à semi-conducteur et son procédé de fabrication
US10693023B2 (en) 2015-06-12 2020-06-23 Canon Kabushiki Kaisha Imaging apparatus, method of manufacturing the same, and camera
US11355658B2 (en) 2015-06-12 2022-06-07 Canon Kabushiki Kaisha Imaging apparatus, method of manufacturing the same, and camera
JP2019192808A (ja) * 2018-04-26 2019-10-31 学校法人東北学院 半導体装置
JP7306536B1 (ja) 2022-06-14 2023-07-11 信越半導体株式会社 エピタキシャルウェーハの製造方法
JP2023182155A (ja) * 2022-06-14 2023-12-26 信越半導体株式会社 エピタキシャルウェーハの製造方法
CN120797198A (zh) * 2025-09-16 2025-10-17 金瑞泓微电子(嘉兴)有限公司 一种重掺硅单晶衬底制备硅外延片的方法及形成的外延片

Also Published As

Publication number Publication date
JPWO2009075257A1 (ja) 2011-04-28
TW200936825A (en) 2009-09-01

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