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WO2009066760A1 - シストリックアレイ及び演算方法 - Google Patents

シストリックアレイ及び演算方法 Download PDF

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Publication number
WO2009066760A1
WO2009066760A1 PCT/JP2008/071220 JP2008071220W WO2009066760A1 WO 2009066760 A1 WO2009066760 A1 WO 2009066760A1 JP 2008071220 W JP2008071220 W JP 2008071220W WO 2009066760 A1 WO2009066760 A1 WO 2009066760A1
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WO
WIPO (PCT)
Prior art keywords
systolic array
trapezoidal
cells
row
intermediate result
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2008/071220
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English (en)
French (fr)
Inventor
Katsutoshi Seki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to EP08852353A priority Critical patent/EP2224347A1/en
Priority to US12/744,450 priority patent/US8589467B2/en
Priority to JP2009542599A priority patent/JP5353709B2/ja
Publication of WO2009066760A1 publication Critical patent/WO2009066760A1/ja
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/10—Complex mathematical operations
    • G06F17/16—Matrix or vector computation, e.g. matrix-matrix or matrix-vector multiplication, matrix factorization
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
    • G06F15/8046—Systolic arrays

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Pure & Applied Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Analysis (AREA)
  • Computing Systems (AREA)
  • Mathematical Optimization (AREA)
  • Data Mining & Analysis (AREA)
  • Computer Hardware Design (AREA)
  • Computational Mathematics (AREA)
  • Algebra (AREA)
  • Software Systems (AREA)
  • Databases & Information Systems (AREA)
  • Complex Calculations (AREA)
  • Radio Transmission System (AREA)
  • Variable-Direction Aerials And Aerial Arrays (AREA)

Abstract

　各セルが同一演算回路で実現され、該演算回路の動作率が高く、かつ前記演算回路の処理遅延がセルの種類およびステップに依らず一定でセル間の接続関係が固定であるため同期制御回路が不要な複素行列演算シストリックアレイを提供する。三角シストリックアレイ１０００と四角シストリックアレイ２０００を組み合わせた台形シストリックアレイの下辺に線形シストリックアレイを３０００付加し、セル間の接続が固定になるように、台形シストリックアレイの各行から下行に出力される中間結果を、複素ＭＦＡアルゴリズムの中間結果に対し位相をずらしたものとし、該位相ずれを次行で吸収させ、台形シストリックアレイの最終行から出力される中間結果の位相ずれを線形シストリックアレイ３０００で補正することと、各セルが、ベクトル角度算出／ベクトル回転／除算／積和演算を一定遅延で処理するＣＯＲＤＩＣ回路で実現される。
PCT/JP2008/071220 2007-11-22 2008-11-21 シストリックアレイ及び演算方法 Ceased WO2009066760A1 (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
EP08852353A EP2224347A1 (en) 2007-11-22 2008-11-21 Systolic array and calculation method
US12/744,450 US8589467B2 (en) 2007-11-22 2008-11-21 Systolic array and calculation method
JP2009542599A JP5353709B2 (ja) 2007-11-22 2008-11-21 シストリックアレイ及び演算方法

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2007-302536 2007-11-22
JP2007302536 2007-11-22

Publications (1)

Publication Number Publication Date
WO2009066760A1 true WO2009066760A1 (ja) 2009-05-28

Family

ID=40667582

Family Applications (1)

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PCT/JP2008/071220 Ceased WO2009066760A1 (ja) 2007-11-22 2008-11-21 シストリックアレイ及び演算方法

Country Status (4)

Country Link
US (1) US8589467B2 (ja)
EP (1) EP2224347A1 (ja)
JP (1) JP5353709B2 (ja)
WO (1) WO2009066760A1 (ja)

Cited By (1)

* Cited by examiner, † Cited by third party
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US12260248B2 (en) 2017-09-21 2025-03-25 Huawei Technologies Co., Ltd. Systems and methods for performing multiplication of one or more matrices using multi-thread systolic arrays

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US8589467B2 (en) * 2007-11-22 2013-11-19 Nec Corporation Systolic array and calculation method
US9014249B2 (en) 2012-11-02 2015-04-21 Harris Corporation Communications receiver with channel identification using A-priori generated gain vectors and associated methods
US8824603B1 (en) * 2013-03-01 2014-09-02 Futurewei Technologies, Inc. Bi-directional ring-bus architecture for CORDIC-based matrix inversion
US20160267111A1 (en) * 2015-03-11 2016-09-15 Microsoft Technology Licensing, Llc Two-stage vector reduction using two-dimensional and one-dimensional systolic arrays
US10268886B2 (en) 2015-03-11 2019-04-23 Microsoft Technology Licensing, Llc Context-awareness through biased on-device image classifiers
US10055672B2 (en) 2015-03-11 2018-08-21 Microsoft Technology Licensing, Llc Methods and systems for low-energy image classification
US11507429B2 (en) 2017-09-14 2022-11-22 Electronics And Telecommunications Research Institute Neural network accelerator including bidirectional processing element array
TWI841330B (zh) * 2023-03-31 2024-05-01 國立臺灣大學 高斯消去計算系統及高斯消去計算方法

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US4823299A (en) * 1987-04-01 1989-04-18 The United States Of America As Represented By The Administrator Of The National Aeronautics And Space Administration Systolic VLSI array for implementing the Kalman filter algorithm
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US7218624B2 (en) * 2001-11-14 2007-05-15 Interdigital Technology Corporation User equipment and base station performing data detection using a scalar array
JP4657998B2 (ja) * 2006-07-21 2011-03-23 ルネサスエレクトロニクス株式会社 シストリックアレイ
US8589467B2 (en) * 2007-11-22 2013-11-19 Nec Corporation Systolic array and calculation method

Non-Patent Citations (6)

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Title
"2nd Signal Processing Education Workshop", PROCEEDINGS OF 2002 IEEE, 13 October 2002 (2002-10-13), pages 350 - 355
J. G. NASH: "Modified Faddeeva algorithm for concurrent execution of linear algebraic operations", IEEE TRANS. COMPUTERS, vol. 37, no. 2, 1988, pages 129 - 137
KATSUTOSHI S. ET AL.: "Signal Processing Systems, 2007 IEEE Workshop on", 19 October 2007, article "A Cordic-Based Reconfigrable Systolic Array Processor for MIMO-OFDM Wireless Communications", pages: 639 - 644, XP031164039 *
M.OTTE; J.GOTZE; M.BUCKER: "Matrix based signal processing on a reconfigurable hardware accelerator", DIGITAL SIGNAL PROCESSING WORKSHOP, 2002
NASH J.G. ET AL.: "Computers, IEEE Transactions on", vol. 37, February 1988, IEEE, article "Modified Faddeeva algorithm for concurrent execution of linear algebraic operations", pages: 129 - 137, XP008134508 *
OTTE M. ET AL.: "Digital Signal Processing Workshop, 2002 and the 2nd Signal Processing Education Workshop. Proceedings of 2002 IEEE 10th", 16 October 2002, IEEE, article "Matrix based signal processing on a reconfigurable hardware accelerator", pages: 350 - 355, XP010657825 *

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US12260248B2 (en) 2017-09-21 2025-03-25 Huawei Technologies Co., Ltd. Systems and methods for performing multiplication of one or more matrices using multi-thread systolic arrays

Also Published As

Publication number Publication date
JP5353709B2 (ja) 2013-11-27
US20100250640A1 (en) 2010-09-30
EP2224347A1 (en) 2010-09-01
US8589467B2 (en) 2013-11-19
JPWO2009066760A1 (ja) 2011-04-07

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