WO2009063588A1 - Dispositif à semi-conducteur et procédé de fabrication de celui-ci - Google Patents
Dispositif à semi-conducteur et procédé de fabrication de celui-ci Download PDFInfo
- Publication number
- WO2009063588A1 WO2009063588A1 PCT/JP2008/002758 JP2008002758W WO2009063588A1 WO 2009063588 A1 WO2009063588 A1 WO 2009063588A1 JP 2008002758 W JP2008002758 W JP 2008002758W WO 2009063588 A1 WO2009063588 A1 WO 2009063588A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- region
- trench section
- gate electrode
- conductivity type
- semiconductor substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Ceased
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Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/791—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions
- H10D30/797—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions being in source or drain regions, e.g. SiGe source or drain
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/01—Manufacture or treatment
- H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
- H10D30/027—Manufacture or treatment of FETs having insulated gates [IGFET] of lateral single-gate IGFETs
- H10D30/0275—Manufacture or treatment of FETs having insulated gates [IGFET] of lateral single-gate IGFETs forming single crystalline semiconductor source or drain regions resulting in recessed gates, e.g. forming raised source or drain regions
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/01—Manufacture or treatment
- H10D62/021—Forming source or drain recesses by etching e.g. recessing by etching and then refilling
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
- H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
- H10D84/0128—Manufacturing their channels
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
- H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
- H10D84/013—Manufacturing their source or drain regions, e.g. silicided source or drain regions
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
- H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
- H10D84/0151—Manufacturing their isolation regions
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
- H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
- H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
- H10D84/0167—Manufacturing their channels
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
- H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
- H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
- H10D84/017—Manufacturing their source or drain regions, e.g. silicided source or drain regions
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
- H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
- H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
- H10D84/0188—Manufacturing their isolation regions
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/02—Manufacture or treatment characterised by using material-based technologies
- H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
- H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/01—Manufacture or treatment
- H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
- H10D30/0212—Manufacture or treatment of FETs having insulated gates [IGFET] using self-aligned silicidation
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/601—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
- H10D62/82—Heterojunctions
- H10D62/822—Heterojunctions comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
Landscapes
- Insulated Gate Type Field-Effect Transistor (AREA)
- Element Separation (AREA)
Abstract
Un dispositif à semi-conducteur est doté d'une région d'isolation d'élément (11a) formée dans un substrat semi-conducteur (10) ; d'une région active, composée du substrat semi-conducteur (10) entourée par la région d'isolation d'élément (11a) et comportant une section de tranchée ; un transistor MIS d'un premier type de conductivité comportant une électrode de grille (13) formée sur la région active, une première paroi latérale (19) formée entre l'électrode de grille (13) et une section de tranchée sur une surface latérale de l'électrode de grille (13) en vue en plan, et une couche de mélange cristal-silicium (21) d'un premier type de conductivité appliquée dans la section de tranchée ; une région de substrat disposée entre la section de tranchée et les régions d'isolation d'élément (11a, 11b) et composée du substrat semi-conducteur (10) ; et une région d'impureté (22) d'un premier type de conductivité formée dans la région de substrat. La couche de mélange cristal-silicium (21) permet de générer une contrainte sur une région de canal dans la région active.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US12/482,945 US8502301B2 (en) | 2007-11-16 | 2009-06-11 | Semiconductor device and method for fabricating the same |
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2007297639A JP5107680B2 (ja) | 2007-11-16 | 2007-11-16 | 半導体装置 |
| JP2007-297639 | 2007-11-16 |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| US12/482,945 Continuation US8502301B2 (en) | 2007-11-16 | 2009-06-11 | Semiconductor device and method for fabricating the same |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| WO2009063588A1 true WO2009063588A1 (fr) | 2009-05-22 |
Family
ID=40638444
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| PCT/JP2008/002758 Ceased WO2009063588A1 (fr) | 2007-11-16 | 2008-10-01 | Dispositif à semi-conducteur et procédé de fabrication de celui-ci |
Country Status (3)
| Country | Link |
|---|---|
| US (1) | US8502301B2 (fr) |
| JP (1) | JP5107680B2 (fr) |
| WO (1) | WO2009063588A1 (fr) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103219340A (zh) * | 2012-01-23 | 2013-07-24 | 台湾积体电路制造股份有限公司 | 用于具有线端延长的晶体管的结构和方法 |
| US12218239B2 (en) | 2012-01-23 | 2025-02-04 | Mosaid Technologies Incorporated | Structure and method for providing line end extensions for fin-type active regions |
Families Citing this family (29)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2010003812A (ja) * | 2008-06-19 | 2010-01-07 | Fujitsu Microelectronics Ltd | 半導体装置およびその製造方法 |
| JP5668277B2 (ja) | 2009-06-12 | 2015-02-12 | ソニー株式会社 | 半導体装置 |
| US8497528B2 (en) | 2010-05-06 | 2013-07-30 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for fabricating a strained structure |
| KR101574107B1 (ko) * | 2010-02-11 | 2015-12-04 | 삼성전자 주식회사 | 반도체 장치의 제조 방법 |
| US9673328B2 (en) | 2010-05-28 | 2017-06-06 | Taiwan Semiconductor Manufacturing Company, Ltd. | Structure and method for providing line end extensions for fin-type active regions |
| US8377780B2 (en) * | 2010-09-21 | 2013-02-19 | International Business Machines Corporation | Transistors having stressed channel regions and methods of forming transistors having stressed channel regions |
| CN102456739A (zh) * | 2010-10-28 | 2012-05-16 | 中国科学院微电子研究所 | 半导体结构及其形成方法 |
| US9117843B2 (en) * | 2011-09-14 | 2015-08-25 | Taiwan Semiconductor Manufacturing Company, Ltd. | Device with engineered epitaxial region and methods of making same |
| US9246004B2 (en) * | 2011-11-15 | 2016-01-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Strained structures of semiconductor devices |
| US8735991B2 (en) | 2011-12-01 | 2014-05-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | High gate density devices and methods |
| US8803241B2 (en) | 2012-06-29 | 2014-08-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | Dummy gate electrode of semiconductor device |
| US10134895B2 (en) | 2012-12-03 | 2018-11-20 | Stmicroelectronics, Inc. | Facet-free strained silicon transistor |
| US9419126B2 (en) * | 2013-03-15 | 2016-08-16 | GlobalFoundries, Inc. | Integrated circuits and methods for fabricating integrated circuits with active area protection |
| KR102025309B1 (ko) * | 2013-08-22 | 2019-09-25 | 삼성전자 주식회사 | 반도체 장치 및 그 제조 방법 |
| US9379106B2 (en) | 2013-08-22 | 2016-06-28 | Samsung Electronics Co., Ltd. | Semiconductor devices having 3D channels, and methods of fabricating semiconductor devices having 3D channels |
| US9245971B2 (en) * | 2013-09-27 | 2016-01-26 | Qualcomm Incorporated | Semiconductor device having high mobility channel |
| FR3011678B1 (fr) * | 2013-10-07 | 2017-01-27 | St Microelectronics Crolles 2 Sas | Procede de relaxation des contraites mecaniques transversales dans la region active d'un transistor mos, et circuit integre correspondant |
| US9165944B2 (en) * | 2013-10-07 | 2015-10-20 | Globalfoundries Inc. | Semiconductor device including SOI butted junction to reduce short-channel penalty |
| KR102085525B1 (ko) | 2013-11-27 | 2020-03-09 | 삼성전자 주식회사 | 반도체 장치 및 그 제조 방법 |
| KR102200922B1 (ko) | 2014-07-17 | 2021-01-11 | 삼성전자주식회사 | 절연 패턴을 갖는 반도체 소자 및 그 형성 방법 |
| KR102214023B1 (ko) | 2014-12-03 | 2021-02-09 | 삼성전자주식회사 | 반도체 장치 |
| KR102448597B1 (ko) | 2015-06-24 | 2022-09-27 | 삼성전자주식회사 | 반도체 장치 |
| CN106340455B (zh) * | 2015-07-06 | 2021-08-03 | 联华电子股份有限公司 | 半导体元件及其制作方法 |
| KR102563923B1 (ko) * | 2018-04-10 | 2023-08-04 | 삼성전자 주식회사 | 집적회로 소자 |
| KR102546305B1 (ko) * | 2018-04-20 | 2023-06-21 | 삼성전자주식회사 | 집적회로 소자 |
| US10910277B2 (en) | 2018-06-12 | 2021-02-02 | United Microelectronics Corp. | Semiconductor device and method for fabricating the same |
| CN113314467B (zh) * | 2020-02-26 | 2024-08-27 | 联华电子股份有限公司 | 半导体元件及其制作方法 |
| US11854863B2 (en) * | 2021-06-24 | 2023-12-26 | Taiwan Semiconductor Manufacturing Company Ltd. | Semiconductor device including an isolation region having an edge being covered and manufacturing method for the same |
| CN115799161B (zh) * | 2023-01-09 | 2023-05-09 | 广州粤芯半导体技术有限公司 | 半导体结构及其制备方法 |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH10326892A (ja) * | 1997-05-23 | 1998-12-08 | Nec Corp | 半導体装置およびその製造方法 |
| JPH11163325A (ja) * | 1997-11-27 | 1999-06-18 | Matsushita Electron Corp | 半導体装置及びその製造方法 |
| JP2006013082A (ja) * | 2004-06-24 | 2006-01-12 | Fujitsu Ltd | 半導体装置とその製造方法、及び半導体装置の評価方法 |
| WO2006006972A1 (fr) * | 2004-06-24 | 2006-01-19 | International Business Machines Corporation | Procede et dispositif cmos ameliore a couche contrainte contenant du silicium |
| JP2007110098A (ja) * | 2005-09-13 | 2007-04-26 | Infineon Technologies Ag | 応力変形させた半導体装置およびその製造方法 |
| JP2007220808A (ja) * | 2006-02-15 | 2007-08-30 | Toshiba Corp | 半導体装置及びその製造方法 |
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| KR100350056B1 (ko) * | 2000-03-09 | 2002-08-24 | 삼성전자 주식회사 | 다마신 게이트 공정에서 자기정렬콘택패드 형성 방법 |
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| JP4375619B2 (ja) | 2004-05-26 | 2009-12-02 | 富士通マイクロエレクトロニクス株式会社 | 半導体装置の製造方法 |
| KR100583968B1 (ko) * | 2004-08-03 | 2006-05-26 | 삼성전자주식회사 | 스페이스 트랜치들을 갖는 불 휘발성 메모리 장치들 및 그형성방법들 |
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| JP2007157924A (ja) * | 2005-12-02 | 2007-06-21 | Fujitsu Ltd | 半導体装置および半導体装置の製造方法 |
| US7922757B2 (en) * | 2006-10-23 | 2011-04-12 | Rex Medical, L.P. | Vascular conduit |
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-
2007
- 2007-11-16 JP JP2007297639A patent/JP5107680B2/ja not_active Expired - Fee Related
-
2008
- 2008-10-01 WO PCT/JP2008/002758 patent/WO2009063588A1/fr not_active Ceased
-
2009
- 2009-06-11 US US12/482,945 patent/US8502301B2/en not_active Expired - Fee Related
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH10326892A (ja) * | 1997-05-23 | 1998-12-08 | Nec Corp | 半導体装置およびその製造方法 |
| JPH11163325A (ja) * | 1997-11-27 | 1999-06-18 | Matsushita Electron Corp | 半導体装置及びその製造方法 |
| JP2006013082A (ja) * | 2004-06-24 | 2006-01-12 | Fujitsu Ltd | 半導体装置とその製造方法、及び半導体装置の評価方法 |
| WO2006006972A1 (fr) * | 2004-06-24 | 2006-01-19 | International Business Machines Corporation | Procede et dispositif cmos ameliore a couche contrainte contenant du silicium |
| JP2007110098A (ja) * | 2005-09-13 | 2007-04-26 | Infineon Technologies Ag | 応力変形させた半導体装置およびその製造方法 |
| JP2007220808A (ja) * | 2006-02-15 | 2007-08-30 | Toshiba Corp | 半導体装置及びその製造方法 |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103219340A (zh) * | 2012-01-23 | 2013-07-24 | 台湾积体电路制造股份有限公司 | 用于具有线端延长的晶体管的结构和方法 |
| CN103219340B (zh) * | 2012-01-23 | 2016-04-20 | 台湾积体电路制造股份有限公司 | 用于具有线端延长的晶体管的结构和方法 |
| US12218239B2 (en) | 2012-01-23 | 2025-02-04 | Mosaid Technologies Incorporated | Structure and method for providing line end extensions for fin-type active regions |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2009123997A (ja) | 2009-06-04 |
| JP5107680B2 (ja) | 2012-12-26 |
| US20090242995A1 (en) | 2009-10-01 |
| US8502301B2 (en) | 2013-08-06 |
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