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WO2009040509A1 - A multilayer semiconductor structure, a bifet includin such a structure, and a multilayer semiconductor substrate - Google Patents

A multilayer semiconductor structure, a bifet includin such a structure, and a multilayer semiconductor substrate Download PDF

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Publication number
WO2009040509A1
WO2009040509A1 PCT/GB2008/003216 GB2008003216W WO2009040509A1 WO 2009040509 A1 WO2009040509 A1 WO 2009040509A1 GB 2008003216 W GB2008003216 W GB 2008003216W WO 2009040509 A1 WO2009040509 A1 WO 2009040509A1
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WO
WIPO (PCT)
Prior art keywords
layer
multilayer semiconductor
semiconductor substrate
layers
etch stop
Prior art date
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Ceased
Application number
PCT/GB2008/003216
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French (fr)
Inventor
John Stephen Atherton
Matthew Francis O'keefe
Michael Charles Clausen
Robert Grey
Richard Alun Davies
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RFMD UK Ltd
Original Assignee
Filtronic Compound Semiconductors Ltd
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Publication of WO2009040509A1 publication Critical patent/WO2009040509A1/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D10/00—Bipolar junction transistors [BJT]
    • H10D10/80—Heterojunction BJTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/05—Manufacture or treatment characterised by using material-based technologies using Group III-V technology
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/40—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels
    • H10D30/47—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having 2D charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
    • H10D30/471—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT]
    • H10D30/473—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT] having confinement of carriers by multiple heterojunctions, e.g. quantum well HEMT
    • H10D30/4732—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT] having confinement of carriers by multiple heterojunctions, e.g. quantum well HEMT using Group III-V semiconductor material
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/177—Base regions of bipolar transistors, e.g. BJTs or IGBTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/40—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00 with at least one component covered by groups H10D10/00 or H10D18/00, e.g. integration of IGFETs with BJTs
    • H10D84/401—Combinations of FETs or IGBTs with BJTs

Definitions

  • a MULTILAYER SEMICONDUCTOR STRUCTURE A BiFET INCLUDING SUCH A STRUCTURE, AND A MULTILAYER SEMICONDUCTOR
  • the present invention relates to a multilayer semiconductor structure, a BiFET including such a structure and also to a multilayer semiconductor substrate for the manufacture of such a structure. More particularly, but not exclusively, the present invention relates to a
  • BiFET in which the sub-collector layer of the HBT is a different layer to the cap layer of the FET.
  • FETs field effect transistors
  • HBTs heteroj unction bipolar transistor
  • US 7015519 discloses an integrated FET/HBT device.
  • the integrated device comprises a contact layer shared by the FET and HBT.
  • the contact layer acts as a cap layer on the FET.
  • the contact layer acts a sub-collector layer.
  • the multilayer semiconductor structure according to the invention seeks to overcome these problems.
  • the present invention provides a multilayer semiconductor structure divided into HBT and FET portions comprising a first epitaxial structure shared by the HBT and FET portions, the epitaxial structure comprising layers suitable for forming the layers of a FET beneath a FET gate;
  • the FET portion comprising an aperture extending through the cap layer and first etch stop layer to the first epitaxial structure
  • the second epitaxial structure comprising layers suitable for forming a portion of a HBT.
  • the resulting BiFET does not suffer from thermal runaway.
  • no design comprise is necessary for the thickness of the cap layer.
  • the multilayer semiconductor structure further comprises a metal gate contact on the first epitaxial structure within the aperture.
  • the multilayer semiconductor structure can further comprise an ohmic metal source contact and an ohmic metal drain contact arranged on the cap layer on opposite sides of the aperture.
  • the first etch stop layer can be AlInP.
  • the second etch stop layer can be AIInP.
  • the cap layer can be GaAs.
  • the composition of the AlInP layer is Al x Ini_ x P, wherein x is in the range 0.05 to 0.95, more preferably 0.4 to 0.6, more preferably 0.5.
  • the first epitaxial structure can comprise a buffer layer, preferably an AlGaAs or GaAs buffer layer.
  • the first epitaxial structure can comprise a set of MESFET epitaxial layers.
  • the MESFET layer can comprise an undoped spacer layer and a doped channel layer.
  • the spacer layer and channel layer can be GaAs layers.
  • the first epitaxial structure comprises a set of pHEMT layers.
  • the pHEMT layers can comprise a barrier layer, a channel layer and a Schottky barrier layer.
  • the barrier layer can be GaAs.
  • the barrier layer can be AlGaAs.
  • the barrier layer can be AlInAs or InGaP.
  • the Schottky barrier layer can be AlGaAs or InGaP.
  • the Schottky barrier layer can be AlInAs.
  • the channel layer can be InGaAs.
  • the second epitaxial layer can comprise a sub-collector layer, a collector layer, a base layer and an emitter layer.
  • the base layer can comprise a GaAs layer.
  • the base layer can further comprise an AIInP cover layer on the GaAs layer.
  • the collector layer can comprise a GaAs layer.
  • the sub-collector layer can comprise a GaAs layer.
  • BiFET comprising a multilayer semiconductor structure divided into HBT and FET portions comprising
  • the epitaxial structure comprising layers suitable for forming the layers of a FET beneath a FET gate;
  • the FET portion comprising an aperture extending through the cap layer and first etch stop layer to the first epitaxial structure
  • the second epitaxial structure comprising layers suitable for forming a portion of a HBT
  • a multilayer semiconductor substrate for manufacture of a combined FET and HBT comprising
  • a first epitaxial structure comprising layers suitable for forming the layers of a FET beneath a FET gate; an etch stop layer on the first epitaxial structure;
  • the second epitaxial structure comprising layers suitable for forming a portion of a HBT.
  • the first etch stop layer can be AlInP.
  • the second etch stop layer can be AlInP.
  • the composition of the AlInP layer is Al x Ini. x P, wherein x is in the range 0.05 to 0.95, preferably in the range 0.4 to 0.6, more preferably 0.5.
  • the first epitaxial layer comprises a buffer layer, preferably an AlGaAs or GaAs buffer layer.
  • the first epitaxial structure can comprise a set of MESFET epitaxial layers.
  • the set of MESFET layers can comprise an undoped spacer layer and a doped channel layer.
  • the spacer layer and channel layer can be GaAs layers.
  • the first epitaxial structure comprises a set of pHEMT layers.
  • the pHEMT layers can comprise a barrier layer, a channel layer and a Schottky barrier layer.
  • the barrier layer can be GaAs or AlGaAs.
  • the barrier layer can be AlInAs or InGaP.
  • the channel layer can be InGaAs.
  • the Schottky barrier layer can be AlGaAs or InGaP.
  • the Schottky barrier layer can be AlInAs.
  • the cap layer can be GaAs.
  • the second epitaxial structure comprises a sub-collector layer, a collector layer, a base layer and an emitter layer.
  • the base layer can comprise a GaAs layer.
  • the collector layer can comprise a GaAs layer.
  • the sub-collector layer can comprise a GaAs layer.
  • Figure 1 shows a BiFET according to the invention in cross section
  • Figure 2 shows a multilayer semiconductor substrate according to the invention in cross section.
  • the BiFET 1 comprises a multilayer semiconductor structure divided into HBT and FET portions 2,3.
  • the multilayer semiconductor structure comprises a first epitaxial structure 4 shared by the FET and HBT portions 2,3.
  • the first epitaxial structure 4 comprises layers suitable for forming layers of a FET beneath a FET gate 5.
  • the first epitaxial structure 4 comprises a buffer layer 6.
  • the buffer layer 6 is typically GaAs or AlGaAs.
  • Arranged on the buffer layer 6 are a set of pHEMT layers 7.
  • the pHEMT layers 7 comprise a barrier layer 8. This is typically GaAs or AlGaAs.
  • the barrier layer 8 could also be InAlAs or InGaP.
  • a Schottky barrier layer 9 This is typically AlGaAs or InGaP. A further alternative is AlInAs. Sandwiched between the barrier layer 8 and Schottky barrier layer 9 is a channel layer 10 typically an InGaAs layer. At least one of the barrier layer 8 and the Schottky layer 9 comprises at least one silicon layer 11 which act as electron donor layers for the channel layer 10. Arranged on the Schottky barrier layer 9 is a GaAs cover layer 12. The operation of a pHEMT is well known and will not be described in detail
  • AlInP first etch stop layer 13 shared between the FET and HBT regions 2,3.
  • GaAs cap layer 14 shared between HBT and FET regions 2,3.
  • An aperture 15 extends through the cap layer 14 and first etch stop layer 13 to the first epitaxial structure 4 in the FET region 3.
  • Arranged in the aperture 15 on the first epitaxial structure 4 is the metal gate contact 5.
  • Arranged on the cap layer 14 on either side of the metal gate 5 contact are ohmic metal source and drain contacts 16,17.
  • a second AlInP etch stop layer 18 Arranged on the second etch stop layer 18 is a second epitaxial structure 19 comprising layers suitable for forming a portion of a HBT.
  • the second epitaxial structure 19 comprises a GaAs sub-collector layer 20 arranged on the second etch stop layer 18.
  • Arranged on the sub-collector layer 20 is a GaAs collector layer 21.
  • Arranged on the collector layer 21 is a GaAs base layer 22.
  • the base layer 22 is covered by an optional AlInP cover layer 23 to reduce recombination current in the HBT.
  • Arranged on the cover layer 23 Arranged on the cover layer 23 is a GaAs emitter layer 24.
  • an InGaAs contact layer 25 Arranged on the sub-collector layer 20 is an ohmic metal collector contact 26. Arranged on the cover layer 23 is a metal base contact 27. Finally, arranged on the contact layer 25 is a metal emitter contact 28.
  • a HBT The operation of a HBT is known and will not be described in detail.
  • the FET portion 3 and the HBT portion 2 are electrically isolated from each other by an isolation portion 29 formed by implant isolation of a section through the multilayer semiconductor structure.
  • the BiFET 1 of the invention has separate sub-collector and cap layers 20,14 separated by an etch stop layer 18. Accordingly, in contrast to known BiFETs, the BiFET 1 of the invention does not suffer from thermal runaway.
  • the etch stop layers 13,18 are AlInP. More Particularly, the composition of the etch stop layers is Al x In 1 - X P wherein x is in the range 0.05 to 0.95, preferably 0.4 to 0.6, more preferably 0.5.
  • the first epitaxial structure 4 comprises a set of MESFET layers.
  • the MESFET layers comprise an undoped GaAs spacer layer and a doped GaAs channel layer. Again, the operation of the MESFET is well known and will not be described in detail.
  • the substrate 30 comprises a first epitaxial structure 4 comprising layers suitable for forming the layers of a FET beneath a FET gate.
  • the first epitaxial structure 4 has been described in detail with reference to figure 1.
  • first AlInP etch stop layer 12 Arranged on the first epitaxial structure 4 is a first AlInP etch stop layer 12. Arranged on the first etch stop layer 12 is a GaAs cap layer 14. Arranged on the cap layer 14 is a second AlInP etch stop layer 18. Finally, arranged on the second etch stop layer 18 is a second epitaxial structure 19 comprising a sub-collector, collector, base and emitter layers (not shown). The second epitaxial structure 19 has been described in detail with reference to figure 1.
  • the multilayer semiconductor substrate 30 according to the invention can be used to manufacture a BiFET similar to that of figure 1 although lacking the optional cover layer 23 and contact layer 25.
  • the multilayer semiconductor substrate 30 further comprises one or both of these optional layers.
  • etch stop layers 12,18 comprise both Aluminium and Phosphorous (preferably AlInP). This enables etching by both wet and dry routes. This enables the manufacture of a BiFET 1 having either vertical or shaped structures so allowing for greater flexibility in the design of the BiFET 1.
  • references to layers comprising three components including AlInP, AlGaAs, AlInAs, InGaP and InGaAs. More generally, these may be written as A x Bi. x C.
  • AlInP specific compositional ranges of x have not been specified. Suitable ranges for x are well known to one skilled in the art of device manufacture and are defined by the desired device characteristics and also by the requirement to keep the difference in lattice spacing between adjacent layers within acceptable ranges to reduce device stress.
  • x is typically in the range 0.05 to 0.95, more preferably 0.4 to 0.6, more preferably 0.5.

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  • Chemical & Material Sciences (AREA)
  • Engineering & Computer Science (AREA)
  • Materials Engineering (AREA)
  • Junction Field-Effect Transistors (AREA)
  • Bipolar Transistors (AREA)

Abstract

A multilayer semiconductor structure divided into HBT and FET portions comprising a first epitaxial structure shared by the HBT and FET portions, the epitaxial structure comprising layers suitable for forming the layers of a FET beneath a FET gate; a first etch stop layer on the first epitaxial structure shared by the HBT and FET portions; a cap layer on the first etch stop layer shared by the HBT and FET portions; the FET portion comprising an aperture extending through the cap layer and. first etch stop layer to the first epitaxial structure; a second etch stop layer on the HBT portion of the cap layer; and a second epitaxial structure on the second etch stop layer, the second epitaxial structure comprising layers suitable for forming a portion of a HBT.

Description

A MULTILAYER SEMICONDUCTOR STRUCTURE, A BiFET INCLUDING SUCH A STRUCTURE, AND A MULTILAYER SEMICONDUCTOR
SUBSTRATE
The present invention relates to a multilayer semiconductor structure, a BiFET including such a structure and also to a multilayer semiconductor substrate for the manufacture of such a structure. More particularly, but not exclusively, the present invention relates to a
BiFET in which the sub-collector layer of the HBT is a different layer to the cap layer of the FET.
The integration of field effect transistors (FETs) and heteroj unction bipolar transistor (HBTs) into a single structure (a BiFET) is attractive as it enables a number of design possibilities. These include bias enabled switching, stage bypassing, adaptive gate switching and integration of amplifier and switch.
US 7015519 (ANADIGICS INC) discloses an integrated FET/HBT device. The integrated device comprises a contact layer shared by the FET and HBT. Within the FET the contact layer acts as a cap layer on the FET. Within the HBT the contact layer acts a sub-collector layer.
This sharing of a common layer increases the compactness of the integrated device. However, this tends to result in thermal runaway of the device. In addition, the HBT and FET optimally require different thickness of contact layer so resulting in a design trade off in the final design.
The multilayer semiconductor structure according to the invention seeks to overcome these problems.
Accordingly, in a first aspect, the present invention provides a multilayer semiconductor structure divided into HBT and FET portions comprising a first epitaxial structure shared by the HBT and FET portions, the epitaxial structure comprising layers suitable for forming the layers of a FET beneath a FET gate;
a first etch stop layer on the first epitaxial structure shared by the HBT and FET portions;
a cap layer on the first etch stop layer shared by the HBT and FET portions;
the FET portion comprising an aperture extending through the cap layer and first etch stop layer to the first epitaxial structure;
a second etch stop layer on the HBT portion of the cap layer; and
a second epitaxial structure on the second etch stop layer, the second epitaxial structure comprising layers suitable for forming a portion of a HBT.
By connecting appropriate contacts to the multilayer semiconductor structure it acts as a
BiFET. As the second epitaxial structure is separated from the cap layer, rather than sharing a layer, the resulting BiFET does not suffer from thermal runaway. In addition, no design comprise is necessary for the thickness of the cap layer.
Preferably the multilayer semiconductor structure further comprises a metal gate contact on the first epitaxial structure within the aperture.
The multilayer semiconductor structure can further comprise an ohmic metal source contact and an ohmic metal drain contact arranged on the cap layer on opposite sides of the aperture.
The first etch stop layer can be AlInP.
The second etch stop layer can be AIInP. The cap layer can be GaAs.
Preferably, the composition of the AlInP layer is AlxIni_xP, wherein x is in the range 0.05 to 0.95, more preferably 0.4 to 0.6, more preferably 0.5.
The first epitaxial structure can comprise a buffer layer, preferably an AlGaAs or GaAs buffer layer.
The first epitaxial structure can comprise a set of MESFET epitaxial layers.
The MESFET layer can comprise an undoped spacer layer and a doped channel layer.
The spacer layer and channel layer can be GaAs layers.
Alternatively, the first epitaxial structure comprises a set of pHEMT layers.
The pHEMT layers can comprise a barrier layer, a channel layer and a Schottky barrier layer.
The barrier layer can be GaAs. The barrier layer can be AlGaAs. The barrier layer can be AlInAs or InGaP.
The Schottky barrier layer can be AlGaAs or InGaP. The Schottky barrier layer can be AlInAs.
The channel layer can be InGaAs.
The second epitaxial layer can comprise a sub-collector layer, a collector layer, a base layer and an emitter layer.
The base layer can comprise a GaAs layer. The base layer can further comprise an AIInP cover layer on the GaAs layer.
The collector layer can comprise a GaAs layer.
The sub-collector layer can comprise a GaAs layer.
In a further aspect of the invention there is provided a BiFET comprising a multilayer semiconductor structure divided into HBT and FET portions comprising
a first epitaxial structure shared by the HBT and FET portions, the epitaxial structure comprising layers suitable for forming the layers of a FET beneath a FET gate;
a first etch stop layer on the first epitaxial structure shared by the HBT and FET portions;
a cap layer on the first etch stop layer shared by the HBT and FET portions;
the FET portion comprising an aperture extending through the cap layer and first etch stop layer to the first epitaxial structure;
a second etch stop layer on the HBT portion of the cap layer; and
a second epitaxial structure on the second etch stop layer, the second epitaxial structure comprising layers suitable for forming a portion of a HBT
In a further aspect of the invention there is provided a multilayer semiconductor substrate for manufacture of a combined FET and HBT, the substrate comprising
a first epitaxial structure comprising layers suitable for forming the layers of a FET beneath a FET gate; an etch stop layer on the first epitaxial structure;
a cap layer on the first etch stop layer;
a second etch stop layer on the cap layer; and
»
a second epitaxial structure on the second etch stop layer, the second epitaxial structure comprising layers suitable for forming a portion of a HBT.
The first etch stop layer can be AlInP.
The second etch stop layer can be AlInP.
Preferably, the composition of the AlInP layer is AlxIni.xP, wherein x is in the range 0.05 to 0.95, preferably in the range 0.4 to 0.6, more preferably 0.5.
Preferably, the first epitaxial layer comprises a buffer layer, preferably an AlGaAs or GaAs buffer layer.
The first epitaxial structure can comprise a set of MESFET epitaxial layers.
The set of MESFET layers can comprise an undoped spacer layer and a doped channel layer.
The spacer layer and channel layer can be GaAs layers.
Alternatively, the first epitaxial structure comprises a set of pHEMT layers.
The pHEMT layers can comprise a barrier layer, a channel layer and a Schottky barrier layer. The barrier layer can be GaAs or AlGaAs. The barrier layer can be AlInAs or InGaP.
The channel layer can be InGaAs.
The Schottky barrier layer can be AlGaAs or InGaP. The Schottky barrier layer can be AlInAs.
The cap layer can be GaAs.
Preferably, the second epitaxial structure comprises a sub-collector layer, a collector layer, a base layer and an emitter layer.
The base layer can comprise a GaAs layer.
The collector layer can comprise a GaAs layer.
The sub-collector layer can comprise a GaAs layer.
The present invention will now be described by way of example only, and not in any limitative sense with reference to the accompanying drawings in which
Figure 1 shows a BiFET according to the invention in cross section; and
Figure 2 shows a multilayer semiconductor substrate according to the invention in cross section.
Shown in figure 1 is a BiFET 1 according to the invention in cross section. The BiFET 1 comprises a multilayer semiconductor structure divided into HBT and FET portions 2,3. The multilayer semiconductor structure comprises a first epitaxial structure 4 shared by the FET and HBT portions 2,3. The first epitaxial structure 4 comprises layers suitable for forming layers of a FET beneath a FET gate 5. In particular, the first epitaxial structure 4 comprises a buffer layer 6. The buffer layer 6 is typically GaAs or AlGaAs. Arranged on the buffer layer 6 are a set of pHEMT layers 7. The pHEMT layers 7 comprise a barrier layer 8. This is typically GaAs or AlGaAs. The barrier layer 8 could also be InAlAs or InGaP. Above the barrier layer 8 is a Schottky barrier layer 9. This is typically AlGaAs or InGaP. A further alternative is AlInAs. Sandwiched between the barrier layer 8 and Schottky barrier layer 9 is a channel layer 10 typically an InGaAs layer. At least one of the barrier layer 8 and the Schottky layer 9 comprises at least one silicon layer 11 which act as electron donor layers for the channel layer 10. Arranged on the Schottky barrier layer 9 is a GaAs cover layer 12. The operation of a pHEMT is well known and will not be described in detail
Arranged on the first epitaxial structure 4 is an AlInP first etch stop layer 13 shared between the FET and HBT regions 2,3. Arranged on the first etch stop layer 13 is a GaAs cap layer 14 shared between HBT and FET regions 2,3.
An aperture 15 extends through the cap layer 14 and first etch stop layer 13 to the first epitaxial structure 4 in the FET region 3. Arranged in the aperture 15 on the first epitaxial structure 4 is the metal gate contact 5. Arranged on the cap layer 14 on either side of the metal gate 5 contact are ohmic metal source and drain contacts 16,17.
Arranged on the cap layer 14 in the HBT region 2 is a second AlInP etch stop layer 18. Arranged on the second etch stop layer 18 is a second epitaxial structure 19 comprising layers suitable for forming a portion of a HBT. In particular the second epitaxial structure 19 comprises a GaAs sub-collector layer 20 arranged on the second etch stop layer 18. Arranged on the sub-collector layer 20 is a GaAs collector layer 21. Arranged on the collector layer 21 is a GaAs base layer 22. The base layer 22 is covered by an optional AlInP cover layer 23 to reduce recombination current in the HBT. Arranged on the cover layer 23 is a GaAs emitter layer 24. Finally, on the emitter layer 24 is an InGaAs contact layer 25. Arranged on the sub-collector layer 20 is an ohmic metal collector contact 26. Arranged on the cover layer 23 is a metal base contact 27. Finally, arranged on the contact layer 25 is a metal emitter contact 28. The operation of a HBT is known and will not be described in detail.
The FET portion 3 and the HBT portion 2 are electrically isolated from each other by an isolation portion 29 formed by implant isolation of a section through the multilayer semiconductor structure.
The BiFET 1 of the invention has separate sub-collector and cap layers 20,14 separated by an etch stop layer 18. Accordingly, in contrast to known BiFETs, the BiFET 1 of the invention does not suffer from thermal runaway.
The etch stop layers 13,18 are AlInP. More Particularly, the composition of the etch stop layers is AlxIn1-XP wherein x is in the range 0.05 to 0.95, preferably 0.4 to 0.6, more preferably 0.5.
In an alterative aspect of the invention (not shown) the first epitaxial structure 4 comprises a set of MESFET layers. The MESFET layers comprise an undoped GaAs spacer layer and a doped GaAs channel layer. Again, the operation of the MESFET is well known and will not be described in detail.
Shown in figure 2 is a multilayer semiconductor substrate 30 according to the invention. The substrate 30 comprises a first epitaxial structure 4 comprising layers suitable for forming the layers of a FET beneath a FET gate. The first epitaxial structure 4 has been described in detail with reference to figure 1.
Arranged on the first epitaxial structure 4 is a first AlInP etch stop layer 12. Arranged on the first etch stop layer 12 is a GaAs cap layer 14. Arranged on the cap layer 14 is a second AlInP etch stop layer 18. Finally, arranged on the second etch stop layer 18 is a second epitaxial structure 19 comprising a sub-collector, collector, base and emitter layers (not shown). The second epitaxial structure 19 has been described in detail with reference to figure 1.
The multilayer semiconductor substrate 30 according to the invention can be used to manufacture a BiFET similar to that of figure 1 although lacking the optional cover layer 23 and contact layer 25. In further embodiments of the invention (not shown), the multilayer semiconductor substrate 30 further comprises one or both of these optional layers.
The method of manufacture of a BiFET 1 according to the invention from a multilayer semiconductor substrate 30 as shown in figure 2 would be a relatively straightforward matter for one skilled in the art of device fabrication and will not be described in detail. An important feature of a preferred embodiment of the multilayer semiconductor substrate 30 of the current invention is that the etch stop layers 12,18 comprise both Aluminium and Phosphorous (preferably AlInP). This enables etching by both wet and dry routes. This enables the manufacture of a BiFET 1 having either vertical or shaped structures so allowing for greater flexibility in the design of the BiFET 1.
The above description includes references to layers comprising three components, including AlInP, AlGaAs, AlInAs, InGaP and InGaAs. More generally, these may be written as AxBi.xC. With the exception of AlInP specific compositional ranges of x have not been specified. Suitable ranges for x are well known to one skilled in the art of device manufacture and are defined by the desired device characteristics and also by the requirement to keep the difference in lattice spacing between adjacent layers within acceptable ranges to reduce device stress. As a specific example, x is typically in the range 0.05 to 0.95, more preferably 0.4 to 0.6, more preferably 0.5.

Claims

1. A multilayer semiconductor structure divided into HBT and FET portions comprising
a first epitaxial structure shared by the HBT and FET portions, the epitaxial structure comprising layers suitable for forming the layers of a FET beneath a FET gate;
a first etch stop layer on the first epitaxial structure shared by the HBT and FET portions;
a cap layer on the first etch stop layer shared by the HBT and FET portions;
the FET portion comprising an aperture extending through the cap layer and first etch stop layer to the first epitaxial structure;
a second etch stop layer on the HBT portion of the cap layer; and
a second epitaxial structure on the second etch stop layer, the second epitaxial structure comprising layers suitable for forming a portion of a HBT.
2. A multilayer semiconductor structure as claimed in claim 1, further comprising a metal gate contact on the first epitaxial structure within the aperture.
3. A multilayer semiconductor structure as claimed in either of claims 1 or 2, further comprising an ohmic metal source contact and an ohmic metal drain contact arranged on the cap layer on opposite sides of the aperture.
4. A multilayer semiconductor structure as claimed in any one of claims 1 to 3, wherein the first etch stop layer is AIInP.
5. A multilayer semiconductor structure as claimed in any one of claims 1 to 4, wherein the second etch stop layer is AlInP.
6. A multilayer semiconductor structure as claimed in either of claims 4 or 5, wherein the composition of the AlInP layer is AlxIni.xP, wherein x is in the range 0.05 to 0.95, more preferably 0.4 to 0.6, more preferably 0.5.
7. A multilayer semiconductor structure as claimed in any one of claims 1 to 6, wherein the cap layer is GaAs.
8. A multilayer semiconductor structure as claimed in any one of claims 1 to 7, wherein the first epitaxial structure comprises a buffer layer, preferably an AlGaAs or GaAs buffer layer.
9. A multilayer semiconductor structure as claimed in any one of claims 1 to 8, wherein the first epitaxial structure comprises a set of MESFET epitaxial layers.
10. A multilayer semiconductor structure as claimed in claim 9, wherein the MESFET layer comprises an undoped spacer layer and a doped channel layer.
11. A multilayer semiconductor structure as claimed in claim 10, wherein the spacer layer and channel layer are GaAs layers.
12. A multilayer semiconductor structure as claimed in any one of claims 1 to 8, wherein the first epitaxial structure comprises a set of pHEMT layers.
13. A multilayer semiconductor structure as claimed in claim 12, wherein the pHEMT layers comprise a barrier layer, a channel layer and a Schottky barrier layer.
14. A multilayer semiconductor structure as claimed in claim 13, wherein the barrier layer is GaAs or AlGaAs.
15. A multilayer semiconductor structure as claimed in claim 13, wherein the barrier layer is AlGaAs.
16. A multilayer semiconductor structure as claimed in claim 13, wherein the barrier layer is AIInAs or InGaP.
17. A multilayer semiconductor structure as claimed in any one of claims 13 to 16, wherein the Schottky barrier layer is AlGaAs or InGaP.
18. A multilayer semiconductor structure as claimed in any one of claims 13 to 16, wherein the Schottky barrier layer is AlInAs.
19. A multilayer semiconductor structure as claimed in any one of claims 13 to 18, wherein the channel layer is InGaAs.
20. A multilayer semiconductor structure as claimed in any one of claims 1 to 19, wherein the second epitaxial layer comprises a sub-collector layer, a collector layer, a base layer and an emitter layer.
21. A multilayer semiconductor structure as claimed in claim 20, wherein the base layer comprises a GaAs layer.
22. A multilayer semiconductor structure as claimed in claim 21, wherein the base layer further comprises a AlInP cover layer on the GaAs layer.
23. A multilayer semiconductor structure as claimed in claim 20, wherein the collector layer comprises a GaAs layer.
24. A multilayer semiconductor structure as claimed in claim 20, wherein the sub- collector layer comprises a GaAs layer.
25. A BiFET comprising a semiconductor structure as claimed in any one of claims 1 to 24.
26. A multilayer semiconductor substrate for manufacture of a combined FET and HBT, the substrate comprising
a first epitaxial structure comprising layers suitable for forming the layers of a FET beneath a FET gate;
an etch stop layer on the first epitaxial structure;
a cap layer on the first etch stop layer;
a second etch stop layer on the cap layer; and
a second epitaxial structure on the second etch stop layer, the second epitaxial structure comprising layers suitable for forming a portion of a HBT.
27. A multilayer semiconductor substrate as claimed in claim 26, wherein the first etch stop layer is AlInP.
28. A multilayer semiconductor substrate as claimed in either of claims 26 or 27, wherein the second etch stop layer is AlInP.
29. A multilayer semiconductor substrate as claimed in either of claims 27 or 28, wherein the composition of the AlInP layer is AlxIn1-XP, wherein x is in the range
. 0.05 to 0.95, preferably in the range 0.4 to 0.6, more preferably 0.5.
30. A multilayer semiconductor substrate as claimed in any one of claims 26 to 29, wherein the first epitaxial layer comprises a buffer layer, preferably an AlGaAs or GaAs buffer layer.
31. A multilayer semiconductor substrate as claimed in any one of claims 26 to 30, wherein the first epitaxial structure comprises a set of MESFET epitaxial layers.
32. A multilayer semiconductor substrate as claimed in claim 31, wherein the set of MESFET layers comprises an undoped spacer layer and a doped channel layer.
33. A multilayer semiconductor substrate as claimed in claim 32, wherein the spacer layer and channel layer are GaAs layers.
34. A multilayer semiconductor substrate as claimed in any one of claims 26 to 30, wherein the first epitaxial structure comprises a set of pHEMT layers.
35. A multilayer semiconductor substrate as claimed in claim 34, wherein the pHEMT layers comprise a barrier layer, a channel layer and a Schottky barrier layer.
36. A multilayer semiconductor substrate as claimed in claim 35, wherein the barrier layer is GaAs
37. A multilayer semiconductor substrate as claimed in claim 35, wherein the barrier layer is AlGaAs.
38. A multilayer semiconductor wafer as claimed in claim 35, wherein the barrier layer is AlInAs or InGaP.
39. A multilayer semiconductor substrate as claimed in any one of claims 35 to 38, wherein the channel layer is InGaAs.
40. A multilayer semiconductor substrate as claimed in any one of claims 35 to 39, wherein the Schottky barrier layer is AlGaAs or InGaP.
41. A multilayer semiconductor substrate as claimed in any one of claims 35 to 39, wherein the Schottky barrier layer is AlInAs.
42. A multilayer semiconductor substrate as claimed in any one of claims 26 to 41, wherein the cap layer is GaAs.
43. A multilayer semiconductor substrate as claimed in any one of claims 26 to 42, wherein the second epitaxial structure comprises a sub-collector layer, a collector layer, a base layer and an emitter layer.
44. A multilayer semiconductor substrate as claimed in claim 43, wherein the base layer comprises a GaAs layer.
45. A multilayer semiconductor substrate as claimed in either of claims 43 or 44, wherein the collector layer comprises a GaAs layer.
46. A multilayer semiconductor substrate as claimed in any one of claims 43 to 45, wherein the sub-collector layer comprises a GaAs layer.
47. A multilayer semiconductor structure substantially as hereinbefore described.
48. A multilayer semiconductor substrate substantially as hereinbefore described.
49. A BiFET substantially as hereinbefore described.
PCT/GB2008/003216 2007-09-25 2008-09-23 A multilayer semiconductor structure, a bifet includin such a structure, and a multilayer semiconductor substrate Ceased WO2009040509A1 (en)

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