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WO2008139898A1 - 半導体装置の製造方法および半導体装置 - Google Patents

半導体装置の製造方法および半導体装置 Download PDF

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Publication number
WO2008139898A1
WO2008139898A1 PCT/JP2008/058099 JP2008058099W WO2008139898A1 WO 2008139898 A1 WO2008139898 A1 WO 2008139898A1 JP 2008058099 W JP2008058099 W JP 2008058099W WO 2008139898 A1 WO2008139898 A1 WO 2008139898A1
Authority
WO
WIPO (PCT)
Prior art keywords
semiconductor device
electrode
exposed
oxide film
arranging
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2008/058099
Other languages
English (en)
French (fr)
Inventor
Masaru Takaishi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Rohm Co Ltd
Original Assignee
Rohm Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Rohm Co Ltd filed Critical Rohm Co Ltd
Priority to JP2009514085A priority Critical patent/JP5502468B2/ja
Publication of WO2008139898A1 publication Critical patent/WO2008139898A1/ja
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/66—Vertical DMOS [VDMOS] FETs
    • H10D30/668—Vertical DMOS [VDMOS] FETs having trench gate electrodes, e.g. UMOS transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/028—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs
    • H10D30/0291—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs
    • H10D30/0293—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs using formation of insulating sidewall spacers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/028—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs
    • H10D30/0291—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs
    • H10D30/0297—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs using recessing of the gate electrodes, e.g. to form trench gate electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/66—Vertical DMOS [VDMOS] FETs
    • H10D30/665—Vertical DMOS [VDMOS] FETs having edge termination structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/111—Field plates
    • H10D64/117—Recessed field plates, e.g. trench field plates or buried field plates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/517—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the conducting layers
    • H10D64/519—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the conducting layers characterised by their top-view geometrical layouts

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

　製造プロセスが煩雑になるのを抑制することが可能な半導体装置の製造方法を提供する。この半導体装置（１）の製造方法は、トレンチ（２ａ）の幅が、トレンチ（２ｂ）の幅より大きくなるように、トレンチ（２ａおよび２ｂ）を形成する工程と、電極（３および４）を配置する工程と、酸化膜（１４（１４ｂ））を配置する工程と、電極（３）の上面が露出するとともに、電極（４）の上面が露出しないように、酸化膜（１４）を除去する工程と、酸化膜（１５）を配置する工程と、電極（３）の上面が露出するとともに、シリコン基板（２）と電極（４）との上面が露出しないように、酸化膜（１５）を除去する工程と、電極（３）上に配線層（６）を配置する工程とを備える。
PCT/JP2008/058099 2007-04-27 2008-04-25 半導体装置の製造方法および半導体装置 Ceased WO2008139898A1 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2009514085A JP5502468B2 (ja) 2007-04-27 2008-04-25 半導体装置の製造方法および半導体装置

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2007-118932 2007-04-27
JP2007118932 2007-04-27

Publications (1)

Publication Number Publication Date
WO2008139898A1 true WO2008139898A1 (ja) 2008-11-20

Family

ID=40002114

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2008/058099 Ceased WO2008139898A1 (ja) 2007-04-27 2008-04-25 半導体装置の製造方法および半導体装置

Country Status (3)

Country Link
JP (1) JP5502468B2 (ja)
TW (1) TW200849472A (ja)
WO (1) WO2008139898A1 (ja)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2018170456A (ja) * 2017-03-30 2018-11-01 エイブリック株式会社 半導体装置及びその製造方法
JP2019506010A (ja) * 2016-05-31 2019-02-28 無錫華潤上華科技有限公司Ｃｓｍｃ Ｔｅｃｈｎｏｌｏｇｉｅｓ Ｆａｂ２ Ｃｏ．， Ｌｔｄ． トレンチゲートのリードアウト構造およびそれを製造する方法

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9123559B2 (en) * 2013-05-31 2015-09-01 Infineon Technologies Ag Method for producing a semiconductor component

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002270841A (ja) * 2001-03-13 2002-09-20 Denso Corp 半導体装置及びその製造方法
JP2002373988A (ja) * 2001-06-14 2002-12-26 Rohm Co Ltd 半導体装置およびその製法
JP2004179277A (ja) * 2002-11-26 2004-06-24 New Japan Radio Co Ltd 半導体装置の製造方法
JP2004207476A (ja) * 2002-12-25 2004-07-22 Mitsubishi Electric Corp 電力用半導体装置及び電力用半導体装置の製造方法
JP2004311547A (ja) * 2003-04-03 2004-11-04 Seiko Instruments Inc 縦形ｍｏｓトランジスタの製造方法
JP2005191487A (ja) * 2003-12-26 2005-07-14 Seiko Instruments Inc 半導体装置およびその製造法
JP2006100317A (ja) * 2004-09-28 2006-04-13 Nec Electronics Corp 半導体装置
JP2006100404A (ja) * 2004-09-28 2006-04-13 Nec Electronics Corp 半導体装置及びその製造方法

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6449242A (en) * 1987-08-20 1989-02-23 Matsushita Electronics Corp Manufacture of semiconductor device
JPH0349228A (ja) * 1989-07-18 1991-03-04 Fuji Electric Co Ltd 半導体集積回路の製造方法
JP2001085520A (ja) * 1999-09-09 2001-03-30 Seiko Epson Corp コンタクトプラグ構造及びその製造方法

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002270841A (ja) * 2001-03-13 2002-09-20 Denso Corp 半導体装置及びその製造方法
JP2002373988A (ja) * 2001-06-14 2002-12-26 Rohm Co Ltd 半導体装置およびその製法
JP2004179277A (ja) * 2002-11-26 2004-06-24 New Japan Radio Co Ltd 半導体装置の製造方法
JP2004207476A (ja) * 2002-12-25 2004-07-22 Mitsubishi Electric Corp 電力用半導体装置及び電力用半導体装置の製造方法
JP2004311547A (ja) * 2003-04-03 2004-11-04 Seiko Instruments Inc 縦形ｍｏｓトランジスタの製造方法
JP2005191487A (ja) * 2003-12-26 2005-07-14 Seiko Instruments Inc 半導体装置およびその製造法
JP2006100317A (ja) * 2004-09-28 2006-04-13 Nec Electronics Corp 半導体装置
JP2006100404A (ja) * 2004-09-28 2006-04-13 Nec Electronics Corp 半導体装置及びその製造方法

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2019506010A (ja) * 2016-05-31 2019-02-28 無錫華潤上華科技有限公司Ｃｓｍｃ Ｔｅｃｈｎｏｌｏｇｉｅｓ Ｆａｂ２ Ｃｏ．， Ｌｔｄ． トレンチゲートのリードアウト構造およびそれを製造する方法
JP2018170456A (ja) * 2017-03-30 2018-11-01 エイブリック株式会社 半導体装置及びその製造方法

Also Published As

Publication number Publication date
JPWO2008139898A1 (ja) 2011-01-27
JP5502468B2 (ja) 2014-05-28
TW200849472A (en) 2008-12-16

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