WO2008139498A1

WO2008139498A1 - A method of testing electronic circuits and related circuit

Info

Publication number: WO2008139498A1
Application number: PCT/IT2007/000341
Authority: WO
Inventors: Antonio Callegaro; Andreas Huber
Original assignee: Osram GmbH; Osram SpA
Current assignee: Osram GmbH; Osram SpA
Priority date: 2007-05-10
Filing date: 2007-05-10
Publication date: 2008-11-20
Anticipated expiration: 2009-11-10

Abstract

Testing an electronic circuit (EC) includes the steps of applying to the electronic circuit (EC) stimulation signals, and collecting from the electronic circuit (EC) test signals resulting from the application of the stimulation signals. At least one processing unit (PUl) such as a microcontroller is included in the electronic circuit (EC) - i.e. by embedding it into the circuit - in order to apply the stimulation signals and collect the resulting signals, and possibly process them to yield a test outcome.

Description

"A method of testing electronic circuits and related circuit"

* * * Field of the invention

The invention relates to techniques for testing electronic circuits.

Description of the related art

Automated testing of electronic circuits, e.g. electronic circuits mounted on a board, is usually performed by resorting to a mix of different test capabilities, namely:

- optical inspection,

- in-circuit parametric or functional testing, and

- functional (i.e. operational) testing with real and simulated loads. In this context, a conventional approach is to employ processing units such as microcontrollers programmed to generate "stimulation" signals that are applied to the^' circuit under test. The results of stimulation (namely the signals generated by the circuit under test as a result of the stimulation signals applied to it) are collected and processed with a view to check correct operation thereof.

Figure 1 annexed herewith is generally representative of such an arrangement where a processing unit PU (such as a microcontroller) is used together with test equipment TE for testing an electronic circuit (generally designated EC) such as a printed circuit board having various components mounted thereon. To that end, the processing unit PU (hereinafter a microcontroller will be mostly referred to for the sake of simplicity) is connected to the circuit EC via a (generally huge) quantity of connecting wires/lines W in order to apply the stimulation signals and collect the resulting signals, which are then processed by the test equipment TE.

In general terms, the test process is devised as a compromise between the time required to perform it and the expected performance of the test process, namely the completeness and reliability of the results of the test technique. It will thus be appreciated that setting up an arrangement as shown in figure 1 may be time consuming, with the additional risk that some of the connections W- may turn out to be faulty or erroneous .

Object and summary of the invention

In view of the foregoing, the need exists for solutions that may simplify the test procedures as described in the foregoing, especially as regards reducing the time involved in performing the test, while maintaining (and possibly improving) the quality of testing in terms of reliability and general performance . The object of the invention is to provide such a solution.

According to the present invention, that object is achieved by means of a method having the features set forth in the claims that follow. The invention also relates to a corresponding circuit.

The claims are an integral part of the disclosure of the invention provided herein.

The solution described herein can be applied to any electronic circuit including at least one processing unit. Exemplary of such circuits are electronic boards with embedded microcontrollers.

In a preferred embodiment of the arrangement described herein, test time consumption is reduced, while at the same time improving reliability and performance quality by using one or more processing units (typically microcontrollers) available in the circuit under test to perform a complete or partial self-test procedure. In an embodiment, proper firmware is provided in the "on-board" microcontroller or microcontrollers in order to apply stimulation signals to the circuit and detect the results produced deriving from such stimulation signals being applied. The "onboard" microcontroller (s ) is/are able to compare these results (in some instances, external hardware may be required in order to properly close the loop from outputs to inputs) with the test limits stored in the memory. Consequently, the test equipment has just to check the results of the test provided by the board under test to yield the final test outcome. In certain embodiments, however, the functionalities of the onboard microcontroller (s) can be extended to processing the signals resulting from the stimulation applied up to the point of providing a test outcome proper.

Brief description of the annexed drawings

The invention will now be described, by way of example only, with reference to the enclosed figures of drawing, wherein: figure 1 has been already described in the foregoing,

- figure 2 is a block diagram of an exemplary embodiment of the arrangement described herein, and - figure 3 shows an alternative embodiment of the arrangement described herein.

Detailed description of preferred embodiments

In figures 2 and 3 (as in figure 1) the designation EC indicates an electronic circuit under test .

The circuit in question may be any kind of circuit, save for the fact that in the case of figures 2 and 3, the electronic circuit EC includes mounted thereon (typically embedded therein) one or a plurality of processing units PUl, PU2, and so on in the form of e.g. microcontrollers. In the embodiment of figure 2, the microcontroller PUl operates under the control of test equipment TE and includes firmware adapted to implement any test procedure for the circuit EC generally including the steps of applying to the elements in the circuit EC "stimulation" signals and collecting the resulting signals (possibly including "non signals" - i.e. signals missing due to a fault) from the circuit elements due to the stimulation signals being applied. These resulting signals are then processed to derive therefrom a test outcome.

The test procedure in question may be of any type known in the art and does not constitute - per se - the subject matter of this application.

This also applies the possible partitioning of the related functions between the microcontroller PUl and the test equipment TE.

In a presently preferred embodiment, the microcontroller PUl includes firmware configured to implement connecting lines Wl, W2, W3... to the various elements in the circuit EC under test so that the stimulation signals can be delivered to these elements and the signals resulting from such stimulation collected therefrom.

As indicated, in some instances, external hardware (not shown) may be required in order to properly close the loop from outputs to inputs.

Also, the specific criteria for partitioning processing functions between the test equipment TE and the microcontroller PUl are dictated by the specific test procedure implemented.

A significant point in the embodiment of figure 2 lies in that, contrary to the wiring/connections W of figure 1 (which are positively established for performing the test procedure, with the disadvantages already outlined in the foregoing) , the wiring/connections Wl, W2, W3 may be in the form of wiring already provided in the circuit EC (e.g. when the PCB board is manufactured) and do not need to be provided just for testing to be subsequently dispensed with once the testing is completed.

Also, at least part of the wiring Wl, W2, W3 may be simply comprised of wiring already existing in the electronic circuit EC for functional purposes and which is temporarily used for test purposes. The alternative arrangement of figure 3 refers to a situation where the electronic circuit under test, again designated EC, includes at least two processing units such as two microcontrollers PUl, PU2, e.g. in the form of microcontrollers embedded in the circuit EC.

Both microcontrollers PUl, PU2 include respective firmware configured to implement various connecting lines Wl, W2, W3... and Wl', W2' , W3'... to elements in the circuit EC Under these circumstances, the on-board testing procedure may be configured in such a way that the two microcontrollers PUl, PU2 cross-test each other e.g. via (common) lines included in the sets designated W2 and W2' .

For instance, after, or preferably before, being used for testing the other elements in the circuit EC one of the microcontrollers - for instance the microcontroller PUl - is subjected to a pre-test procedure performed by the other microcontroller PU2

(which is in turn tested by means of the microcontroller PUl) .

The self-test method described herein provides a number of significant advantages. In the first place, it allows functional, dynamic testing of electronic circuits EC by reducing to a minimum, and virtually dispensing with, the need of external equipment.

The circuit test time is reduced since complex components can be reliably tested directly via the self-test procedure.

Additionally, the test results can be provided to the test system in different ways (output frequency of voltage, COM port, and so on) , which significantly reduces the complexity/cost of the system.

Finally, the test results can be stored in the memory of the processing unit to allow off-line faulty part analysis and traceability.

Of course, without prejudice to the underlying principle of the invention, the details and embodiments may vary, even significantly, with respect to what has been described by way of example only, without departing from the scope of the invention as defined in the annexed claims.

Claims

1. A method of testing an electronic circuit (EC) including the steps of: - applying to said electronic circuit (EC) stimulation signals, and collecting from said electronic circuit (EC) test signals resulting from the application of said stimulation signals, characterized in that the method includes:

- including in said electronic circuit (EC) at least one processing unit (PUl), and

- performing said steps of applying said stimulation signals and collecting said resulting signals by utilizing said at least one processing unit (PUl, PU2) included in said electronic circuit (EC).

2. The method of claim 1, further including the step of processing said resulting signals to derive therefrom a test outcome by utilizing, for at least part of said processing, said at least one processing unit (PUl, PU2) included in said electronic circuit (EC) .

3. The method of either of claims 1 or 2, including the step of selecting a microcontroller as said at least one processing unit (PUl, PU2).

4. The method of any of the previous claims, wherein said at least one processing unit (PUl, PU2) is embedded in said electronic circuit (EC) .

5. The method of any of the previous claims, including the step of providing at least two said processing units (PUl, PU2) in said electronic circuit (EC) and causing one (PU2 resp. PUl) of the said two processing units to apply stimulation signals to the other (PUl resp. PU2) of said at least two processing units and collecting therefrom the test signals deriving from said stimulation signals being applied.

6. An electronic circuit (EC) including at least one processing unit (PUl, PU2) configured for performing the method of any of claims 1 to 5.