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WO2008120418A1 - 半導体装置およびその製造方法 - Google Patents

半導体装置およびその製造方法 Download PDF

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Publication number
WO2008120418A1
WO2008120418A1 PCT/JP2007/073308 JP2007073308W WO2008120418A1 WO 2008120418 A1 WO2008120418 A1 WO 2008120418A1 JP 2007073308 W JP2007073308 W JP 2007073308W WO 2008120418 A1 WO2008120418 A1 WO 2008120418A1
Authority
WO
WIPO (PCT)
Prior art keywords
electrode
semiconductor device
source
drain
gate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2007/073308
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English (en)
French (fr)
Inventor
Kazutaka Takagi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to EP07832928A priority Critical patent/EP2133909A4/en
Priority to KR1020097008283A priority patent/KR101156779B1/ko
Priority to US12/514,933 priority patent/US8278685B2/en
Publication of WO2008120418A1 publication Critical patent/WO2008120418A1/ja
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/86—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of Schottky-barrier gate FETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/80—FETs having rectifying junction gate electrodes
    • H10D30/87—FETs having Schottky gate electrodes, e.g. metal-semiconductor FETs [MESFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/23—Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
    • H10D64/251—Source or drain electrodes for field-effect devices
    • H10D64/257—Source or drain electrodes for field-effect devices for lateral devices wherein the source or drain electrodes are characterised by top-view geometrical layouts, e.g. interdigitated, semi-circular, annular or L-shaped electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

　接地インダクタンスを低減化した半導体装置およびその製造方法。 　半絶縁性基板１１の第１表面に配置され,複数のフィンガーを有するゲート電極、ソース電極およびドレイン電極と、第１表面とは反対側の第２表面に配置された接地導体２６と、ゲート電極、ソース電極およびドレイン電極ごとに複数のフィンガーをそれぞれ束ねて形成したゲート端子電極１４、ソース端子電極１８およびドレイン端子電極１２と、ゲート電極、ソース電極およびドレイン電極の下部の半絶縁性基板１１上に形成された動作層と、第１表面近傍の小口径ＶＩＡホール３０と第２表面近傍の大口径ＶＩＡホール２０とからなる多段ＶＩＡホールと、多段ＶＩＡホールの内壁面および第２表面に形成され、ソース端子電極１８に対して第２表面側の接地導体から接続された接地電極２３とを備える半導体装置およびその製造方法。
PCT/JP2007/073308 2007-04-02 2007-12-03 半導体装置およびその製造方法 Ceased WO2008120418A1 (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
EP07832928A EP2133909A4 (en) 2007-04-02 2007-12-03 SEMICONDUCTOR ARRANGEMENT AND METHOD FOR THE PRODUCTION THEREOF
KR1020097008283A KR101156779B1 (ko) 2007-04-02 2007-12-03 반도체 장치 및 그 제조 방법
US12/514,933 US8278685B2 (en) 2007-04-02 2007-12-03 Semiconductor device used with high frequency band

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2007096851A JP5100185B2 (ja) 2007-04-02 2007-04-02 半導体装置およびその製造方法
JP2007-096851 2007-04-02

Publications (1)

Publication Number Publication Date
WO2008120418A1 true WO2008120418A1 (ja) 2008-10-09

Family

ID=39808006

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2007/073308 Ceased WO2008120418A1 (ja) 2007-04-02 2007-12-03 半導体装置およびその製造方法

Country Status (6)

Country Link
US (1) US8278685B2 (ja)
EP (1) EP2133909A4 (ja)
JP (1) JP5100185B2 (ja)
KR (1) KR101156779B1 (ja)
TW (1) TWI385788B (ja)
WO (1) WO2008120418A1 (ja)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2010068872A1 (en) * 2008-12-12 2010-06-17 Qualcomm Incorporated Via first plus via last technique for ic interconnect
CN106847679A (zh) * 2015-10-09 2017-06-13 英飞凌科技股份有限公司 通过去除非晶化的部分来制造碳化硅半导体器件的方法

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US8143654B1 (en) * 2008-01-16 2012-03-27 Triquint Semiconductor, Inc. Monolithic microwave integrated circuit with diamond layer
US20110018013A1 (en) * 2009-07-21 2011-01-27 Koninklijke Philips Electronics N.V. Thin-film flip-chip series connected leds
JP5631607B2 (ja) * 2009-08-21 2014-11-26 株式会社東芝 マルチチップモジュール構造を有する高周波回路
TWI515930B (zh) * 2010-05-31 2016-01-01 精材科技股份有限公司 發光二極體次基板、發光二極體封裝及其製造方法
JP5649357B2 (ja) * 2010-07-30 2015-01-07 住友電工デバイス・イノベーション株式会社 半導体装置及び製造方法
JP5760394B2 (ja) * 2010-11-05 2015-08-12 三菱電機株式会社 ビアホールの製造方法およびビアホールを有する半導体素子の製造方法
US8853857B2 (en) 2011-05-05 2014-10-07 International Business Machines Corporation 3-D integration using multi stage vias
KR101813180B1 (ko) * 2011-06-28 2017-12-29 삼성전자주식회사 고 전자 이동도 트랜지스터 및 그 제조방법
KR101649060B1 (ko) * 2012-03-12 2016-08-17 미쓰비시덴키 가부시키가이샤 태양전지 셀의 제조 방법
KR101988893B1 (ko) 2012-12-12 2019-09-30 한국전자통신연구원 반도체 소자 및 이를 제조하는 방법
US10672877B2 (en) * 2018-02-06 2020-06-02 Integrated Device Technology, Inc. Method of boosting RON*COFF performance
US10629526B1 (en) 2018-10-11 2020-04-21 Nxp Usa, Inc. Transistor with non-circular via connections in two orientations
JP2021052025A (ja) * 2019-09-20 2021-04-01 富士通株式会社 半導体装置、半導体装置の製造方法及び電子装置
US11670605B2 (en) 2020-04-03 2023-06-06 Wolfspeed, Inc. RF amplifier devices including interconnect structures and methods of manufacturing
US12500562B2 (en) 2020-04-03 2025-12-16 Macom Technology Solutions Holdings, Inc. RF amplifier devices and methods of manufacturing including modularized designs with flip chip interconnections
US11837457B2 (en) * 2020-09-11 2023-12-05 Wolfspeed, Inc. Packaging for RF transistor amplifiers
US12166003B2 (en) 2020-04-03 2024-12-10 Macom Technology Solutions Holdings, Inc. RF amplifier devices including top side contacts and methods of manufacturing
US11356070B2 (en) 2020-06-01 2022-06-07 Wolfspeed, Inc. RF amplifiers having shielded transmission line structures
WO2022176051A1 (ja) * 2021-02-17 2022-08-25 三菱電機株式会社 窒化物半導体装置および窒化物半導体装置の製造方法
CN115248364A (zh) 2021-04-26 2022-10-28 财团法人工业技术研究院 高频元件测试装置及其测试方法
EP4394890A4 (en) * 2021-09-15 2024-10-16 Huawei Technologies Co., Ltd. Semiconductor device and preparation method therefor, and power amplification circuit and electronic device

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JPS63278368A (ja) * 1987-05-11 1988-11-16 Nec Corp 半導体基板のバイアホ−ル形成方法
JPH02307219A (ja) * 1989-05-23 1990-12-20 Oki Electric Ind Co Ltd 半導体素子の電極の製造方法
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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2010068872A1 (en) * 2008-12-12 2010-06-17 Qualcomm Incorporated Via first plus via last technique for ic interconnect
US7939926B2 (en) 2008-12-12 2011-05-10 Qualcomm Incorporated Via first plus via last technique for IC interconnects
US7985620B2 (en) 2008-12-12 2011-07-26 Qualcomm Incorporated Method of fabricating via first plus via last IC interconnect
US8076768B2 (en) 2008-12-12 2011-12-13 Qualcomm Incorporated IC interconnect
CN106847679A (zh) * 2015-10-09 2017-06-13 英飞凌科技股份有限公司 通过去除非晶化的部分来制造碳化硅半导体器件的方法

Also Published As

Publication number Publication date
EP2133909A1 (en) 2009-12-16
TW200841455A (en) 2008-10-16
US20100059791A1 (en) 2010-03-11
KR101156779B1 (ko) 2012-06-18
JP2008258281A (ja) 2008-10-23
JP5100185B2 (ja) 2012-12-19
TWI385788B (zh) 2013-02-11
EP2133909A4 (en) 2011-03-16
KR20090084825A (ko) 2009-08-05
US8278685B2 (en) 2012-10-02

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