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WO2008120393A1 - 情報処理装置、情報処理装置設計方法、情報処理装置設計プログラム - Google Patents

情報処理装置、情報処理装置設計方法、情報処理装置設計プログラム Download PDF

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Publication number
WO2008120393A1
WO2008120393A1 PCT/JP2007/056983 JP2007056983W WO2008120393A1 WO 2008120393 A1 WO2008120393 A1 WO 2008120393A1 JP 2007056983 W JP2007056983 W JP 2007056983W WO 2008120393 A1 WO2008120393 A1 WO 2008120393A1
Authority
WO
WIPO (PCT)
Prior art keywords
information processor
designing
program
designing method
processor designing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2007/056983
Other languages
English (en)
French (fr)
Inventor
Keisuke Muraya
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP2009507381A priority Critical patent/JP4894915B2/ja
Priority to PCT/JP2007/056983 priority patent/WO2008120393A1/ja
Publication of WO2008120393A1 publication Critical patent/WO2008120393A1/ja
Priority to US12/562,738 priority patent/US8799684B2/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/211—Design considerations for internal polarisation
    • H10D89/213—Design considerations for internal polarisation in field-effect devices
    • H10D89/215—Design considerations for internal polarisation in field-effect devices comprising arrangements for charge pumping or biasing substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H10D84/85—Complementary IGFETs, e.g. CMOS

Landscapes

  • Semiconductor Integrated Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)

Abstract

　それぞれが複数のトランジスタを有する複数のプロセサコアと、プロセサコア数に基づいて設定された基板バイアス電圧をトランジスタのそれぞれに与える少なくとも１つの基板バイアス回路とを備えた。
PCT/JP2007/056983 2007-03-29 2007-03-29 情報処理装置、情報処理装置設計方法、情報処理装置設計プログラム Ceased WO2008120393A1 (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2009507381A JP4894915B2 (ja) 2007-03-29 2007-03-29 情報処理装置設計方法、情報処理装置設計プログラム
PCT/JP2007/056983 WO2008120393A1 (ja) 2007-03-29 2007-03-29 情報処理装置、情報処理装置設計方法、情報処理装置設計プログラム
US12/562,738 US8799684B2 (en) 2007-03-29 2009-09-18 Apparatus, method and process to determine a threshold voltage so that leakage power of a plurality of transistors is inversely proportional to a plurality of processor cores

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2007/056983 WO2008120393A1 (ja) 2007-03-29 2007-03-29 情報処理装置、情報処理装置設計方法、情報処理装置設計プログラム

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US12/562,738 Continuation US8799684B2 (en) 2007-03-29 2009-09-18 Apparatus, method and process to determine a threshold voltage so that leakage power of a plurality of transistors is inversely proportional to a plurality of processor cores

Publications (1)

Publication Number Publication Date
WO2008120393A1 true WO2008120393A1 (ja) 2008-10-09

Family

ID=39807984

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2007/056983 Ceased WO2008120393A1 (ja) 2007-03-29 2007-03-29 情報処理装置、情報処理装置設計方法、情報処理装置設計プログラム

Country Status (3)

Country Link
US (1) US8799684B2 (ja)
JP (1) JP4894915B2 (ja)
WO (1) WO2008120393A1 (ja)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2021523491A (ja) * 2018-05-15 2021-09-02 パルテック・クラスター・コンペテンス・センター・ゲゼルシャフト・ミット・ベシュレンクテル・ハフツングＰａｒｔｅｃ Ｃｌｕｓｔｅｒ Ｃｏｍｐｅｔｅｎｃｅ Ｃｅｎｔｅｒ Ｇｍｂｈ 効率的な並列計算のための装置および方法

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9021284B2 (en) * 2011-09-08 2015-04-28 Infineon Technologies Ag Standby operation with additional micro-controller
CN109948173A (zh) * 2019-01-04 2019-06-28 上海亿算科技有限公司 一种芯片系统
US11797410B2 (en) * 2021-11-15 2023-10-24 Advanced Micro Devices, Inc. Chiplet-level performance information for configuring chiplets in a processor

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001051957A (ja) * 1999-08-04 2001-02-23 Hitachi Ltd オンチップマルチプロセッサ

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003209616A (ja) 2002-01-15 2003-07-25 Fujitsu Ltd 半導体装置および携帯端末装置
JP4549652B2 (ja) * 2003-10-27 2010-09-22 パナソニック株式会社 プロセッサシステム
JP2005166698A (ja) * 2003-11-28 2005-06-23 Matsushita Electric Ind Co Ltd 半導体集積回路
US7216310B2 (en) * 2004-01-07 2007-05-08 Texas Instruments Incorporated Design method and system for optimum performance in integrated circuits that use power management
JP4088645B2 (ja) 2005-12-22 2008-05-21 松下電器産業株式会社 Ｌｓｉシステム設計方法
US8171323B2 (en) * 2008-07-01 2012-05-01 Broadcom Corporation Integrated circuit with modular dynamic power optimization architecture

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001051957A (ja) * 1999-08-04 2001-02-23 Hitachi Ltd オンチップマルチプロセッサ

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2021523491A (ja) * 2018-05-15 2021-09-02 パルテック・クラスター・コンペテンス・センター・ゲゼルシャフト・ミット・ベシュレンクテル・ハフツングＰａｒｔｅｃ Ｃｌｕｓｔｅｒ Ｃｏｍｐｅｔｅｎｃｅ Ｃｅｎｔｅｒ Ｇｍｂｈ 効率的な並列計算のための装置および方法
JP7561033B2 (ja) 2018-05-15 2024-10-03 パルテック・アーゲー 効率的な並列計算のための装置および方法

Also Published As

Publication number Publication date
JP4894915B2 (ja) 2012-03-14
JPWO2008120393A1 (ja) 2010-07-15
US20100011189A1 (en) 2010-01-14
US8799684B2 (en) 2014-08-05

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