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WO2008101232A1 - Dispositif optoélectronique à longueur d'onde multiple comprenant un super-réseau et procédés associés - Google Patents

Dispositif optoélectronique à longueur d'onde multiple comprenant un super-réseau et procédés associés Download PDF

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Publication number
WO2008101232A1
WO2008101232A1 PCT/US2008/054210 US2008054210W WO2008101232A1 WO 2008101232 A1 WO2008101232 A1 WO 2008101232A1 US 2008054210 W US2008054210 W US 2008054210W WO 2008101232 A1 WO2008101232 A1 WO 2008101232A1
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Prior art keywords
semiconductor
electronic device
superlattice
opto
active optical
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PCT/US2008/054210
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English (en)
Inventor
Robert J. Mears
Robert J. Stephenson
Marek Hytha
Ilija Dukovski
Jean Augustin Chan Sow Fook Yiptong
Samed Halilov
Xiangyang Huang
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Atomera Inc
Original Assignee
Mears Technologies Inc
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Priority claimed from US11/675,846 external-priority patent/US7863066B2/en
Priority claimed from US11/675,833 external-priority patent/US7880161B2/en
Application filed by Mears Technologies Inc filed Critical Mears Technologies Inc
Publication of WO2008101232A1 publication Critical patent/WO2008101232A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F77/00—Constructional details of devices covered by this subclass
    • H10F77/10—Semiconductor bodies
    • H10F77/14—Shape of semiconductor bodies; Shapes, relative sizes or dispositions of semiconductor regions within semiconductor bodies
    • H10F77/146—Superlattices; Multiple quantum well structures
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y20/00—Nanooptics, e.g. quantum optics or photonic crystals
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
    • H01L25/03—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/041—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in subclass H10F
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F19/00—Integrated devices, or assemblies of multiple devices, comprising at least one photovoltaic cell covered by group H10F10/00, e.g. photovoltaic modules
    • H10F19/40—Integrated devices, or assemblies of multiple devices, comprising at least one photovoltaic cell covered by group H10F10/00, e.g. photovoltaic modules comprising photovoltaic cells in a mechanically stacked configuration
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy

Definitions

  • the present invention relates to the field of semiconductor devices, and, more particularly, to opto-electronic devices and related methods.
  • U.S. Patent No. 6,472,685 B2 to Takagi discloses a semiconductor device including a silicon and carbon layer sandwiched between silicon layers so that the conduction band and valence band of the second silicon layer receive a tensile strain. Electrons having a smaller effective mass, and which have been induced by an electric field applied to the gate electrode, are confined in the second siiicon layer, thus, an n-channel MOSFET is asserted to have a higher mobiiity.
  • U.S. Patent No. 4,937,204 to lshibashi et al. discloses a superlattice in which a plurality of layers, less than eight monolayers, and containing a fraction or a binary compound semiconductor layers, are alternately and epitaxiaily grown. The direction of main current flow is perpendicular to the layers of the superlattice.
  • U.S. Patent No. 5,357,119 to Wang et al. discloses a Si-Ge short period superlattice with higher mobiiity achieved by reducing alloy scattering in the superlattice.
  • U.S. Patent No. 5,683,934 to Candelaria discloses an enhanced mobility MOSFET including a channel layer comprising an alloy of siiicon and a second materia! substitutional ⁇ present in the silicon lattice at a percentage that places the channel layer under tensile stress.
  • U.S. Patent No. 5,216,262 to Tsu discloses a quantum well structure comprising two barrier regions and a thin epitaxiaily grown semiconductor layer sandwiched between the barriers. Each barrier region consists of alternate layers of SiO 2 /Si with a thickness generally in a range of two to six monolayers. A much thicker section of silicon is sandwiched between the barriers.
  • SAS semiconductor- atomic superlattice
  • the Si/O superlattice is disclosed as useful in silicon quantum and light-emitting devices.
  • a green electroluminescence diode structure was constructed and tested. Current flow in the diode structure is vertical, that is, perpendicular to the layers of the SAS.
  • the disclosed SAS may include semiconductor layers separated by adsorbed species such as oxygen atoms, and CO molecules. The siiicon growth beyond the adsorbed monolayer of oxygen is described as epitaxial with a fairly low defect density.
  • One SAS structure included a 1.1 nm thick silicon portion that is about eight atomic layers of silicon, and another structure had twice this thickness of silicon.
  • An article to Luo et al. entitled “Chemical Design of Direct-Gap Light-Emitting Silicon” published in Physical Review Letters, Vol. 89, No. 7 (August 12, 2002) further discusses the light emitting SAS structures of Tsu.
  • optical devices For example, typical optical detectors used in solar (i.e., photovoltaic) cells are made of amorphous silicon and are thus relatively inefficient. As such, to provide desired power output in many applications a relatively large surface area has to be covered with such solar cells, which may not be practical. Accordingly, it would be desirable to incorporate materials with enhanced mobility in solar cells to improve efficiency thereof with reduced weight and/or surface area requirements.
  • a muitipie-waveiength opto-electronic device may include a substrate and a plurality of active optical devices carried by the substrate and operating at different respective wavelengths.
  • each optical device may include a superlattice comprising a plurality of stacked groups of layers, and each group of layers may include a plurality of stacked semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer thereon.
  • the at least one non-semiconductor monolayer may be constrained within a crystal lattice of adjacent base semiconductor portions, and at least some semiconductor atoms from opposing base semiconductor portions may be chemically bound together through the at least one non- semiconductor monolayer therebetween.
  • each active optica! device may further include first and second semiconductor regions on opposing sides of the superlattice and having opposite conductivity types.
  • the optical devices may be stacked in a vertical direction, as well as positioned laterally adjacent one another, for example.
  • the plurality of superlattices may have different numbers of semiconductor monolayers in their respective base semiconductor portions, for example.
  • the active optica! devices may be optica! detectors.
  • the optical detectors may be configured to provide an output equal to a sum of photocurrents therefrom, thereby providing an efficient solar cell arrangement.
  • the active optical devices may comprise optical transmitters, or both optical detectors and transmitters may be used in the same device.
  • Each superlattice may have a substantially direct bandgap.
  • each superlattice may also have a different respective bandgap.
  • the multiple- wavelength opto-eiectronic device may further include at least one contact coupled to the plurality of active optical devices.
  • the substrate may comprise various materials including semiconductors and non-semiconductors. In accordance with one exemplary embodiment, the substrate may comprise glass.
  • each base semiconductor portion may comprise a base semiconductor selected from the group consisting of Group ( V semiconductors, Group ill-V semiconductors, and Group II-VI semiconductors.
  • the base semiconductor portions may comprise silicon.
  • each non-semiconductor monolayer may comprise a non-semiconductor selected from the group consisting of oxygen, nitrogen, fluorine, and carbon- oxygen, for example.
  • a method aspect is for making a multiple-wavelength opto-eiectronic device.
  • the method may comprise providing a substrate, and forming a plurality of active optical devices to be carried by the substrate and operating at different respective wavelengths.
  • each active optical device may include a superlattice comprising a plurality of stacked groups of layers, and with each group of layers comprising a plurality of stacked semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer thereon.
  • FIG. 1 is a greatly enlarged schematic cross-sectional view of a superlattice for use in a semiconductor device in accordance with the present invention.
  • FIG. 2 is a perspective schematic atomic diagram of a portion of the superlattice shown in FIG. 1.
  • FIG. 3 is a greatly enlarged schematic cross-sectional view of another embodiment of a superlattice in accordance with the invention.
  • FiG. 4A is a graph of the calculated band structure from the gamma point (G) for both bulk siiicon as in the prior art, and for the 4/1 Si/O superlattice as shown in FIGS. 1-2.
  • FIG. 4B is a graph of the calculated band structure from the Z point for both bulk silicon as in the prior art, and for the 4/1 Si/O superlattice as shown in FIGS. 1-2.
  • FIG. 4C is a graph of the calculated band structure from both the gamma and Z points for both bulk silicon as in the prior art, and for the 5/1/3/1 Si/O superlattice as shown in FIG. 3.
  • FIG. 5 is a schematic block diagram of a multiple-wavelength optoelectronic device including a plurality of vertically stacked optical devices each with a respective superiattice in accordance with the invention.
  • FIG. 6 is a graph of absorption vs. energy curves for pure silicon and a plurality of superlattice structures for use in accordance with the invention.
  • FIG. 7 is a schematic block diagram of an alternative embodiment of the multiple-wavelength opto-eiectronic device of FIG. 5 including a plurality of laterally adjacent optical devices.
  • the present invention relates to controlling the properties of semiconductor materials at the atomic or molecular level. Further, the invention relates to the identification, creation, and use of improved materials for use in semiconductor devices.
  • f is the Fermi-Dirac distribution
  • EF is the Fermi energy
  • T is the temperature
  • E(k,n) is the energy of an electron in the state corresponding to wave vector k and the n th energy band
  • the indices i and j refer to Cartesian coordinates x, y and z
  • the integrals are taken over the Brillouin zone (B.Z.)
  • the summations are taken over bands with energies above and below the Fermi energy for electrons and holes respectively.
  • the effective mass tensor is such that a tensoriai component of the conductivity of the material is greater for greater values of the corresponding component of the conductivity reciprocal effective mass tensor.
  • the superlattices described herein set the values of the conductivity reciprocal effective mass tensor so as to enhance the conductive properties of the material, such as typicaliy for a preferred direction of charge carrier transport.
  • the inverse of the appropriate tensor element is referred to as the conductivity effective mass.
  • the conductivity effective mass for electrons/holes as described above and calculated in the direction of intended carrier transport is used to distinguish improved materials.
  • the materials or structures are in the form of a superlattice 25 whose structure is controlled at the atomic or molecular level and may be formed using known techniques of atomic or molecular layer deposition.
  • the superlattice 25 includes a plurality of layer groups 45a-45n arranged in stacked relation, as perhaps best understood with specific reference to the schematic cross-sectional view of FIG. 1.
  • Each group of layers 45a-45n of the superlattice 25 illustratively includes a plurality of stacked base semiconductor monolayers 46 defining a respective base semiconductor portion 46a-46n and an energy band- modifying layer 50 thereon.
  • the energy band-modifying layers 50 are indicated by stippling in FIG. 1 for clarity of illustration.
  • the energy band-modifying layer 50 illustratively includes one non- semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.
  • non-semiconductor monolayer may be possible.
  • reference herein to a non- semiconductor or semiconductor monolayer means that the material used for the monolayer would be a non-semiconductor or semiconductor if formed in bulk. That is, a single monolayer of a material, such as silicon, may not necessarily exhibit the same properties that it would if formed in bulk or in a relatively thick layer, as will be appreciated by those skilled in the art.
  • energy band-modifying layers 50 and adjacent base semiconductor portions 46a-46n cause the superlattice 25 to have a lower appropriate conductivity effective mass for the charge carriers in the parallel layer direction than would otherwise be present.
  • the band-modifying layers 50 may also cause the superlattice 25 to have a common energy band structure.
  • the band modifying layers 50 may also cause the superlattice 25 to have a common energy band structure, while also advantageously functioning as an insulator between layers or regions vertically above and below the superlattice.
  • this superlattice structure may also advantageously act as a barrier to dopant and/or material diffusion between layers vertically above and below the superlattice 25.
  • the superlattice 25 may provide an interface for high-K dielectrics which not only reduces diffusion of the high-K material into the channel region, but which may also advantageously reduce unwanted scattering effects and improve device mobility, as will be appreciated by those skilled in the art.
  • semiconductor devices including the superlattice 25 may enjoy a higher charge carrier mobility based upon the lower conductivity effective mass than would otherwise be present.
  • the superlattice 25 may further have a substantially direct energy bandgap that may be particularly advantageous for opto-electronic devices, as wili be discussed further below, for example.
  • the superlattice 25 also illustratively includes a cap layer 52 on an upper layer group 45n.
  • the cap layer 52 may comprise a plurality of base semiconductor monolayers 46.
  • the cap layer 52 may have between 2 to 100 monolayers of the base semiconductor, and, more preferably between 10 to 50 monolayers.
  • Each base semiconductor portion 46a-46n may comprise a base semiconductor selected from the group consisting of Group IV semiconductors, Group IH-V semiconductors, and Group Ii-Vl semiconductors.
  • Group IV semiconductors aiso includes Group IV-IV semiconductors, as will be appreciated by those skilled in the art.
  • the base semiconductor may comprise at least one of silicon and germanium, for example.
  • Each energy band-modifying layer 50 may comprise a non- semiconductor selected from the group consisting of oxygen, nitrogen, fluorine, and carbon-oxygen, for example.
  • the non-semiconductor is also desirably thermally stable through deposition of a next layer to thereby facilitate manufacturing.
  • the non-semiconductor may be another inorganic or organic element or compound that is compatible with the given semiconductor processing as will be appreciated by those skilled in the art.
  • the term monolayer is meant to include a single atomic layer and also a single molecular layer.
  • the energy band-modifying iayer 50 provided by a single monolayer is also meant to include a monolayer wherein not all of the possible sites are occupied (i.e., there is less than full or 100% coverage).
  • a 4/1 repeating structure is illustrated for silicon as the base semiconductor materia!, and oxygen as the energy band-modifying material. Only half of the possible sites for oxygen are occupied in the illustrated example.
  • this one half occupation would not necessarily be the case, as will be appreciated by those skilled in the art. Indeed, it can be seen even in this schematic diagram that individual atoms of oxygen in a given monolayer are not precisely aligned along a flat plane, as will also be appreciated by those of skill in the art of atomic deposition. By way of example, a preferred occupation range is from about one-eighth to one-half of the possible oxygen sites being full, although other numbers may be used in certain embodiments. [0045] Silicon and oxygen are currently widely used in conventional semiconductor processing, and, hence, manufacturers will be readily able to use these materials as described herein. Atomic or monolayer deposition is also now widely used.
  • the lower conductivity effective mass for the 4/1 Si/O embodiment of the superlattice 25 may be less than two-thirds the conductivity effective mass than would otherwise occur, and this applies for both electrons and holes.
  • the superlattice 25 may further comprise at least one type of conductivity dopant therein, as will also be appreciated by those skilled in the art.
  • FIG. 3 another embodiment of a superlattice 25' in accordance with the invention having different properties is now described.
  • a repeating pattern of 3/1/5/1 is illustrated. More particularly, the lowest base semiconductor portion 46a' has three monolayers, and the second lowest base semiconductor portion 46b' has five monolayers. This pattern repeats throughout the superlattice 25'.
  • the energy band-modifying layers 50' may each include a single monolayer.
  • the enhancement of charge carrier mobility is independent of orientation in the plane of the layers.
  • all of the base semiconductor portions of a superlattice may be a same number of monolayers thick. In other embodiments, at least some of the base semiconductor portions may be a different number of monolayers thick. In still other embodiments, all of the base semiconductor portions may be a different number of monolayers thick.
  • DFT Density Functional Theory
  • 4A shows the calculated band structure from the gamma point (G) for both bulk silicon (represented by continuous lines) and for the 4/1 Si/O superlattice 25 shown in FIG. 1 (represented by dotted lines).
  • the directions refer to the unit cell of the 4/1 Si/O structure and not to the conventional unit celi of Si, although the (001) direction in the figure does correspond to the (001) direction of the conventional unit ceil of Si, and, hence, shows the expected location of the Si conduction band minimum.
  • the (100) and (010) directions in the figure correspond to the (110) and (-110) directions of the conventional Si unit cell.
  • the conduction band minimum for the 4/1 Si/O structure is located at the gamma point in contrast to bulk silicon (Si), whereas the valence band minimum occurs at the edge of the Brillouin zone in the (001) direction which we refer to as the Z point.
  • the greater curvature of the conduction band minimum for the 4/1 Si/O structure compared to the curvature of the conduction band minimum for Si owing to the band splitting due to the perturbation introduced by the additional oxygen layer.
  • FIG. 4B shows the calculated band structure from the Z point for both bulk silicon (continuous lines) and for the 4/1 Si/O superlattice 25 (dotted lines). This figure illustrates the enhanced curvature of the valence band in the (100) direction.
  • FIG. 4C shows the calculated band structure from both the gamma and Z point for both bulk silicon (continuous lines) and for the 5/1/3/1 Si/O structure of the superiattice 25' of FIG. 3 (dotted lines). Due to the symmetry of the 5/1/3/1 Si/O structure, the calculated band structures in the (100) and (010) directions are equivalent. Thus the conductivity effective mass and mobility are expected to be isotropic in the plane parallel to the layers, i.e. perpendicular to the (001) stacking direction. Note that in the 5/1/3/1 Si/O example the conduction band minimum and the valence band maximum are both at or close to the Z point.
  • the PV ceil 20 iliustrativeiy includes a substrate 21 and a plurality of active optica! devices 22a-22n carried by the substrate and operating at different respective wavelengths.
  • each active optical device 22 includes a first semiconductor layer 23, a superlattice layer 25 vertically stacked on the first semiconductor layer, and a second semiconductor layer 24 vertically stacked on the superlattice layer 25.
  • the active optical devices 25a-25n are vertically stacked on top of one another as shown.
  • a top or upper terminal contact 26 is on the uppermost active optical device 22a, and a bottom or backside contact 27 is on the substrate 21 opposite the bottommost active optical device 22n, as shown.
  • the upper terminal contact 26 layer is preferably a transparent contact, such as a transparent conductive oxide (TCO) (e.g., fluorine-doped tin oxide, doped zinc oxide, and indium tin oxide), although other suitable materials may also be used.
  • TCO transparent conductive oxide
  • the backside contact 27 may be any suitable material such as metal, for example, although other contact materials may also be used.
  • the first and second semiconductor layers 23, 24 are oppositely doped to define a PiN structure with the superlattice layer 25 therebetween.
  • the first semiconductor layers 23a-23n are P-type
  • the second semiconductor layers 24a-24n are N-type, although other configurations are also possible (e.g., these layers could be doped with the opposite conductivity type).
  • the upper terminal contact 26 is a -Ve contact
  • the backside contact 27 is a +Ve contact.
  • the direct bandgap nature of the superiattice layer 25 makes it a more efficient optical detector (or transmitter) layer than silicon alone.
  • the superiattice 25 also functions as a dopant diffusion blocking layer as discussed above, the superiattice is also well suited for use between P and N type layers, since the superiattice will advantageously reduce dopant diffusion or creep therebetween. Further details regarding the use of the above-described superiattice structures as dopant blocking layers may be found in co-pending U.S. application serial no. 11/380,992, which is assigned to the present Assignee and is hereby incorporated herein in its entirety by reference.
  • portions of the superiattice 25 may instead be doped with a P/N region to define a PN junction with an N/P region above or below the superiattice 25, or both N and P regions may be doped in the superiattice layer.
  • Further details on superiattice structures with regions of doping to provide PN junctions therein or in conjunction with an adjacent semiconductor layer may be found in U.S. Patent No. 7,045,813 and co-pending U.S. application serial no. 11/097,612, both of which are assigned to the present Assignee and are hereby incorporated herein in their entireties by reference.
  • the substrate 21 may be a semiconductor substrate, such as silicon, for example, although other semiconductors may also be used (germanium, silicon-germanium, etc.). While the substrate 21 may be monocrystalline silicon and the layers 23-25 may be formed directly thereon in some embodiments, to provide cost savings an amorphous silicon substrate may also be used by epitaxially forming the layer 23n (i.e., a monocrysta ⁇ ine layer) on a separate monocrystaiiine substrate and transferring this layer to the amorphous substrate.
  • a monocrysta ⁇ ine layer i.e., a monocrysta ⁇ ine layer
  • the superlattice layer 25n which also advantageously has a crystalline structure as discussed above, and the semiconductor layer 24n may then be formed on the crystalline layer 23n by epitaxial deposition, following by the deposition of the various layers 23-25 of the remaining optical detectors 22, as will be appreciated by those skilled in the art.
  • An alternative approach is to form one or more of the devices 22a-22n on a separate crystalline substrate and then transfer the device(s) to the substrate 21, as will aiso be appreciated by those skilled in the art. in other embodiments, non-semiconductor substrates may also be used.
  • each of the active optical devices 22a-22n advantageously operates at different respective wavelengths Aa- ⁇ n.
  • each of the active optical devices 22a-22n i.e., optical detectors in the present PV cell embodiment
  • the PV cell advantageously provides enhanced efficiency with respect to a typical single layer solar cell.
  • the optical detectors 22a-22n are configured to provide an output equal to a sum of photocurrents therefrom.
  • each photon of sunlight creates an electron-hole pair that, if formed in the PN junction region and experiences an electric field, separates and moves in opposite directions resulting in current flow.
  • Voltage can either be measured across the detectors 22a-22n (for an open-circuit) or a current (with a closed-circuit), but practically speaking, the power output (which is the product of the voltage and current) is preferably optimized for the given application, as will be appreciated by those skilled in the art.
  • the higher bandgap superlattice layer 25 generates a larger voltage output for the photovoltaic (PV) cell, and hence, delivers more power for an equivalent absorption efficiency (i.e. current). While there may potentially be some trade-off between closed-circuit current and open-circuit voltage when creating the PV cell 20, the stacking of several active optical detectors 22 provides a multilayer PV cell that captures an increased amount of electromagnetic (EM) radiation across a wide spectrum of energies.
  • EM electromagnetic
  • the superlattice SL1 is a 4-1 Si/O structure
  • the superlattice SL2 is a 8-1 Si/O structure
  • the superlattice SL3 is a 12-1 Si/O with 50% coverage structure.
  • another embodiment of a multiple- wavelength opto-electronic device 20' illustratively includes laterally adjacent active optical devices 22a' and 22b', although more than just the two illustrated devices may be used.
  • the active optica! devices 22a' and 22b' may be optical transmitters, optical detectors, or a combination of both optical detectors and transmitters, as will be appreciated by those skilled in the art.
  • the active optical devices 22a' and 22b' may be used in lasers, optical communications devices, etc.
  • the optical devices 22a' and 22b* may be coupled to respective waveguides, or to a common waveguide using wave division multipiexing (WDM) techniques known to those skilled in the art, for example.
  • WDM wave division multipiexing
  • the active optical devices are aiso implemented on a semiconductor (e.g., silicon) on insulator (SOi) substrate 21' having an insulating (e.g., oxide) layer 28' thereon.
  • SOI semiconductor
  • insulator oxide
  • FIG. 11 an insulating or shallow trench isolation (STI) region 29' is illustratively included between the active optical devices 22a', 22b'.
  • STI shallow trench isolation

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Abstract

Dispositif optoélectronique à longueur d'onde multiple pouvant inclure un substrat et une pluralité de dispositifs optiques actifs portés par le substrat et fonctionnant à différentes longueurs d'onde respectives. Chaque dispositif optique peut inclure un super-réseau comprenant une pluralité de groupes de couches (45) empilées et chaque groupe de couches peut comprendre une pluralité de mono-couches de semi-conducteurs (46) empilées, définissant une portion de semi-conducteur de base et au moins une mono-couche sans semi-conducteur (50) dessus.
PCT/US2008/054210 2007-02-16 2008-02-18 Dispositif optoélectronique à longueur d'onde multiple comprenant un super-réseau et procédés associés Ceased WO2008101232A1 (fr)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US11/675,846 US7863066B2 (en) 2007-02-16 2007-02-16 Method for making a multiple-wavelength opto-electronic device including a superlattice
US11/675,833 2007-02-16
US11/675,833 US7880161B2 (en) 2007-02-16 2007-02-16 Multiple-wavelength opto-electronic device including a superlattice
US11/675,846 2007-02-16

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Cited By (3)

* Cited by examiner, † Cited by third party
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US9406753B2 (en) 2013-11-22 2016-08-02 Atomera Incorporated Semiconductor devices including superlattice depletion layer stack and related methods
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US9406753B2 (en) 2013-11-22 2016-08-02 Atomera Incorporated Semiconductor devices including superlattice depletion layer stack and related methods
WO2024191733A1 (fr) * 2023-03-10 2024-09-19 Atomera Incorporated Procédé de fabrication d'une structure silicium sur isolant radiofréquence (rfsoi) comprenant un super-réseau

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