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WO2008155829A1 - 情報処理装置，キャッシュメモリ制御装置およびメモリアクセス順序保証方法 - Google Patents

情報処理装置，キャッシュメモリ制御装置およびメモリアクセス順序保証方法 Download PDF

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Publication number
WO2008155829A1
WO2008155829A1 PCT/JP2007/062389 JP2007062389W WO2008155829A1 WO 2008155829 A1 WO2008155829 A1 WO 2008155829A1 JP 2007062389 W JP2007062389 W JP 2007062389W WO 2008155829 A1 WO2008155829 A1 WO 2008155829A1
Authority
WO
WIPO (PCT)
Prior art keywords
request
instruction
reexecution
store
processing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2007/062389
Other languages
English (en)
French (fr)
Inventor
Naohiro Kiyota
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to KR1020097025129A priority Critical patent/KR101084228B1/ko
Priority to EP07767228A priority patent/EP2159703A4/en
Priority to CN200780053369A priority patent/CN101689142A/zh
Priority to PCT/JP2007/062389 priority patent/WO2008155829A1/ja
Priority to JP2009520183A priority patent/JP4983919B2/ja
Publication of WO2008155829A1 publication Critical patent/WO2008155829A1/ja
Priority to US12/654,380 priority patent/US8103859B2/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0844—Multiple simultaneous or quasi-simultaneous cache accessing
    • G06F12/0855—Overlapped cache accessing, e.g. pipeline
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3824—Operand accessing
    • G06F9/3834—Maintaining memory consistency
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3851—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution from multiple instruction streams, e.g. multistreaming
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/52—Program synchronisation; Mutual exclusion, e.g. by means of semaphores

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multimedia (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Advance Control (AREA)

Abstract

　あるスレッドのストア処理でキャッシュＲＡＭ２１上のデータが書き換えられると，アドレス一致判定回路２５は，他のスレッドの要求を保持するフェッチポート２２を検索し，処理完了済みであり，ロード系の命令であり，かつその命令の対象アドレスがストア処理の対象アドレスと一致する要求があるかをチェックし，該当する要求が検出されれば，最も古い要求を保持するエントリの次から前記検出された要求を保持するエントリまでのフェッチポート２２のすべてのエントリに，ストアによる命令再実行要求フラグをセットする。命令再実行要求回路２６は，前記最も古い要求の処理が行われると，ストアによる命令再実行要求フラグがセットされているエントリに保持された要求について，命令制御部１０に対して命令の再実行要求を送る。これにより，ＳＭＴのプロセッサにおいてスレッド間のデータ更新の順序性を保証する。
PCT/JP2007/062389 2007-06-20 2007-06-20 情報処理装置，キャッシュメモリ制御装置およびメモリアクセス順序保証方法 Ceased WO2008155829A1 (ja)

Priority Applications (6)

Application Number Priority Date Filing Date Title
KR1020097025129A KR101084228B1 (ko) 2007-06-20 2007-06-20 정보 처리 장치, 캐시 메모리 제어 장치 및 메모리 액세스 순서 보증 방법
EP07767228A EP2159703A4 (en) 2007-06-20 2007-06-20 INFORMATION PROCESSOR, CACHE MEMORY CONTROL, AND MEMORY ACCESS SEQUENCES PROCESSING
CN200780053369A CN101689142A (zh) 2007-06-20 2007-06-20 信息处理装置、高速缓冲存储器控制装置以及存储器访问顺序保证方法
PCT/JP2007/062389 WO2008155829A1 (ja) 2007-06-20 2007-06-20 情報処理装置，キャッシュメモリ制御装置およびメモリアクセス順序保証方法
JP2009520183A JP4983919B2 (ja) 2007-06-20 2007-06-20 演算処理装置および演算処理装置の制御方法
US12/654,380 US8103859B2 (en) 2007-06-20 2009-12-17 Information processing apparatus, cache memory controlling apparatus, and memory access order assuring method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2007/062389 WO2008155829A1 (ja) 2007-06-20 2007-06-20 情報処理装置，キャッシュメモリ制御装置およびメモリアクセス順序保証方法

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US12/654,380 Continuation US8103859B2 (en) 2007-06-20 2009-12-17 Information processing apparatus, cache memory controlling apparatus, and memory access order assuring method

Publications (1)

Publication Number Publication Date
WO2008155829A1 true WO2008155829A1 (ja) 2008-12-24

Family

ID=40155995

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2007/062389 Ceased WO2008155829A1 (ja) 2007-06-20 2007-06-20 情報処理装置，キャッシュメモリ制御装置およびメモリアクセス順序保証方法

Country Status (6)

Country Link
US (1) US8103859B2 (ja)
EP (1) EP2159703A4 (ja)
JP (1) JP4983919B2 (ja)
KR (1) KR101084228B1 (ja)
CN (1) CN101689142A (ja)
WO (1) WO2008155829A1 (ja)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011134205A (ja) * 2009-12-25 2011-07-07 Fujitsu Ltd 情報処理装置およびキャッシュメモリ制御装置
JP2015036889A (ja) * 2013-08-13 2015-02-23 富士通株式会社 演算処理装置及び演算処理装置の制御方法
JP2016186689A (ja) * 2015-03-27 2016-10-27 富士通株式会社 演算処理装置及び演算処理装置の制御方法
US10489158B2 (en) 2014-09-26 2019-11-26 Intel Corporation Processors, methods, systems, and instructions to selectively fence only persistent storage of given data relative to subsequent stores

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JP5966759B2 (ja) * 2012-08-20 2016-08-10 富士通株式会社 演算処理装置および演算処理装置の制御方法
KR101993258B1 (ko) 2012-11-22 2019-09-27 삼성전자주식회사 레지스터 슬라이싱 회로 및 이를 포함하는 시스템 온 칩
US9361176B2 (en) * 2014-06-25 2016-06-07 International Business Machines Corporation Detecting the use of stale data values due to weak consistency
CN106527959B (zh) * 2015-09-10 2019-07-26 阿里巴巴集团控股有限公司 刷新磁盘输入输出请求的处理方法及设备
CN112445587A (zh) * 2019-08-30 2021-03-05 上海华为技术有限公司 一种任务处理的方法以及任务处理装置

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WO2004068361A1 (ja) * 2003-01-27 2004-08-12 Fujitsu Limited 記憶制御装置、データキャッシュ制御装置、中央処理装置、記憶装置制御方法、データキャッシュ制御方法およびキャッシュ制御方法
JP2006048696A (ja) * 2004-07-30 2006-02-16 Intel Corp 複数の順序ベクトルで複数のメモリ順序モデルを実施する方法及び装置

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011134205A (ja) * 2009-12-25 2011-07-07 Fujitsu Ltd 情報処理装置およびキャッシュメモリ制御装置
JP2015036889A (ja) * 2013-08-13 2015-02-23 富士通株式会社 演算処理装置及び演算処理装置の制御方法
US10489158B2 (en) 2014-09-26 2019-11-26 Intel Corporation Processors, methods, systems, and instructions to selectively fence only persistent storage of given data relative to subsequent stores
JP2016186689A (ja) * 2015-03-27 2016-10-27 富士通株式会社 演算処理装置及び演算処理装置の制御方法

Also Published As

Publication number Publication date
JPWO2008155829A1 (ja) 2010-08-26
EP2159703A4 (en) 2010-12-08
US20100100710A1 (en) 2010-04-22
JP4983919B2 (ja) 2012-07-25
US8103859B2 (en) 2012-01-24
CN101689142A (zh) 2010-03-31
EP2159703A1 (en) 2010-03-03
KR101084228B1 (ko) 2011-11-17
KR20100006578A (ko) 2010-01-19

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