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WO2008155849A1 - 演算処理装置、ｔｌｂ制御方法、ｔｌｂ制御プログラムおよび情報処理装置 - Google Patents

演算処理装置、ｔｌｂ制御方法、ｔｌｂ制御プログラムおよび情報処理装置 Download PDF

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Publication number
WO2008155849A1
WO2008155849A1 PCT/JP2007/062463 JP2007062463W WO2008155849A1 WO 2008155849 A1 WO2008155849 A1 WO 2008155849A1 JP 2007062463 W JP2007062463 W JP 2007062463W WO 2008155849 A1 WO2008155849 A1 WO 2008155849A1
Authority
WO
WIPO (PCT)
Prior art keywords
processor
tlb
address
translation request
tlb control
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2007/062463
Other languages
English (en)
French (fr)
Inventor
Masanori Doi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to PCT/JP2007/062463 priority Critical patent/WO2008155849A1/ja
Priority to JP2009520203A priority patent/JPWO2008155849A1/ja
Priority to EP07767301A priority patent/EP2169557A4/en
Publication of WO2008155849A1 publication Critical patent/WO2008155849A1/ja
Priority to US12/654,379 priority patent/US20100100702A1/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
    • G06F12/1036—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] for multiple virtual address spaces, e.g. segmentation
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/68—Details of translation look-aside buffer [TLB]
    • G06F2212/681—Multi-level TLB, e.g. microTLB and main TLB

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)

Abstract

　この演算処理装置は、仮想アドレスと物理アドレスとの対応を示す複数のエントリをページテーブルとして保持するメインＴＬＢと、メインＴＬＢに保持されるページテーブルの一部を保持するマイクロＴＬＢとを備える。このような構成において、演算処理装置は、メインＴＬＢに保持される物理アドレスと、当該物理アドレスに関連付けられた仮想アドレスと、アドレス変換要求に含まれるコンテキストＩＤとを対応付けてエントリとしてマイクロＴＬＢに登録し、アドレス変換要求を受信した場合に、当該アドレス変換要求に含まれるコンテキストＩＤをコンテキスト値に変換することなく、当該アドレス変換要求に含まれる仮想アドレスとコンテキストＩＤとに一致するエントリをマイクロＴＬＢから検索し、エントリが検索された場合に、エントリに含まれる物理アドレスを応答し、エントリが検索されなかった場合に、アドレス変換要求をメインＴＬＢに送信する。
PCT/JP2007/062463 2007-06-20 2007-06-20 演算処理装置、ｔｌｂ制御方法、ｔｌｂ制御プログラムおよび情報処理装置 Ceased WO2008155849A1 (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
PCT/JP2007/062463 WO2008155849A1 (ja) 2007-06-20 2007-06-20 演算処理装置、ｔｌｂ制御方法、ｔｌｂ制御プログラムおよび情報処理装置
JP2009520203A JPWO2008155849A1 (ja) 2007-06-20 2007-06-20 演算処理装置、ｔｌｂ制御方法、ｔｌｂ制御プログラムおよび情報処理装置
EP07767301A EP2169557A4 (en) 2007-06-20 2007-06-20 PROCESSOR, TLB CONTROL PROCEDURE, TLB CONTROL PROGRAM AND INFORMATION PROCESSOR
US12/654,379 US20100100702A1 (en) 2007-06-20 2009-12-17 Arithmetic processing apparatus, TLB control method, and information processing apparatus

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2007/062463 WO2008155849A1 (ja) 2007-06-20 2007-06-20 演算処理装置、ｔｌｂ制御方法、ｔｌｂ制御プログラムおよび情報処理装置

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US12/654,379 Continuation US20100100702A1 (en) 2007-06-20 2009-12-17 Arithmetic processing apparatus, TLB control method, and information processing apparatus

Publications (1)

Publication Number Publication Date
WO2008155849A1 true WO2008155849A1 (ja) 2008-12-24

Family

ID=40156015

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2007/062463 Ceased WO2008155849A1 (ja) 2007-06-20 2007-06-20 演算処理装置、ｔｌｂ制御方法、ｔｌｂ制御プログラムおよび情報処理装置

Country Status (4)

Country Link
US (1) US20100100702A1 (ja)
EP (1) EP2169557A4 (ja)
JP (1) JPWO2008155849A1 (ja)
WO (1) WO2008155849A1 (ja)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2011084542A1 (en) * 2009-12-15 2011-07-14 Qualcomm Incorporated Apparatuses, systems, and methods for reducing translation lookaside buffer (tlb) lookups
JP2012530960A (ja) * 2009-06-26 2012-12-06 インテル・コーポレーション 無制限トランザクショナルメモリ（ｕｔｍ）システムの最適化

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2929729A1 (fr) * 2008-04-03 2009-10-09 Alveol Technology Sarl Dispositif de gestion de la memoire d'un environnement informatique
US9921967B2 (en) * 2011-07-26 2018-03-20 Intel Corporation Multi-core shared page miss handler
JP2013125355A (ja) * 2011-12-13 2013-06-24 Fujitsu Ltd 演算処理装置および演算処理装置の制御方法
US9672159B2 (en) * 2015-07-02 2017-06-06 Arm Limited Translation buffer unit management
US11144472B2 (en) * 2019-03-27 2021-10-12 Intel Corporation Memory management apparatus and method for managing different page tables for different privilege levels

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61221846A (ja) * 1985-03-27 1986-10-02 Fujitsu Ltd アドレス変換制御方式
JPS6381548A (ja) * 1986-09-25 1988-04-12 Matsushita Electric Ind Co Ltd 高速アドレス変換装置
JPH03156542A (ja) * 1989-08-29 1991-07-04 Hitachi Ltd アドレス変換装置及びそのためのアドレス情報の管理方法
JPH03235144A (ja) * 1990-02-13 1991-10-21 Sanyo Electric Co Ltd キャッシュメモリ制御装置
JPH08272692A (ja) * 1995-03-09 1996-10-18 Hewlett Packard Co <Hp> 仮想アドレス変換方法
JP2000122927A (ja) * 1998-10-12 2000-04-28 Hewlett Packard Co <Hp> 仮想領域番号によってアクセスするコンピュ―タ・システム
JP2005044363A (ja) * 2003-07-22 2005-02-17 Samsung Electronics Co Ltd 複数のスレッドを同時に処理する装置及び方法

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5619576A (en) * 1979-07-25 1981-02-24 Fujitsu Ltd Address matching detection system in multiple-space processing data processing system
JPS6057449A (ja) * 1983-09-09 1985-04-03 Hitachi Ltd 仮想計算機システムのアドレス変換方式
JPS60209862A (ja) * 1984-02-29 1985-10-22 Panafacom Ltd アドレス変換制御方式
US5237671A (en) * 1986-05-02 1993-08-17 Silicon Graphics, Inc. Translation lookaside buffer shutdown scheme
JP2510605B2 (ja) * 1987-07-24 1996-06-26 株式会社日立製作所 仮想計算機システム
JPH05173881A (ja) * 1991-12-19 1993-07-13 Nec Corp 情報処理装置
JP3439337B2 (ja) * 1998-03-04 2003-08-25 日本電気株式会社 ネットワーク管理システム
JP3557947B2 (ja) * 1999-05-24 2004-08-25 日本電気株式会社 複数のプロセッサで同時にスレッドの実行を開始させる方法及びその装置並びにコンピュータ可読記録媒体
US6420903B1 (en) * 2000-08-14 2002-07-16 Sun Microsystems, Inc. High speed multiple-bit flip-flop
US6742103B2 (en) * 2000-08-21 2004-05-25 Texas Instruments Incorporated Processing system with shared translation lookaside buffer
KR100591755B1 (ko) * 2003-07-22 2006-06-22 삼성전자주식회사 복수의 스레드를 동시에 처리하는 장치 및 방법
US8136111B2 (en) * 2006-06-27 2012-03-13 International Business Machines Corporation Managing execution of mixed workloads in a simultaneous multi-threaded (SMT) enabled system

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61221846A (ja) * 1985-03-27 1986-10-02 Fujitsu Ltd アドレス変換制御方式
JPS6381548A (ja) * 1986-09-25 1988-04-12 Matsushita Electric Ind Co Ltd 高速アドレス変換装置
JPH03156542A (ja) * 1989-08-29 1991-07-04 Hitachi Ltd アドレス変換装置及びそのためのアドレス情報の管理方法
JPH03235144A (ja) * 1990-02-13 1991-10-21 Sanyo Electric Co Ltd キャッシュメモリ制御装置
JPH08272692A (ja) * 1995-03-09 1996-10-18 Hewlett Packard Co <Hp> 仮想アドレス変換方法
JP2000122927A (ja) * 1998-10-12 2000-04-28 Hewlett Packard Co <Hp> 仮想領域番号によってアクセスするコンピュ―タ・システム
JP2005044363A (ja) * 2003-07-22 2005-02-17 Samsung Electronics Co Ltd 複数のスレッドを同時に処理する装置及び方法

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
WEAVER D.L. AND GERMOND T.: "The SPARC Architecture Manual, Version 9", 2003, PTR PRENTICE HALL, ISBN: 0-13-825001-4, pages: 287 - 290, XP003023939 *

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012530960A (ja) * 2009-06-26 2012-12-06 インテル・コーポレーション 無制限トランザクショナルメモリ（ｕｔｍ）システムの最適化
WO2011084542A1 (en) * 2009-12-15 2011-07-14 Qualcomm Incorporated Apparatuses, systems, and methods for reducing translation lookaside buffer (tlb) lookups

Also Published As

Publication number Publication date
EP2169557A1 (en) 2010-03-31
US20100100702A1 (en) 2010-04-22
EP2169557A4 (en) 2010-08-04
JPWO2008155849A1 (ja) 2010-08-26

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