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WO2008152151A3 - Strukturierte schichtabscheidung auf prozessierten wafern der mikrosystemtechnik - Google Patents

Strukturierte schichtabscheidung auf prozessierten wafern der mikrosystemtechnik Download PDF

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Publication number
WO2008152151A3
WO2008152151A3 PCT/EP2008/057579 EP2008057579W WO2008152151A3 WO 2008152151 A3 WO2008152151 A3 WO 2008152151A3 EP 2008057579 W EP2008057579 W EP 2008057579W WO 2008152151 A3 WO2008152151 A3 WO 2008152151A3
Authority
WO
WIPO (PCT)
Prior art keywords
layer deposition
mask
wafer
structured layer
processed wafers
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/EP2008/057579
Other languages
English (en)
French (fr)
Other versions
WO2008152151A2 (de
Inventor
Roy Knechtel
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
X Fab Semiconductor Foundries GmbH
Original Assignee
X Fab Semiconductor Foundries GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by X Fab Semiconductor Foundries GmbH filed Critical X Fab Semiconductor Foundries GmbH
Priority to US12/664,272 priority Critical patent/US20100311248A1/en
Publication of WO2008152151A2 publication Critical patent/WO2008152151A2/de
Publication of WO2008152151A3 publication Critical patent/WO2008152151A3/de
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/04—Coating on selected surface areas, e.g. using masks
    • C23C16/042—Coating on selected surface areas, e.g. using masks using masks
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
    • B81C1/00349—Creating layers of material on a substrate
    • B81C1/0038—Processes for creating layers of materials not provided for in groups B81C1/00357 - B81C1/00373
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/04—Coating on selected surface areas, e.g. using masks
    • C23C14/042—Coating on selected surface areas, e.g. using masks using masks
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C2201/00—Manufacture or treatment of microstructural devices or systems
    • B81C2201/01—Manufacture or treatment of microstructural devices or systems in or on a substrate
    • B81C2201/0101—Shaping material; Structuring the bulk substrate or layers on the substrate; Film patterning
    • B81C2201/0147—Film patterning
    • B81C2201/0154—Film patterning other processes for film patterning not provided for in B81C2201/0149 - B81C2201/015
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C2201/00—Manufacture or treatment of microstructural devices or systems
    • B81C2201/03—Processes for manufacturing substrate-free structures
    • B81C2201/038—Processes for manufacturing substrate-free structures not provided for in B81C2201/034 - B81C2201/036
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Chemical & Material Sciences (AREA)
  • Engineering & Computer Science (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Materials Engineering (AREA)
  • Mechanical Engineering (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • General Chemical & Material Sciences (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physical Vapour Deposition (AREA)
  • Chemical Vapour Deposition (AREA)

Abstract

Die Erfindung beschreibt eine Verfahrensweise und eine Durchdampfmaske zur strukturierten Schichtabscheidung mit einer besonders gestalteten Beschichtungsmaske (1), die Strukturen (4) aufweist, welche sich passgenau in komplementäre Justagestrukturen (5) des strukturiert zu beschichtenden (8) Mikrosystemtechnikwafers (2) setzen, so dass sich die Maske und der Wafer genau zueinander ausrichten lassen. Durch Löcher (7, 7') in der Beschichtungsmaske hindurch werden sehr exakt definierte Bereiche auf dem Mikrosystemtechnikwafer beschichtet (8), beispielsweise durch Sputtern, CVD oder Verdampfungsprozesse.
PCT/EP2008/057579 2007-06-14 2008-06-16 Strukturierte schichtabscheidung auf prozessierten wafern der mikrosystemtechnik Ceased WO2008152151A2 (de)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US12/664,272 US20100311248A1 (en) 2007-06-14 2008-06-16 Structured layer deposition on processed wafers used in microsystem technology

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE102007027435A DE102007027435A1 (de) 2007-06-14 2007-06-14 Verfahren und Vorrichtung zur strukturierten Schichtabscheidung auf prozessierten Mikrosystemtechnikwafern
DE102007027435.3 2007-06-14

Publications (2)

Publication Number Publication Date
WO2008152151A2 WO2008152151A2 (de) 2008-12-18
WO2008152151A3 true WO2008152151A3 (de) 2009-03-26

Family

ID=39986116

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/EP2008/057579 Ceased WO2008152151A2 (de) 2007-06-14 2008-06-16 Strukturierte schichtabscheidung auf prozessierten wafern der mikrosystemtechnik

Country Status (3)

Country Link
US (1) US20100311248A1 (de)
DE (1) DE102007027435A1 (de)
WO (1) WO2008152151A2 (de)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5298244B2 (ja) * 2010-10-19 2013-09-25 シャープ株式会社 蒸着装置
CN106784373A (zh) * 2016-12-27 2017-05-31 武汉华星光电技术有限公司 Oled保护膜的封装结构及其封装方法
KR102427557B1 (ko) * 2017-09-29 2022-08-01 삼성전자주식회사 반도체 패키지
CN109136836A (zh) * 2018-10-12 2019-01-04 京东方科技集团股份有限公司 掩膜板、晶圆、蒸镀装置及蒸镀方法

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3224234A1 (de) * 1981-09-01 1983-03-10 Siemens AG, 1000 Berlin und 8000 München Verfahren zur herstellung von metallfreien streifen bei der metallbedampfung eines isolierstoffbandes und vorrichtung zur durchfuehrung des verfahrens
US4980240A (en) * 1989-04-20 1990-12-25 Honeywell Inc. Surface etched shadow mask
US5154797A (en) * 1991-08-14 1992-10-13 The United States Of America As Represented By The Secretary Of The Army Silicon shadow mask
JP3372258B2 (ja) * 1995-08-04 2003-01-27 インターナシヨナル・ビジネス・マシーンズ・コーポレーシヨン リソグラフィ・プロセス用のスタンプ
US5810931A (en) * 1996-07-30 1998-09-22 Applied Materials, Inc. High aspect ratio clamp ring
US6080513A (en) * 1998-05-04 2000-06-27 International Business Machines Corporation Mask and method for modification of a surface
GB0007419D0 (en) * 2000-03-27 2000-05-17 Smithkline Beecham Gmbh Composition
DE10062713C1 (de) * 2000-12-15 2002-09-05 Zeiss Carl Verfahren zum Beschichten von Substraten und Maskenhaltern
JP2003253434A (ja) * 2002-03-01 2003-09-10 Sanyo Electric Co Ltd 蒸着方法及び表示装置の製造方法
JP2004183044A (ja) * 2002-12-03 2004-07-02 Seiko Epson Corp マスク蒸着方法及び装置、マスク及びマスクの製造方法、表示パネル製造装置、表示パネル並びに電子機器
JP3794407B2 (ja) * 2003-11-17 2006-07-05 セイコーエプソン株式会社 マスク及びマスクの製造方法、表示装置の製造方法、有機ｅｌ表示装置の製造方法、有機ｅｌ装置、及び電子機器
JP4971723B2 (ja) * 2006-08-29 2012-07-11 キヤノン株式会社 有機発光表示装置の製造方法

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
BRUGGER ET AL: "Resistless patterning of sub-micron structures by evaporation through nanostencils", MICROELECTRONIC ENGINEERING, ELSEVIER PUBLISHERS BV., AMSTERDAM, NL, vol. 53, no. 1-4, 1 June 2000 (2000-06-01), pages 403 - 405, XP022553210, ISSN: 0167-9317 *
KIM G ET AL: "All-photoplastic microstencil with self-alignment for multiple layer shadow-mask patterning", SENSORS AND ACTUATORS A, ELSEVIER SEQUOIA S.A., LAUSANNE, CH, vol. 107, no. 2, 15 October 2003 (2003-10-15), pages 132 - 136, XP004460579, ISSN: 0924-4247 *

Also Published As

Publication number Publication date
US20100311248A1 (en) 2010-12-09
DE102007027435A1 (de) 2008-12-18
WO2008152151A2 (de) 2008-12-18

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