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WO2008151138A1 - Transistor à effet de champ à mode d'amplification p-gan/algan/aln/gan - Google Patents

Transistor à effet de champ à mode d'amplification p-gan/algan/aln/gan Download PDF

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Publication number
WO2008151138A1
WO2008151138A1 PCT/US2008/065543 US2008065543W WO2008151138A1 WO 2008151138 A1 WO2008151138 A1 WO 2008151138A1 US 2008065543 W US2008065543 W US 2008065543W WO 2008151138 A1 WO2008151138 A1 WO 2008151138A1
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Prior art keywords
nitride
ill
layer
barrier layer
gate
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Chang Soo Suh
Umesh Kumar Mishra
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University of California Berkeley
University of California San Diego UCSD
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University of California Berkeley
University of California San Diego UCSD
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/40—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels
    • H10D30/47—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having 2D charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
    • H10D30/471—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT]
    • H10D30/475—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT] having wider bandgap layer formed on top of lower bandgap active layer, e.g. undoped barrier HEMTs such as i-AlGaN/GaN HEMTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/015—Manufacture or treatment of FETs having heterojunction interface channels or heterojunction gate electrodes, e.g. HEMT
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/343—Gate regions of field-effect devices having PN junction gates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/85—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group III-V materials, e.g. GaAs
    • H10D62/8503—Nitride Group III-V materials, e.g. AlN or GaN
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/602—Heterojunction gate electrodes for FETs

Definitions

  • the present invention relates to an improved enhancement mode field effect transistor (FET).
  • FET enhancement mode field effect transistor
  • Enhancement mode or normally-off devices, based on Gallium Nitride (GaN) technology are interesting for a variety of applications, for example, in integration of control circuitry and for the added safety of a normally-off device in power switching applications.
  • Enhancement mode operation is commonly achieved using an AlGaN/GaN buffer structure, by etching away some of the AlGaN under the gate region until all the charge is depleted [1], or by exposing the AlGaN under the gate with fluoride-based plasma until negatively charged fixed fluorine ions screen all the charge in the channel [2].
  • These devices suffer from threshold voltage non- uniformity and repeatability, due to the processes requiring gate recess etch or plasma treatment.
  • these devices have a low Schottky gate turn-on voltage (of at most 2 V) due to low Schottky barriers. If a threshold voltage of 1 V is required, these devices are left with a maximum modulation of 1 V. Because high-power switching applications require a threshold voltage of over 1 V for gate signal noise immunity, increasing the gate turn-on voltage is crucial.
  • the present invention discloses a novel enhancement mode High Electron Mobility Transistor (HEMT) structure with a p-GaN cap layer for high gate turn-on plus an aluminum nitride (AlN) interlayer for low on-resistance.
  • HEMT High Electron Mobility Transistor
  • this transistor Under the gate, this transistor has a p-GaN/AlGaN/AlN/GaN epilayer structure.
  • the high barrier of the p-GaN layer depletes the electron gas at the AlN/GaN interface under zero gate bias, and also increases the gate turn-on voltage. Furthermore, changing the aluminum (Al) composition and the thickness of the AlGaN layer controls the threshold voltage over a wide range.
  • the epilayer is AlGaN/ AlN/GaN. Without the high barrier of p-GaN, polarization fields in the AlGaN and AlN layers allow a charge sheet to form at the AlN/GaN interface, thus leading to low on- resistance.
  • the on-resistance is further reduced due to increased mobility of the 2DEG charge at the AlN/GaN interface compared to the mobility of 2DEGs at AlGaN/GaN interfaces.
  • the AlN layer is required to maintain low on-resistance especially when high threshold voltage is desired. Because threshold voltage can be controlled over a wide range while maintaining low on-resistance, this device can be used as a normally-off, or enhancement mode FET, for different applications.
  • the present invention discloses a method for fabricating a field effect transistor, comprising using a III -nitride barrier layer to control a threshold voltage of a gate of the transistor and confine a two dimensional electron gas (2DEG) to a channel layer of the transistor; and using a polarization induced electric field of a III- nitride interlayer between the 2DEG and the Ill-nitride barrier layer to induce a larger 2DEG charge density as compared to without the III -nitride interlayer, thereby reducing an on-resistance of the transistor and controlling the on-resistance independently of the threshold voltage.
  • a III -nitride barrier layer to control a threshold voltage of a gate of the transistor and confine a two dimensional electron gas (2DEG) to a channel layer of the transistor
  • 2DEG two dimensional electron gas
  • the method may further comprise selecting a thickness and material composition of the Ill-nitride barrier layer to obtain a desired threshold voltage of the transistor, wherein the thickness of the Ill-nitride barrier layer does not substantially decrease the on-resistance of the transistor.
  • the Ill-nitride barrier layer may be AlGaN, and the material composition may be Al content, and the transistor may be an enhancement mode High Electron Mobility Transistor (HEMT) .
  • HEMT High Electron Mobility Transistor
  • the thickness and material composition may be selected to obtain a threshold voltage of IV or greater.
  • the obtained threshold voltage may be at least IV and the on-resistance may correspond to a charge density in the 2DEG in excess of 7 x 10 12 cm "2 or allow a current density in the 2DEG in excess of 0.3 A/mm.
  • the thickness and composition may be selected to maximize the threshold voltage.
  • the method may further comprise using a thickness of p-III -nitride cap layer between the gate and the III -nitride barrier layer to increase a gate turn-on of the transistor's gate, wherein the p-III -nitride layer depletes the 2DEG under the gate at zero gate bias.
  • the gate turn-on may be at least 3 V.
  • the method may further comprise removing the p-III-nitride cap layer from in and under contact regions and access regions of the transistor, wherein the thickness of the Ill-nitride barrier layer is smaller than a thickness of the Ill-nitride barrier layer in a transistor without the Ill-nitride barrier layer.
  • the transistor may be an enhancement mode HEMT, wherein the Ill-nitride barrier layer is AlGaN and the p- Ill-nitride layer is p-GaN.
  • the present invention further discloses a nitride based enhancement mode High Electron Mobility Transistor (HEMT), comprising a Ill-nitride channel layer having a channel potential energy for containing a two dimensional electron gas (2DEG), wherein the 2DEG has a resistance; a Ill-nitride barrier layer positioned for, and having a barrier potential energy for, confining the 2DEG in the channel layer, wherein a polarization coefficient of the barrier layer is larger than a polarization coefficient of the channel layer; a III -nitride interlay er between the barrier layer and the channel layer, wherein the Ill-nitride interlayer has a polarization coefficient higher than the polarization coefficient of the barrier layer; a source for supplying a current to the 2DEG; a drain for supplying an output current, wherein the current flows from the source, through the 2DEG and then to the drain to produce the output current; a gate for controlling the current's flow through the 2DEG; and
  • the HEMT may further comprise a thickness and material composition of the Ill-nitride barrier layer, wherein the thickness and the material composition is selected to obtain a desired threshold voltage of the HEMT.
  • the HEMT may further comprise a thickness of the p-type Ill-nitride layer, wherein the thickness of the p-type III- nitride layer is selected to obtain a turn-on voltage of the gate of 3 V or greater.
  • the thickness of the Ill-nitride barrier layer may not substantially reduce an on-resistance of the HEMT or resistance of the 2DEG.
  • the thickness and the material composition of the Ill-nitride barrier may be selected to obtain the threshold voltage of at least IV and a charge density of the 2DEG in excess of 7 x 10 12 cm “2 or a current density in the 2DEG is in excess of 0.3 A/mm.
  • the HEMT may further comprise a first access region between the source and the gate and a second access region between the drain and the gate, wherein the p-type III -nitride layer is not present under the source, drain, first access region and second access region; and the thickness of the Ill-nitride barrier layer which is smaller than a thickness of the Ill-nitride barrier layer in a HEMT without the Ill-nitride interlayer.
  • the Ill-nitride barrier layer may be AlGaN, the material composition may be an Al content, and the Ill-nitride interlayer may be AlN.
  • a thickness of the AlN may be thin enough such that the AlN is not relaxed but is strained, due to a lattice mismatch with the barrier layer and the channel layer, or the thickness of the AlN may be less than 20 nm.
  • the III -nitride interlayer may interface the III -nitride barrier layer and the Ill-nitride channel layer.
  • the channel layer may be GaN and the p-type III- nitride layer may be p-GaN.
  • Fig. l(a) shows a schematic of an enhancement mode device, and band diagrams of the enhancement mode device under the gate (Fig. l(b)) and under the access region and contact region (Fig. l(c)), wherein the two dimensional electron gas (2DEG) is depleted beneath the gate at zero bias.
  • 2DEG two dimensional electron gas
  • Fig. 2(a) shows a graph (calculation) of AlGaN thickness vs. threshold voltage
  • Fig. 2(b) shows a graph (calculation) of sheet charge vs. AlGaN thickness, for a p-GaN/ AlGaN/ AlN/GaN structure, wherein sheet charge density is high (approximately 7 to 8 x 10 12 cm "2 ) at an AlGaN thickness required for high threshold voltages.
  • Fig. 4 is a graph plotting the measured I DS as a function of V GS and plotting the measured transconductance (g m ) as a function of V D s-
  • Fig. 5 is a graph plotting gain as a function of frequency of V GS -
  • Fig. 7 is a graph plotting measured threshold voltage V TH as a function of AlGaN barrier thickness.
  • Fig. 8 is a graph plotting measured gate-source current I GS as a function of
  • Fig. 12(a) is a graph (calculation) of AlGaN thickness vs. threshold voltage
  • Fig. 12(b) is a graph (calculation) of sheet charge vs. AlGaN thickness for a p- GaN/AlGaN/GaN structure, wherein sheet charge density is very low (approximately 4 to 5 e 12 cm "2 ) at an AlGaN thickness required for high threshold voltages.
  • Fig. 13 shows a schematic of an enhancement mode device.
  • Fig. 15 is a graph plotting measured I G (gate leakage) as a function of V GS -
  • Fig. 17 is a graph plotting measured gain as a function of frequency of V GS -
  • Fig. 18 is a flowchart illustrating a method of the present invention.
  • Fig. 19 is a flowchart illustrating a method of the present invention.
  • the present invention comprises a device structure with a p-GaN cap layer and an AlN interlayer which does not have the drawbacks seen in the above mentioned devices.
  • the structure for this device 100 is shown in Fig. l(a).
  • the epilayer stack comprises (from top to bottom) p-GaN 104, Al x Gai_ x N 106 (with 0 ⁇ x ⁇ 1), AlN 108 and a GaN-buffer 110.
  • the high barrier of the p-GaN 104 layer fully depletes the electron gas 112 at the portion 114 of the interface 116 (between the AlN 108 and GaN-buffer 110) which is under the gate 102 (under zero gate bias, see Fig. l(a)), lowers gate leakage, and also increases the gate turn-on voltage (to at least 3 V).
  • changing the Al composition and the thickness of the AlGaN 106 layer controls the threshold voltage over a wide range.
  • 2DEG two dimensional electron gas
  • the epilayer is (from top to bottom) AlGaN 106, AlN 108 and GaN-buffer 110. Etching away the p- GaN 104 in these regions 118, 120,122 induces a high electron density 112 (up to at least 7 to 8 el2 cm "2 ) at the portions 124, 126 of the interface 116 (between the AlN 108 and the GaN-buffer 110) which are under the access region 118 and contact regions 120,122, due to polarization fields.
  • the 2DEG 112 under the gate 102 (not shown) is induced when the gate 102 is forward biased (not shown), while the charge 112 in the access regions 118 is always present (Fig. l(b)).
  • Fig. l(c) is a graph showing band diagram (showing Ec, Ey and Fermi level
  • Fig. l(c) illustrates a method of using a Ill-nitride interlayer 108 between the 2DEG 112 and the second barrier 106 to reduce an on resistance of the transistor 100.
  • a polarization induced potential barrier 108a (which is the potential energy Ec of the III -nitride interlayer 108) reduces overlap of the electron population 112a (and consequently the 2DEG) with the barrier 106, thereby reducing alloy scattering with the barrier layer 106, and/or increasing mobility of the charge 112 as compared to without the Ill-nitride layer 108.
  • the polarization induced electric field associated with the polarization induced potential barrier 108a induces a larger electron population 112a than would be possible without the AlN layer 108.
  • Fig. l(a) also illustrates the source to gate distance L SG 128, a gate length L G
  • Fig. 2(a) shows a graph (calculation) of AlGaN thickness vs. threshold voltage
  • Fig. 2(b) shows a graph (calculation) of sheet charge vs. AlGaN thickness, for the device structure of Fig. l(a), for Al contents of the AlGaN 106 of 5%, 10%, 15% and 20%, wherein sheet charge density is high (approximately 7 to 8 x 10 12 cm "2 ) at an AlGaN thickness required for high threshold voltages (e.g., an Al content of 20% and an AlGaN thickness of 10 nm.
  • the inset 200 shows the p-GaN 202/AlGaN 204/A1N 206/GaN 208 layer structure used to measure the data of Fig. 2(a), and inset 210 shows the AlGaN 204/A1N 206/GaN 208 layer structure used to measure the data of Fig. 2(b).
  • Fig. 2(a) shows how changing the Al composition and the thickness of the AlGaN 106 layer controls the threshold voltage over a wide range.
  • the threshold voltage in these devices 100 is not affected by processing since it is controlled by the epitaxial structure 104-110.
  • Fig. 4 shows peak g m ⁇ 250 mS/mm
  • Fig. 5 shows f t ⁇ 20 GHz and f MA x ⁇ 38 GHz
  • Fig. 6 shows a kink in pulsed IV curve, possibly due to traps at the p-GaN/AlGaN interface.
  • Fig. 7 is measured V TH as a function of thickness of the AlGaN layer 106, for one example of a device structure, grown by MOCVD, where the p-GaN layer 104 is 10 nm thick, the AlGaN layer 106 is 10 nm or 12 nm thick, and the AlN layer 108 is 0.6 nm thick.
  • Table 1 shows various parameters for the device of Fig. 5 as a function of AlGaN layer 106 thickness.
  • Fig. 12(a) is a graph (calculation) of AlGaN thickness vs. threshold voltage
  • Fig. 12(b) is a graph (calculation) of sheet charge vs. AlGaN thickness for a p- GaN/AlGaN/GaN structure
  • the inset 1200 shows the p-GaN 1202/AlGaN 1204/GaN 1206 layer structure used to measure the data of Fig. 12(a)
  • inset 1208 shows the AlGaN 1204/GaN 1206 layer structure used to measure the data of Fig.
  • the data is measured for Al contents of the AlGaN 1204 of 20%, 15%, 10% and 5%, wherein sheet charge density is very low (approximately 4 to 5 el2 cm "2 ) at an AlGaN thickness required for high threshold voltages (e.g., Al content 20% and AlGaN thickness of 10 nm).
  • FIG. 13 shows a HEMT or FET device 1300 fabricated on material grown by
  • RF plasma-assisted molecular beam epitaxy comprising a 2DEG 1302 confined in a GaN layer 1304 by an AlGaN layer 1306, and a p-GaN layer 1308 between the AlGaN layer 1306 and the gate 1310.
  • Si x Ny 1312 is deposited in the access regions 1314, 1316 between the gate 1310 and the source 1318 and between the gate 1310 and the drain 1320 (and partially on the source 1318 and drain 1320).
  • the Mg doping concentration in the 10 nm-thick p-GaN layer 1308 is approximately Ix 10 18 and the thickness of the Alo.22Gao.78N layer 1306 is 12 nm.
  • the p-GaN 1308 in the source 1318 and drain regions 1320 was etched away prior to ohmic metal deposition using a self-aligned dry etch while the p-GaN in the access regions 1314, 1316 was etched away using the ohmic contacts and the gate electrode as masks. Peak g of 160 mS/mm is reached at
  • the threshold voltage is ⁇ 0.5 V
  • maximum I DS ⁇ 300 mA/mm at
  • V GS 3V, as shown in Fig. 14.
  • the 3 V turn-on of the gate diode is approximately 1 V higher than standard Schottky gates as shown in Fig. 15.
  • the DC, 80 ⁇ s, and 200 ns-pulsed I-V output characteristics of the device 1300 are shown in Fig. 16.
  • the maximum output current of the device is the highest reported among p-GaN gated E-mode HEMTs.
  • the kink in the pulsed I-V (Fig. 16, which may be caused by traps in the p-GaN/ AlGaN interface, is currently underommeg b ation. Conseq ⁇ uently •", the device exhibits f T of 12 GHz and f max of 35 GHz which are lower than that of depletion-mode (D-mode) devices with similar dimensions (Fig. 17).
  • V can be achieved with much lower access resistance (Fig. 2(a) and Fig. 2(b)).
  • the present invention may develop a p-GaN/ AlGaN/ AlN/GaN E-mode HEMTs with a threshold voltage of at least 1 V and high current density, for example, a gate turn on voltage of at least 3 V, and a maximum output current in excess of 0.3 A/mm.
  • Fig. 18 is a flowchart illustrating a method for fabricating an E-mode field effect transistor 1800, such as a HEMT.
  • the method comprises one or more of the following steps:
  • Fig. 18(a) illustrates the step of depositing an AlN interlayer 1802 on a GaN layer 1804 (wherein the GaN 1804 is for containing a 2DEG 1804a), an AlGaN layer 1806 on the AlN layer 1802, and a p-GaN layer 1808 on the AlGaN layer 1806.
  • a thickness 1806a and material composition (e.g., Al content) of the Ill-nitride barrier layer 1806 may be selected to obtain a desired threshold voltage V TH of the HEMT, wherein the thickness 1806a does not substantially reduce an on-resistance of the HEMT or resistance of the 2DEG 1804a.
  • the thickness 1806a of the Ill-nitride barrier 1806 may be selected to obtain the threshold voltage of at least IV and a charge density of the 2DEG 1804a in excess of 7 x 10 12 cm "2 or a current density in the 2DEG 1804a is in excess of 0.3 A/mm.
  • a thickness 1808a of the p-type Ill-nitride layer 1808 may be selected to obtain a turn-on voltage of the gate G of 3 V or greater.
  • Fig. 18(b) illustrates the step of etching contact windows 1810, 1812 in the p- GaN 1808.
  • Fig. 18(c) illustrates the step of depositing source S and drain D contacts in the windows 1810, 1812 respectively, on the AlGaN 1806 and annealing the contacts S and D to form ohmic contacts S and D.
  • Fig. 18(d) illustrates the step of depositing a gate G on the p-GaN layer 1808.
  • Fig. 18(e) illustrates the step of etching the p-GaN 1808 in the access regions 1814, 1816 to achieve a device 1800.
  • Fig. 18(e) illustrates a nitride based E-mode HEMT or Field Effect Transistor (FET) 1800, comprising a Ill-nitride channel layer 1804 having a channel potential energy for containing a 2DEG 1804a; a Ill-nitride barrier layer 1806 positioned for, and having a barrier potential energy for, confining the 2DEG 1804a in the channel layer 1804, wherein a polarization coefficient of the barrier layer 1806 is larger than the polarization coefficient of the channel layer 1804; a Ill-nitride interlayer 1802 between the barrier layer 1806 and the channel layer 1804, wherein the Ill-nitride interlayer 1802 has a thickness 1802a and a polarization coefficient greater higher than a polarization coefficient of the channel layer 1804; a source
  • the HEMT may further comprise a first access region 1814 between the source S and the gate G and a second access region 1816 between the drain D and the gate G, wherein the p-type nitride layer 1808 is not present under the source S, drain D, first access region 1814 and second access region 1816.
  • the thickness 1806a of the Ill-nitride barrier layer 1806 may be smaller than a thickness 1806a of the III- nitride barrier layer 1806 in a HEMT without the Ill-nitride interlayer 1808.
  • the barrier layer 1806 may AlGaN and the interlayer 1802 may be AlN.
  • the thickness 1802a of the AlN layer 1802 may be thin enough such that the AlN is not relaxed but is strained, due to a lattice mismatch with the barrier layer 1806 and the channel layer 1804, for example, the thickness 1802a may be less than 20 nm.
  • the AlN interlayer 1802 may interface the barrier layer 1806 and the channel layer 1804.
  • Fig. 18(f) illustrates the step of depositing a SiN x passivation layer in the access regions 1814, 1816 and partially on the contacts S and D.
  • Block 1900 represents the step of using a thickness of a Ill-nitride barrier layer to control a threshold voltage of the transistor's gate and confine a 2DEG in a channel layer of the transistor.
  • the step may comprise selecting a thickness and material composition of the Ill-nitride barrier layer to obtain a desired threshold voltage of the transistor, wherein the thickness of the Ill-nitride barrier layer does not substantially decrease the on-resistance of the transistor, or substantially decrease the 2DEG resistance.
  • the Ill-nitride barrier layer may be AlGaN, and the material composition may be Al content, and the transistor may be an E-mode HEMT.
  • the thickness and material composition may be selected to obtain the threshold voltage of IV or greater, or maximize the threshold voltage.
  • the obtained threshold voltage may be at least IV and the on-resistance may correspond to a charge density in the 2DEG in excess of 7 x 10 12 cm "2 or allow a current density in the 2DEG in excess of 0.3 A/mm.
  • Block 1902 represents the step of using a polarization induced electric field of a Ill-nitride interlayer between the 2DEG and the III -nitride barrier layer to induce a larger 2DEG charge density as compared to without the III -nitride interlayer, thereby reducing an on-resistance of the transistor and controlling the on-resistance independently of the threshold voltage.
  • the thickness and composition of the III- nitride barrier layer may be selected to maximize the threshold voltage independently (or without affecting) the resistance or charge density of the 2DEG, or the on- resistance of the transistor.
  • the magnitude of the polarization induced electric field is proportional to the thickness of the Ill-nitride barrier layer, i.e. the polarization induced electric field increases as the thickness of the AlN layer increases.
  • Block 1904 represents the step of using a thickness of p-III-nitride cap layer between the gate and the III -nitride barrier layer to increase a gate turn-on of the transistor's gate, wherein the p-III-nitride layer depletes the 2DEG under the gate at zero gate bias.
  • the gate turn-on may be at least 3 V.
  • Block 1906 represents the step of removing the p-III-nitride cap layer from contact regions and access regions of the transistor, wherein the thickness of the III- nitride barrier layer is smaller than a thickness of the Ill-nitride barrier layer in a transistor without the Ill-nitride barrier layer.
  • Block 1908 represents the step of obtaining a transistor, for example, an enhancement mode HEMT, wherein the Ill-nitride barrier layer is AlGaN and the p- III-nitride layer is p-GaN.
  • Insertion of an insulator (any combination of Si ⁇ , Si ⁇ N ⁇ , Al ⁇ , and/or any other insulator, thickness ranging from 0.1 A to 5000 A) beneath the gate electrode 102 (and above the p-type layer 104) can further reduce gate leakage and increase the gate turn-on.
  • the p-GaN 104 and/or GaN-buffer 110 layer can be substituted by p-AlGalnN, and AlGaInN, respectively.
  • the p-GaN 104, AlGaN 106, and AlN 108 layers do not have to be abrupt, as they can be gradually graded (in terms of Al composition).
  • the on-resistance (or access resistance) can be further reduced by increasing the thickness of AlGaN 106 in the access regions 118 (by regrowth of AlGaN in the access region 118 or by selectively regrowing the p-GaN 104 below the gate after etching away some of the AlGaN below the gate).
  • the on-resistance can also be reduced by ion-implanting the access regions with donor species. These two methods can be used together or separately.
  • (Al,Ga,In)N, AlGaInN, and Ill-nitride refer to III- nitride compounds.
  • On resistance refers to the resistance of the entire device, and access resistance refers to the resistance of the access regions only.
  • the access region is between the contacts and the gate region. It extends on each side of the gate to the contacts.

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Abstract

L'invention concerne un transistor à mobilité d'électron élevée (HEMT) à mode d'amplification comprenant une couche de nitrure de type p entre la grille et un canal du HEMT, pour réduire une population d'électrons sous la grille. L'HEMT peut également comprendre une couche de nitrure d'aluminium (AlN) entre une couche de AlGaN et une couche tampon du HEMT pour réduire une résistance de marche d'un canal.
PCT/US2008/065543 2007-06-01 2008-06-02 Transistor à effet de champ à mode d'amplification p-gan/algan/aln/gan Ceased WO2008151138A1 (fr)

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US94158007P 2007-06-01 2007-06-01
US60/941,580 2007-06-01

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105428410A (zh) * 2015-11-20 2016-03-23 成都嘉石科技有限公司 具有2DEG恢复效应的GaN HEMT器件
WO2019086664A1 (fr) 2017-11-06 2019-05-09 Institut Fuer Mikroelektronik Stuttgart Composant à semi-conducteur doté d'une structure de transistor du type à enrichissement
WO2020180913A1 (fr) * 2019-03-06 2020-09-10 Texas Instruments Incorporated Transistor à base de nitrure de gallium (gan) ayant de multiples blocs de p-gan

Families Citing this family (114)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW200903805A (en) * 2007-05-24 2009-01-16 Univ California Polarization-induced barriers for N-face nitride-based electronics
JP2008306130A (ja) * 2007-06-11 2008-12-18 Sanken Electric Co Ltd 電界効果型半導体装置及びその製造方法
US8519438B2 (en) 2008-04-23 2013-08-27 Transphorm Inc. Enhancement mode III-N HEMTs
US7985986B2 (en) * 2008-07-31 2011-07-26 Cree, Inc. Normally-off semiconductor devices
JP4968747B2 (ja) * 2009-02-03 2012-07-04 シャープ株式会社 Ｉｉｉ−ｖ族化合物半導体素子
JP2010232279A (ja) * 2009-03-26 2010-10-14 Furukawa Electric Co Ltd:The 電界効果トランジスタ
TWI499054B (zh) * 2009-04-08 2015-09-01 Efficient Power Conversion Corp 補償式閘極金屬絕緣體半導體場效電晶體及其製造方法
DE112010001582T5 (de) * 2009-04-08 2012-08-02 Efficient Power Conversion Corporation Galliumnitrid-Transistor vom Anreicherungstyp mit verbessertern GATE-Eigenschaften
JP5562579B2 (ja) * 2009-05-12 2014-07-30 日本碍子株式会社 半導体素子用エピタキシャル基板の作製方法
US8742459B2 (en) * 2009-05-14 2014-06-03 Transphorm Inc. High voltage III-nitride semiconductor devices
JP2011029247A (ja) * 2009-07-22 2011-02-10 Panasonic Corp 窒化物半導体装置及びその製造方法
WO2011100304A1 (fr) 2010-02-09 2011-08-18 Massachusetts Institute Of Technology Transistors au nitrure normalement inactifs à double gâchette
US8344421B2 (en) 2010-05-11 2013-01-01 Iqe Rf, Llc Group III-nitride enhancement mode field effect devices and fabrication methods
TWI420664B (zh) * 2010-07-27 2013-12-21 Univ Nat Chiao Tung 增強式高電子移動率電晶體及其製造方法
KR101720589B1 (ko) * 2010-10-11 2017-03-30 삼성전자주식회사 이 모드(Ｅ-ｍｏｄｅ) 고 전자 이동도 트랜지스터 및 그 제조방법
WO2012054683A2 (fr) * 2010-10-21 2012-04-26 Carnegie Mellon University Capteurs chimiques à base de gaz électronique bidimensionnel (2deg)
KR102065115B1 (ko) * 2010-11-05 2020-01-13 삼성전자주식회사 Ｅ-모드를 갖는 고 전자 이동도 트랜지스터 및 그 제조방법
JP2012119429A (ja) * 2010-11-30 2012-06-21 Sanken Electric Co Ltd 半導体装置の製造方法、半導体装置
US8742460B2 (en) 2010-12-15 2014-06-03 Transphorm Inc. Transistors with isolation regions
US8643062B2 (en) 2011-02-02 2014-02-04 Transphorm Inc. III-N device structures and methods
US8772842B2 (en) 2011-03-04 2014-07-08 Transphorm, Inc. Semiconductor diodes with low reverse bias currents
US8716141B2 (en) 2011-03-04 2014-05-06 Transphorm Inc. Electrode configurations for semiconductor devices
US8536931B2 (en) 2011-06-17 2013-09-17 Rf Micro Devices, Inc. BI-FET cascode power switch
US8710511B2 (en) 2011-07-29 2014-04-29 Northrop Grumman Systems Corporation AIN buffer N-polar GaN HEMT profile
KR20130014861A (ko) * 2011-08-01 2013-02-12 삼성전자주식회사 고 전자 이동도 트랜지스터 및 그 제조방법
US8901604B2 (en) 2011-09-06 2014-12-02 Transphorm Inc. Semiconductor devices with guard rings
US9257547B2 (en) 2011-09-13 2016-02-09 Transphorm Inc. III-N device structures having a non-insulating substrate
JP5784440B2 (ja) * 2011-09-28 2015-09-24 トランスフォーム・ジャパン株式会社 半導体装置の製造方法及び半導体装置
KR101882997B1 (ko) 2011-09-30 2018-07-30 삼성전기주식회사 질화물 반도체 소자 및 그 제조방법
US8598937B2 (en) 2011-10-07 2013-12-03 Transphorm Inc. High power semiconductor electronic components with increased reliability
US8723226B2 (en) * 2011-11-22 2014-05-13 Texas Instruments Incorporated Manufacturable enhancement-mode group III-N HEMT with a reverse polarization cap
US8785944B2 (en) * 2011-12-07 2014-07-22 Samsung Electronics Co., Ltd. High electron mobility transistor
EP2602827B1 (fr) * 2011-12-09 2016-02-03 Imec Dispositif au nitrure du groupe III à mode d'enrichissement et son procédé de fabrication
CN103999216B (zh) 2011-12-19 2017-06-13 英特尔公司 用于集成有功率管理和射频电路的片上系统(soc)结构的iii族‑n晶体管
US9165766B2 (en) 2012-02-03 2015-10-20 Transphorm Inc. Buffer layer structures suited for III-nitride devices with foreign substrates
KR101920715B1 (ko) * 2012-03-06 2018-11-21 삼성전자주식회사 고 전자 이동도 트랜지스터 및 그 제조방법
JP6054620B2 (ja) * 2012-03-29 2016-12-27 トランスフォーム・ジャパン株式会社 化合物半導体装置及びその製造方法
WO2013155108A1 (fr) 2012-04-09 2013-10-17 Transphorm Inc. Transistors au nitrure-iii n-polaires
JP2013235873A (ja) * 2012-05-02 2013-11-21 Renesas Electronics Corp 半導体装置およびその製造方法
US9184275B2 (en) 2012-06-27 2015-11-10 Transphorm Inc. Semiconductor devices with integrated hole collectors
US8975664B2 (en) * 2012-06-27 2015-03-10 Triquint Semiconductor, Inc. Group III-nitride transistor using a regrown structure
TWI500157B (zh) * 2012-08-09 2015-09-11 Univ Nat Central 場效電晶體裝置及其製造方法
US9917080B2 (en) * 2012-08-24 2018-03-13 Qorvo US. Inc. Semiconductor device with electrical overstress (EOS) protection
JP2014072427A (ja) * 2012-09-28 2014-04-21 Fujitsu Ltd 半導体装置及び半導体装置の製造方法
WO2014127150A1 (fr) 2013-02-15 2014-08-21 Transphorm Inc. Électrodes pour dispositifs à semi-conducteurs et leurs procédés de fabrication
KR102055839B1 (ko) 2013-03-08 2019-12-13 삼성전자주식회사 질화계 반도체 소자
KR102036349B1 (ko) 2013-03-08 2019-10-24 삼성전자 주식회사 고 전자이동도 트랜지스터
US9087718B2 (en) 2013-03-13 2015-07-21 Transphorm Inc. Enhancement-mode III-nitride devices
US9018056B2 (en) * 2013-03-15 2015-04-28 The United States Of America, As Represented By The Secretary Of The Navy Complementary field effect transistors using gallium polar and nitrogen polar III-nitride material
US9245993B2 (en) 2013-03-15 2016-01-26 Transphorm Inc. Carbon doping semiconductor devices
US9443938B2 (en) 2013-07-19 2016-09-13 Transphorm Inc. III-nitride transistor including a p-type depleting layer
KR20150019723A (ko) 2013-08-14 2015-02-25 삼성전자주식회사 고전자이동도 트랜지스터와 그 제조방법 및 고전자이동도 트랜지스터를 포함하는 전자소자
US9048303B1 (en) 2014-01-30 2015-06-02 Infineon Technologies Austria Ag Group III-nitride-based enhancement mode transistor
US9337279B2 (en) 2014-03-03 2016-05-10 Infineon Technologies Austria Ag Group III-nitride-based enhancement mode transistor
CN103996706A (zh) * 2014-04-16 2014-08-20 中国科学院半导体研究所 氮化镓基晶体管及其制备方法
US9318593B2 (en) 2014-07-21 2016-04-19 Transphorm Inc. Forming enhancement mode III-nitride devices
US9536967B2 (en) 2014-12-16 2017-01-03 Transphorm Inc. Recessed ohmic contacts in a III-N device
US9536966B2 (en) 2014-12-16 2017-01-03 Transphorm Inc. Gate structures for III-N devices
KR101750158B1 (ko) * 2014-12-26 2017-06-22 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 Hemt-호환가능 측면 정류기 구조물
US10615158B2 (en) 2015-02-04 2020-04-07 Qorvo Us, Inc. Transition frequency multiplier semiconductor device
US10062684B2 (en) 2015-02-04 2018-08-28 Qorvo Us, Inc. Transition frequency multiplier semiconductor device
US9583607B2 (en) 2015-07-17 2017-02-28 Mitsubishi Electric Research Laboratories, Inc. Semiconductor device with multiple-functional barrier layer
US9876102B2 (en) 2015-07-17 2018-01-23 Mitsubishi Electric Research Laboratories, Inc. Semiconductor device with multiple carrier channels
US9871067B2 (en) * 2015-11-17 2018-01-16 Taiwan Semiconductor Manufacturing Co., Ltd. Infrared image sensor component
US11322599B2 (en) 2016-01-15 2022-05-03 Transphorm Technology, Inc. Enhancement mode III-nitride devices having an Al1-xSixO gate insulator
TWI813243B (zh) 2016-05-31 2023-08-21 美商創世舫科技有限公司 包含漸變空乏層的三族氮化物裝置
DE102017210711A1 (de) 2016-06-27 2017-12-28 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Halbleiterbauelement
US10804386B2 (en) * 2016-07-01 2020-10-13 Intel Corporation Gate stack design for GaN e-mode transistor performance
US10068976B2 (en) * 2016-07-21 2018-09-04 Taiwan Semiconductor Manufacturing Co., Ltd. Enhancement mode field-effect transistor with a gate dielectric layer recessed on a composite barrier layer for high static performance
WO2018063386A1 (fr) * 2016-09-30 2018-04-05 Intel Corporation Diodes connectées à un transistor et dispositifs iii-n connectés et leurs procédés de fabrication
RU2642495C1 (ru) * 2016-10-12 2018-01-25 Федеральное государственное бюджетное образовательное учреждение высшего образования "Томский государственный университет систем управления и радиоэлектроники" (ТУСУР) СПОСОБ УВЕЛИЧЕНИЯ ПОРОГОВОГО НАПРЯЖЕНИЯ ОТПИРАНИЯ GaN ТРАНЗИСТОРА
US10224426B2 (en) 2016-12-02 2019-03-05 Vishay-Siliconix High-electron-mobility transistor devices
US10381473B2 (en) 2016-12-02 2019-08-13 Vishay-Siliconix High-electron-mobility transistor with buried interconnect
US9780181B1 (en) 2016-12-07 2017-10-03 Mitsubishi Electric Research Laboratories, Inc. Semiconductor device with multi-function P-type diamond gate
US11670699B2 (en) 2016-12-15 2023-06-06 National Yang Ming Chiao Tung University Semiconductor device and method of manufacturing the same
TWI612662B (zh) 2017-01-09 2018-01-21 國立臺灣師範大學 半導體裝置及其製造方法
CN106935653A (zh) * 2017-04-21 2017-07-07 中航（重庆）微电子有限公司 一种氮化镓二次外延增强型电子器件及其制备方法
WO2018230136A1 (fr) * 2017-06-13 2018-12-20 パナソニックＩｐマネジメント株式会社 Dispositif à semi-conducteur au nitrure et son procédé de production
WO2019066914A1 (fr) * 2017-09-29 2019-04-04 Intel Corporation Transistors iii-n à jonction de polarisation en tunnel
TWI677092B (zh) 2017-12-20 2019-11-11 新唐科技股份有限公司 半導體裝置及半導體結構
US10355085B1 (en) 2017-12-28 2019-07-16 Nxp Usa, Inc. Semiconductor devices with regrown contacts and methods of fabrication
US10403718B2 (en) 2017-12-28 2019-09-03 Nxp Usa, Inc. Semiconductor devices with regrown contacts and methods of fabrication
TWI661554B (zh) * 2017-12-28 2019-06-01 新唐科技股份有限公司 增強型高電子遷移率電晶體元件及其形成方法
TWI644427B (zh) * 2018-01-02 2018-12-11 世界先進積體電路股份有限公司 高電子移動率電晶體
CN110034171B (zh) * 2018-01-11 2022-11-22 世界先进积体电路股份有限公司 高电子移动率晶体管
US10424659B1 (en) 2018-05-08 2019-09-24 Vanguard International Semiconductor Corporation High electron mobility transistor
US10833063B2 (en) 2018-07-25 2020-11-10 Vishay SIliconix, LLC High electron mobility transistor ESD protection structures
CN112753096B (zh) * 2018-09-30 2023-12-15 苏州晶湛半导体有限公司 一种半导体结构及其制造方法
WO2020062221A1 (fr) * 2018-09-30 2020-04-02 苏州晶湛半导体有限公司 Structure semi-conductrice et son procédé de fabrication
US11610971B2 (en) * 2018-12-17 2023-03-21 Intel Corporation Cap layer on a polarization layer to preserve channel sheet resistance
US11101378B2 (en) 2019-04-09 2021-08-24 Raytheon Company Semiconductor structure having both enhancement mode group III-N high electron mobility transistors and depletion mode group III-N high electron mobility transistors
WO2020215322A1 (fr) * 2019-04-26 2020-10-29 苏州晶湛半导体有限公司 Structure semi-conductrice et procédé de préparation associé
CN112310210A (zh) 2019-08-02 2021-02-02 联华电子股份有限公司 高电子迁移率晶体管
CN112447835B (zh) * 2019-08-30 2025-05-09 广东致能半导体有限公司 半导体器件及其制造方法
TWI846726B (zh) 2019-09-04 2024-07-01 聯華電子股份有限公司 增強型高電子遷移率電晶體
CN118039685A (zh) * 2019-10-09 2024-05-14 联华电子股份有限公司 高电子迁移率晶体管及其制作方法
CN112928161B (zh) * 2019-12-06 2024-01-02 联华电子股份有限公司 高电子迁移率晶体管及其制作方法
TWI775027B (zh) * 2019-12-20 2022-08-21 世界先進積體電路股份有限公司 半導體結構
US11545566B2 (en) 2019-12-26 2023-01-03 Raytheon Company Gallium nitride high electron mobility transistors (HEMTs) having reduced current collapse and power added efficiency enhancement
TWI769431B (zh) * 2020-01-22 2022-07-01 大陸商聚力成半導體(重慶)有限公司 增強型氮化鎵電晶體之結構與使用該結構之封裝晶片
CN111463273A (zh) * 2020-03-25 2020-07-28 西北工业大学 一种基于氮化镓异质结外延的长关型hemt器件及其制备方法
US11152364B1 (en) 2020-04-21 2021-10-19 Vanguard International Semiconductor Corporation Semiconductor structure and methods for manufacturing the same
WO2021217651A1 (fr) 2020-04-30 2021-11-04 Innoscience (suzhou) Semiconductor Co., Ltd. Dispositif à semi-conducteurs et son procédé de fabrication
US11362190B2 (en) 2020-05-22 2022-06-14 Raytheon Company Depletion mode high electron mobility field effect transistor (HEMT) semiconductor device having beryllium doped Schottky contact layers
CN111584628B (zh) * 2020-05-28 2021-03-26 浙江大学 增强型GaN HEMT器件及其制备方法
CN111682065B (zh) * 2020-06-19 2023-04-18 英诺赛科（珠海）科技有限公司 具有非对称栅极结构的半导体器件
CN112310212B (zh) * 2020-07-14 2025-06-03 中山市华南理工大学现代产业技术研究院 一种高线性GaN基毫米波器件及其制备方法
JP7543773B2 (ja) * 2020-08-25 2024-09-03 富士通株式会社 半導体装置及びその製造方法
CN114256343A (zh) 2020-09-24 2022-03-29 联华电子股份有限公司 高电子迁移率晶体管及其制作方法
US20220376041A1 (en) * 2021-04-12 2022-11-24 Innoscience (Suzhou) Technology Co., Ltd. Semiconductor device and method for manufacturing the same
CN117561608A (zh) * 2021-07-12 2024-02-13 美国亚德诺半导体公司 高电流和场管理的晶体管
US20230411507A1 (en) * 2022-06-15 2023-12-21 The Hong Kong University Of Science And Technology Normally-off p-gan gate double channel hemt and the manufacturing method thereof
US20240055488A1 (en) * 2022-08-11 2024-02-15 Texas Instruments Incorporated High band-gap devices with a doped high band-gap gate electrode extension
WO2025063660A1 (fr) * 2023-09-18 2025-03-27 주식회사 칩스케이 Transistor à semi-conducteur de puissance et son procédé de fabrication

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050077541A1 (en) * 2003-10-10 2005-04-14 The Regents Of The University Of California GaN/AIGaN/GaN dispersion-free high electron mobility transistors
US20060197109A1 (en) * 2005-03-03 2006-09-07 Saxler Adam W High electron mobility transistor
US20060214188A1 (en) * 2005-03-22 2006-09-28 Eudyna Devices Inc. Semiconductor device having GaN-based semiconductor layer

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050077541A1 (en) * 2003-10-10 2005-04-14 The Regents Of The University Of California GaN/AIGaN/GaN dispersion-free high electron mobility transistors
US20060197109A1 (en) * 2005-03-03 2006-09-07 Saxler Adam W High electron mobility transistor
US20060214188A1 (en) * 2005-03-22 2006-09-28 Eudyna Devices Inc. Semiconductor device having GaN-based semiconductor layer

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105428410A (zh) * 2015-11-20 2016-03-23 成都嘉石科技有限公司 具有2DEG恢复效应的GaN HEMT器件
CN105428410B (zh) * 2015-11-20 2018-03-02 成都海威华芯科技有限公司 具有2DEG恢复效应的GaN HEMT器件
WO2019086664A1 (fr) 2017-11-06 2019-05-09 Institut Fuer Mikroelektronik Stuttgart Composant à semi-conducteur doté d'une structure de transistor du type à enrichissement
DE102017125803A1 (de) 2017-11-06 2019-05-09 Institut Für Mikroelektronik Stuttgart Halbleiterbauelement mit einer Transistorstruktur vom Anreicherungstyp
US11257915B2 (en) 2017-11-06 2022-02-22 Institut Für Mikroelektronik Stuttgart Semiconductor element having an enhancement-type transistor structure
WO2020180913A1 (fr) * 2019-03-06 2020-09-10 Texas Instruments Incorporated Transistor à base de nitrure de gallium (gan) ayant de multiples blocs de p-gan
US11049960B2 (en) 2019-03-06 2021-06-29 Texas Instruments Incorporated Gallium nitride (GaN) based transistor with multiple p-GaN blocks
CN113519063A (zh) * 2019-03-06 2021-10-19 德克萨斯仪器股份有限公司 具有多个p-GaN块的氮化镓(GaN)基晶体管
US12046666B2 (en) 2019-03-06 2024-07-23 Texas Instruments Incorporated Gallium nitride (GaN) based transistor with multiple p-GaN blocks

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