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WO2008149348A3 - Method architecture circuit & system for providing caching - Google Patents

Method architecture circuit & system for providing caching Download PDF

Info

Publication number
WO2008149348A3
WO2008149348A3 PCT/IL2008/000750 IL2008000750W WO2008149348A3 WO 2008149348 A3 WO2008149348 A3 WO 2008149348A3 IL 2008000750 W IL2008000750 W IL 2008000750W WO 2008149348 A3 WO2008149348 A3 WO 2008149348A3
Authority
WO
WIPO (PCT)
Prior art keywords
caching
providing caching
architecture circuit
method architecture
present
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/IL2008/000750
Other languages
French (fr)
Other versions
WO2008149348A2 (en
Inventor
Yoav Etsion
Dror Feitelson
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Yissum Research Development Co of Hebrew University of Jerusalem
Original Assignee
Yissum Research Development Co of Hebrew University of Jerusalem
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Yissum Research Development Co of Hebrew University of Jerusalem filed Critical Yissum Research Development Co of Hebrew University of Jerusalem
Publication of WO2008149348A2 publication Critical patent/WO2008149348A2/en
Anticipated expiration legal-status Critical
Publication of WO2008149348A3 publication Critical patent/WO2008149348A3/en
Ceased legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0893—Caches characterised by their organisation or structure
    • G06F12/0895—Caches characterised by their organisation or structure of parts of caches, e.g. directory or tag array

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)

Abstract

The present invention relates to methods, architectures, circuits and systems for providing caching. According to some embodiments of the present invention, there may be provided a first cache portion adapted to be operated according to a first caching algorithm, a second cache portion adapted to be operated according to a second caching algorithm; and cache control logic adapted to determining whether to insert data requested by a caching client into either the first or the second caching portions based on either a probabilistic insertion policy or based on a predefined sampling pattern.
PCT/IL2008/000750 2007-06-04 2008-06-03 Method architecture circuit & system for providing caching Ceased WO2008149348A2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US94177907P 2007-06-04 2007-06-04
US60/941,779 2007-06-04

Publications (2)

Publication Number Publication Date
WO2008149348A2 WO2008149348A2 (en) 2008-12-11
WO2008149348A3 true WO2008149348A3 (en) 2010-02-25

Family

ID=40094274

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/IL2008/000750 Ceased WO2008149348A2 (en) 2007-06-04 2008-06-03 Method architecture circuit & system for providing caching

Country Status (1)

Country Link
WO (1) WO2008149348A2 (en)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8897766B2 (en) 2013-02-19 2014-11-25 International Business Machines Corporation System of edge byte caching for cellular networks
US10915453B2 (en) * 2016-12-29 2021-02-09 Intel Corporation Multi level system memory having different caching structures and memory controller that supports concurrent look-up into the different caching structures
US11416405B1 (en) 2020-02-07 2022-08-16 Marvell Asia Pte Ltd System and method for mapping memory addresses to locations in set-associative caches
US11422935B2 (en) * 2020-06-26 2022-08-23 Advanced Micro Devices, Inc. Direct mapping mode for associative cache
US11836053B2 (en) 2021-09-27 2023-12-05 Hewlett Packard Enterprise Development Lp Resource allocation for synthetic backups

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6349365B1 (en) * 1999-10-08 2002-02-19 Advanced Micro Devices, Inc. User-prioritized cache replacement
US20060015686A1 (en) * 2004-07-14 2006-01-19 Silicon Optix Inc. Cache memory management system and method
US20060236020A1 (en) * 2003-03-11 2006-10-19 Taylor Michael D Cache memory architecture and associated microprocessor and system controller designs

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6349365B1 (en) * 1999-10-08 2002-02-19 Advanced Micro Devices, Inc. User-prioritized cache replacement
US20060236020A1 (en) * 2003-03-11 2006-10-19 Taylor Michael D Cache memory architecture and associated microprocessor and system controller designs
US20060015686A1 (en) * 2004-07-14 2006-01-19 Silicon Optix Inc. Cache memory management system and method

Also Published As

Publication number Publication date
WO2008149348A2 (en) 2008-12-11

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