WO2008145060A1 - Development verification apparatus for universal chip - Google Patents

Abstract

A developing verification apparatus for universal chip, which comprises an object design module for storing and performing the object code of the chip to be development verified, a control processing module for performing the control processing program etc. of the user of the apparatus, a power management module for managing the power and charging the battery, and an extended function module for implementing developing functions in various fields.

Description

 Development and verification device for general-purpose chip

 The utility model relates to a universal chip development and verification device, in particular to a universal, high-speed, flexible and expandable integrated circuit chip development and verification platform, belonging to the field of chip design technology. Background technique

 The usual practice of chip design and development is to complete the initial target design on the field programmable gate array, and fully verify, test, and modify until the various performances meet the design requirements, and then convert to the ASIC. The production of ASICs is expensive, so it must be fully verified in the field of programmable gate arrays to eliminate all possible problems before entering the ASIC stage. Therefore, it is necessary to have a stable and reliable, powerful field programmable gate array development and verification device to support the target design, and ensure that the work of design, verification and system testing can be carried out smoothly. This is also the case with the design of various intellectual property cores, as well as the design of on-chip system-on-chips.

 The basic structure of the traditional development and verification device is a programmable gate array and peripheral circuits, a simple power supply control circuit, and external interfaces are all on one motherboard, and externally, some relatively simple functional blocks can be expanded. see picture 1.

 This structure is relatively simple. The functional structure is single and cannot be changed. For different complexity designs, many different types of development and verification platforms are required.

 At the same time, users may have the following requirements at design time:

 1. The design scale of different target chips is definitely different. From the perspective of saving R&D costs, the scale of field programmable gate arrays used should be optional.

2. The user needs to develop a verification platform in addition to a field programmable gate array with suitable capacity. It is also necessary to have an external device suitable for your own use for auxiliary design.

 3. For the intellectual property core or system-on-chip design that needs to work together, due to the uncertainty of external working conditions, a large number of expansion interfaces are needed, so that users can design expansion boards according to their own needs to meet various needs.

 4. The ability to develop the verification platform itself as an embedded system is always limited, and the resources are not rich enough. In order to obtain more resources, it must be able to connect to the computer, so that it can utilize the rich resources of the computer, so that both testing and verification are Very beneficial. At the same time, the connection speed should be fast enough to meet real-time requirements. Utility model content

 The purpose of the utility model is to provide a general-purpose chip development and verification device, which uses a cascading structure connected by a universal interface to provide users with more flexible matching during the development process, so that different users can select the development system that is most suitable for them. The purpose of saving research and development costs.

 The development and verification device of the universal chip proposed by the utility model comprises:

 (1) a target design module for storing and running the target code of the verification chip to be developed, and the target design module is respectively connected to the control processing module and the extended function module through a universal interface;

(2) a control processing module for operating a control program of the user of the device, establishing a data channel between the target design module and a computer that controls the verification process and displays the verification signal,

(3) A power management module that provides power to the device;

 (4) an extended function module, configured to establish a data channel between the target design module and the external test device;

 (5) A computer, a control processing program for inputting the user of the device, and a verification signal of the display device. The computer is connected to the control processing module through a serial port, and is connected to the target design module through a universal serial data bus interface.

The target design module in the above development and verification device includes: (1) A field programmable gate array for operating the target code of the verification chip to be developed;

(2) a configuration memory for storing the target code of the verification chip to be developed, and the configuration memory is connected to the field programmable gate array;

 (3) Universal serial data bus interface, used for data between the computer and the target design module it l;

 (4) A clock for generating a clock signal required for the operation of the target code, the clock being connected to the field programmable gate array;

 (5) Universal interface for signal connection between the target design module and other functional modules.

 The control processing module in the above development and verification device includes:

 (1) a microprocessor, a control processing program for operating the user of the device, controlling data communication with the computer, and the microprocessor is connected to the computer through the serial port;

 (2) The serial port is used to realize the communication connection between the microprocessor and the computer, and the serial port is connected with the microprocessor and the computer.

 (3) General purpose interface, used to control the signal connection between the processing module and other functional modules.

 The power management module in the above development and verification device includes:

 (1) Step-down DC switching power converter for outputting a voltage lower than the lowest voltage of the battery to supply power to the field programmable gate array core;

 (2) Step-up DC switching power converter for outputting a voltage higher than the highest voltage value of the battery to supply power to each peripheral circuit;

 (3) Step-up step-down DC switching power converter for outputting the voltage at the lowest voltage and the highest voltage of the battery, providing power for the field programmable gate interface and the microprocessor;

 (4) A battery charging circuit for charging a lithium battery;

 (5) Lithium battery for powering the unit.

 The extended function module in the above development and verification device includes:

(1) Analog-to-digital, digital-to-analog conversion circuit, analog signal and target for RF transmitting and receiving circuits The signal conversion between the digital signals of the standard design module, the analog-to-digital, digital-to-analog conversion circuit is connected to the RF transmitting and receiving circuit and the target design module;

 (2) RF transmitting and receiving circuits are used for transmitting and receiving wireless test signals. The test signals generated by the target code are digital-analog converted and sent to the RF transmitting circuit, and modulated to emit RF signals; The received RF signals are demodulated. The data is then sent to the target design module via an analog to digital converter;

 (3) Universal interface for extending the signal connection between the function module and other function modules.

 The universal chip development and verification device proposed by the utility model has the following advantages:

 1, scalability. The target design module and the control processing module respectively perform modular integration of the field programmable gate array and the circuit around the microprocessor, and the capacity of the field programmable gate array module can be adjusted according to design requirements, and the replaceable extended function module is Complete chip design, evaluation, and test tasks of varying complexity.

 2, versatility. The target design module, the control processing module, the collaborative chip design, evaluation, test tasks, the development needs of different functions, the use of different extended function modules, the basic platform unchanged, and achieve versatility.

 3. Achieve target design and computer high-speed data exchange. The universal serial data bus interface establishes a high-speed data channel with the computer, through which a large amount of user work can be done on the computer for rapid prototyping. When the design is completed, the computer can generate a test excitation signal to facilitate the verification of the design work.

 4. Powerful power management features. Powered by a lithium battery, a wide range of battery inputs maximizes battery efficiency and can be powered directly from the power supply to meet a variety of operating environments. DRAWINGS

 1 is a structural block diagram of an existing chip development and verification apparatus;

 2 is a structural block diagram of a general-purpose chip development and verification device designed by the present invention;

Figure 3 is a circuit block diagram of a target design module used in the verification apparatus; Figure 4 is a circuit block diagram of a control processing module used in the verification apparatus;

 Figure 5 is a circuit block diagram of a power management module used in the verification device;

 Figure 6 is a schematic diagram of an extended function module in the verification device. detailed description

 The development and verification device of the universal chip proposed by the utility model has a block diagram as shown in FIG. 2, comprising: a target design module for storing and running the target code of the verification chip to be developed; and a control processing module for operating the device user The control processing program establishes a data channel between the target design module and the computer that controls the verification process and displays the verification signal, and generates an excitation signal for causing the target code to operate; the power management module provides power for the device; and the extended function module uses And establishing a data channel between the target design module and the external test device; the computer, the control processing program for inputting the user of the device, and the verification signal of the display device.

The target design module in the above development and verification device has a circuit block diagram as shown in FIG. 3, comprising: a field programmable gate array for running the target code of the verification chip to be developed; and a configuration memory for storing the verification chip to be developed The target code, the configuration memory is connected to the field programmable gate array; the universal serial data bus interface is used for data communication between the computer and the target design module; the clock is used to generate the clock signal required for the target code to run, the clock and The field programmable gate array is connected; the universal interface is used for signal connection between the target design module and other functional modules. In one embodiment of the present invention, the target design module centered on the field programmable gate array, the field programmable gate array and the auxiliary circuit portion include: XILINX Spartenlll series field programmable gate array, field programmable gate array Choose a capacity of 200,000 doors - 1 million doors. Used to implement the user's design. Users can choose the appropriate field programmable gate array according to the scale of their own design, which is conducive to saving development costs. (If a larger field-programmable gate array is required, a higher level of target design module can be used without the need to modify other functional modules to achieve maximum cost savings). One piece of configuration memory (1M/2M/4M), model XCF01S/XCF02S/XCF04S, for configuring field programmable gate arrays. 1 global clock input for field programmable gate array The clock required for the job. General purpose interface. Used for signal connection with other function modules to complete data exchange.

 The control processing module in the above development and verification device has a circuit block diagram as shown in FIG. 4, comprising: a microprocessor, a control processing program for running the device user, controlling data communication with the computer, and the microprocessor passes through the serial port. Connected to the computer; serial port, used to realize the communication connection between the microprocessor and the computer, the serial port is connected with the microprocessor and the computer; the universal interface is used to control the signal connection between the processing module and other functional modules. In one embodiment of the invention, the microprocessor and associated circuitry include a microprocessor using a C8051F120 processor, and the control program is run there. The microprocessor is connected to the field programmable gate array in the target design module through a universal interface, real-time software and system simulation can be realized, and the field programmable gate array output data can be received by sending test data to the field programmable gate array. The device can be used as a simple external simulation and evaluation platform, playing an important role in accelerating the design process and testing the user's design. The simulation and evaluation capabilities of the microprocessor are not enough. Users can connect to the computer through the serial port and use the high-speed computing power of the computer to meet the design and test requirements. Moreover, because computers are often the most familiar development platforms for software developers, they can reduce staff training time and speed up the design process. 1 serial port. Communicate with the computer through the serial port. The serial port driver chip used is SP3232. The universal interface is used for signal connection with other functional modules to complete data exchange.

The power management module in the above development and verification device has a circuit block diagram as shown in FIG. 5, and includes: a step-down DC switching power converter for outputting a voltage lower than the lowest voltage of the battery, and providing the field programmable gate array core. Power supply; a step-up DC switching power converter for outputting a voltage higher than the highest voltage of the battery to supply power to each part of the peripheral circuit; a step-up step-down DC switching power converter for outputting the lowest voltage of the battery The highest voltage value provides power to the field programmable gate interface and microprocessor; the battery charging circuit is used to charge the lithium battery; and the lithium battery is used to supply power to the device. In an embodiment of the present invention, the power management module and the auxiliary circuit include: a step-down DC switching power conversion circuit for outputting low The voltage at the lowest voltage of the battery provides power to the field-programmable gate array core. The chip used is the TPS62040 chip from Texas Instruments. The step-up DC switching power supply conversion circuit is used to output a voltage higher than the highest voltage of the battery, and provides power for each part of the peripheral circuit. The chip is a TPS61032 chip of Texas Instruments. The step-up step-down DC switching power supply conversion circuit is used to output the voltage at the lowest voltage and the highest voltage of the battery, and provides power for the field programmable gate interface and the microprocessor. The chip is the TPS63000 chip of Texas Instruments. . A battery charging circuit that charges a single-cell Li-Ion/Li-Polymer battery. The chip is a Texas Instruments BQ24001 chip that provides power to the unit.

The circuit diagram of the extended function circuit module in the above development and verification device is shown in FIG. 6, and includes: an analog-to-digital, digital-to-analog conversion circuit, and a signal between the analog signal of the RF transmitting and receiving circuit and the digital signal of the target design module. Conversion, connected to the RF transmitting and receiving circuit and the target design module; RF transmitting and receiving circuit, used for transmitting and receiving the wireless test signal, the test signal generated by the target code is digital-analog converted and sent to the RF transmitting circuit, and modulated and transmitted The RF signal is received; the received RF signal is demodulated and sent to the target design module through an analog-to-digital converter; a universal interface is used to extend the signal connection between the function module and other functional modules. Analog-to-digital, digital-to-analog conversion circuit, signal conversion between the analog signal of the RF transmitting and receiving circuits and the digital signal of the target design module, and the analog-to-digital converter converts the analog signal of the RF circuit into a field programmable ί 1 array The digital signal is sent to the target design module. The chip uses the AD9201 chip of Analog Devices. The digital-to-analog converter converts the digital signal sent by the target design module into an analog signal recognizable by the RF circuit. The chip uses the AD9761 chip of Analog Devices. The RF transmitting and receiving circuit is used for transmitting and receiving the wireless test signal. The test signal generated by the target code is digital-analog converted and sent to the RF transmitting circuit. After modulation, the RF signal is transmitted. The transmitting modulation chip uses the AD8349 chip of Analog Devices. The received RF signal is demodulated and sent to the target design module through an analog-to-digital converter. The receiving demodulator chip uses the AD8347 chip of Analog Devices; the universal interface. Used for signal connection with other function modules to complete data exchange. The verification device adopts a cascading structure, and each part of the functional modules exist independently, and the functions can be realized in any combination, and the expansion modules of different functions can be used to meet the design requirements.

 Since the target design of the user is various, the method of developing the verification and the resources used are different, and one or several parts of the development verification apparatus may be used, so the example cannot be completed here, and the use of the development apparatus is explained.

 Establishment of working environment: In order to complete the wireless transmission and reception of data, extended function modules are designed: digital/analog, analog/digital conversion circuit, RF transmitting/receiving circuit, and target design module, control processing module and power management module to form wireless Transceiver system.

 Run the designed data transceiver display and control program on the computer side. The control program is run on the microprocessor of the control processing module, and the field programmable gate array in the target design module implements the target code of the wireless transceiver - the intellectual property core.

 The following describes the working process of this device:

 Data transmission process:

 1. The computer sends the excitation signal of the target code to the microprocessor in the control processing module through the serial port.

 2. After the microprocessor receives the excitation signal for the action of the target code, the excitation signal is processed by the control processing program and sent to the field programmable gate array in the target design module through the universal interface.

 3. The target code in the field programmable gate array processes the received excitation signal accordingly, and transmits the wireless test signal through digital-to-analog conversion and RF transmission.

 Data receiving process:

 1. The wireless test signal is received by the RF, analog-to-digital conversion, and sent to the target code in the field programmable gate array. The target code processes the received test signal for corresponding data, and sends the verification signal to the control processing module through the universal interface. In the microprocessor.

2. After receiving the verification signal, the microprocessor transmits it to the computer through the serial port. 3. After the computer receives the verification signal, it is processed and displayed.

 This development verification device supports the development phase:

 The user's final design goal is the object code within the field programmable gate array. This code is a link in the data stream. This link may be relatively simple or complex.

 This development verification device supports the verification phase:

 Verification of the target design requires the application of a large number of test stimulus signals. In traditional development verification structures, it is often necessary to implement a test stimulus signal in a field programmable gate array using a hardware description language. In this development verification device, this method can also be employed. At the same time, another option is provided to generate a test excitation signal from a computer, transmit it to the microprocessor through the serial port, and then apply a test excitation signal to the field programmable gate array by microprocessing. This method is more flexible than the traditional method of applying the stimulus, and the user can change the test excitation signal at any time without changing the target design, thereby completing the verification process quickly.

Claims

Claim  A development and verification device for a general-purpose chip, characterized in that the device comprises:  (1) a target design module for storing and running the target code of the verification chip to be developed, and the target design module is respectively connected to the control processing module and the extended function module through a universal interface; (2) a control processing module for operating a control program of the user of the device, establishing a data channel between the target design module and a computer that controls the verification process and displays the verification signal, (3) A power management module that provides power to the device;  (4) an extended function module, configured to establish a data channel between the target design module and the external test device;  (5) Computer, a control processing program for the input device user, a verification signal of the display device, the computer is connected to the control processing module through the serial port, and is connected to the target design module through the universal serial data bus interface.  2. The development verification apparatus according to claim 1, wherein said target design module comprises:  (1) A field programmable gate array for operating the target code of the verification chip to be developed; (2) a configuration memory for storing the target code of the verification chip to be developed, and the configuration memory is connected to the field programmable gate array;  (3) Universal serial data bus interface for data communication between the computer and the target design module;  (4) A clock for generating a clock signal required for the operation of the target code, the clock being connected to the field programmable gate array;  (5) Universal interface for signal connection between the target design module and other functional modules. 3. The development verification device of claim 1, wherein the control processing module comprises: (1) a microprocessor, a control processing program for operating the user of the device, controlling data communication with the computer, and the microprocessor is connected to the computer through the serial port;  (2) The serial port is used to realize the communication connection between the microprocessor and the computer, and the serial port is connected with the microprocessor and the computer.  (3) General purpose interface, used to control the signal connection between the processing module and other functional modules.  4. The development verification device of claim 1, wherein the power management module comprises:  (1) Step-down DC switching power converter for outputting a voltage lower than the lowest voltage of the battery to supply power to the field programmable gate array core;  (2) Step-up DC switching power converter for outputting a voltage higher than the highest voltage value of the battery to supply power to each peripheral circuit;  (3) Step-up step-down DC switching power converter for outputting the voltage at the lowest voltage and the highest voltage of the battery, providing power for the field programmable gate interface and the microprocessor;  (4) A battery charging circuit for charging a lithium battery;  (5) Lithium battery for powering the unit.  5. The development verification apparatus according to claim 1, wherein said extended function module comprises:  (1) Analog-to-digital, digital-to-analog conversion circuit, signal conversion between the analog signal of the RF transmitting and receiving circuits and the digital signal of the target design module, and the analog-to-digital, digital-to-analog conversion circuit is connected to the RF transmitting and receiving circuit and the target design module ;  (2) Radio frequency transmitting and receiving circuits, used for transmitting and receiving wireless test signals, the test signals generated by the target code are digital-analog converted and sent to the radio frequency transmitting circuit, and modulated to emit radio frequency signals; the received radio frequency signals are demodulated The data is then sent to the target design module via an analog to digital converter;  (3) General purpose interface, used to extend the signal connection between the function module and other function modules.