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WO2008142732A1 - 半導体メモリ - Google Patents

半導体メモリ Download PDF

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Publication number
WO2008142732A1
WO2008142732A1 PCT/JP2007/000533 JP2007000533W WO2008142732A1 WO 2008142732 A1 WO2008142732 A1 WO 2008142732A1 JP 2007000533 W JP2007000533 W JP 2007000533W WO 2008142732 A1 WO2008142732 A1 WO 2008142732A1
Authority
WO
WIPO (PCT)
Prior art keywords
sense amplifier
read
memory cell
detection signal
timing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2007/000533
Other languages
English (en)
French (fr)
Inventor
Keizo Morita
Kenichi Nakabayashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Semiconductor Ltd
Original Assignee
Fujitsu Semiconductor Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Semiconductor Ltd filed Critical Fujitsu Semiconductor Ltd
Priority to EP07737189.6A priority Critical patent/EP2149884B1/en
Priority to CN2007800530218A priority patent/CN101675480B/zh
Priority to PCT/JP2007/000533 priority patent/WO2008142732A1/ja
Priority to KR1020097023865A priority patent/KR101071212B1/ko
Priority to JP2009515004A priority patent/JP5024374B2/ja
Publication of WO2008142732A1 publication Critical patent/WO2008142732A1/ja
Priority to US12/603,065 priority patent/US8064241B2/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/22—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G11C7/08—Control thereof
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G11C7/222—Clock generating, synchronizing or distributing circuits within memory device
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G11C7/227—Timing of memory operations based on dummy memory elements or replica circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Dram (AREA)
  • Static Random-Access Memory (AREA)

Abstract

　電圧検出回路は、一対のビット線の一方に読み出される電荷量が所定量に到達したときに、検出信号を出力する。タイミング生成回路のマスク回路は、センスアンプ活性化信号の出力を検出信号が出力されるまでマスクする。センスアンプは、センスアンプ活性化信号に同期してメモリセルからビット線に読み出されるデータの論理を判定する。センスアンプの動作は、所定量の電荷がメモリセルからビット線に読み出された後、すなわち、検出信号の出力後に開始される。このため、半導体メモリの製造条件の変動により、タイミング信号の出力タイミングが早くなった場合にも、メモリセルから読み出されるデータをセンスアンプに正しくラッチできる。この結果、半導体メモリの誤動作を防止できる。
PCT/JP2007/000533 2007-05-18 2007-05-18 半導体メモリ Ceased WO2008142732A1 (ja)

Priority Applications (6)

Application Number Priority Date Filing Date Title
EP07737189.6A EP2149884B1 (en) 2007-05-18 2007-05-18 Semiconductor memory
CN2007800530218A CN101675480B (zh) 2007-05-18 2007-05-18 半导体存储器
PCT/JP2007/000533 WO2008142732A1 (ja) 2007-05-18 2007-05-18 半導体メモリ
KR1020097023865A KR101071212B1 (ko) 2007-05-18 2007-05-18 반도체 메모리
JP2009515004A JP5024374B2 (ja) 2007-05-18 2007-05-18 半導体メモリ
US12/603,065 US8064241B2 (en) 2007-05-18 2009-10-21 Semiconductor memory including voltage detection circuit for generating sense amplifier signal

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2007/000533 WO2008142732A1 (ja) 2007-05-18 2007-05-18 半導体メモリ

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US12/603,065 Continuation US8064241B2 (en) 2007-05-18 2009-10-21 Semiconductor memory including voltage detection circuit for generating sense amplifier signal

Publications (1)

Publication Number Publication Date
WO2008142732A1 true WO2008142732A1 (ja) 2008-11-27

Family

ID=40031459

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2007/000533 Ceased WO2008142732A1 (ja) 2007-05-18 2007-05-18 半導体メモリ

Country Status (6)

Country Link
US (1) US8064241B2 (ja)
EP (1) EP2149884B1 (ja)
JP (1) JP5024374B2 (ja)
KR (1) KR101071212B1 (ja)
CN (1) CN101675480B (ja)
WO (1) WO2008142732A1 (ja)

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JP2021093233A (ja) * 2019-05-21 2021-06-17 富士通セミコンダクターメモリソリューション株式会社 半導体記憶装置及び半導体記憶装置の試験方法

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JP2011023076A (ja) * 2009-07-16 2011-02-03 Toshiba Corp 半導体記憶装置及びその制御方法
US20110235458A1 (en) * 2010-03-29 2011-09-29 Kabushiki Kaisha Toshiba Electric device
US8130580B1 (en) * 2010-09-03 2012-03-06 Atmel Corporation Low power sense amplifier for reading memory
US9042159B2 (en) 2012-10-15 2015-05-26 Marvell World Trade Ltd. Configuring resistive random access memory (RRAM) array for write operations
US9047945B2 (en) 2012-10-15 2015-06-02 Marvell World Trade Ltd. Systems and methods for reading resistive random access memory (RRAM) cells
US8885388B2 (en) 2012-10-24 2014-11-11 Marvell World Trade Ltd. Apparatus and method for reforming resistive memory cells
US9042162B2 (en) 2012-10-31 2015-05-26 Marvell World Trade Ltd. SRAM cells suitable for Fin field-effect transistor (FinFET) process
CN105190760B (zh) 2012-11-12 2018-04-24 马维尔国际贸易有限公司 在存储器系统中并行地使用具有nmos通过门和pmos通过门两者的sram单元
US9087579B1 (en) 2014-01-06 2015-07-21 Qualcomm Incorporated Sense amplifiers employing control circuitry for decoupling resistive memory sense inputs during state sensing to prevent current back injection, and related methods and systems
US9691462B2 (en) 2014-09-27 2017-06-27 Qualcomm Incorporated Latch offset cancelation for magnetoresistive random access memory
CN105279537A (zh) * 2015-11-18 2016-01-27 许继集团有限公司 变电站挂接地线检测系统和方法
US10083731B2 (en) * 2016-03-11 2018-09-25 Micron Technology, Inc Memory cell sensing with storage component isolation
US9704588B1 (en) * 2016-03-14 2017-07-11 Sandisk Technologies Llc Apparatus and method for preconditioning currents to reduce errors in sensing for non-volatile memory
CN106024069A (zh) * 2016-05-13 2016-10-12 上海华虹宏力半导体制造有限公司 存储器操作电压的侦测电路
US9941021B2 (en) * 2016-06-16 2018-04-10 Micron Technology, Inc. Plate defect mitigation techniques
US10403389B2 (en) 2016-06-16 2019-09-03 Micron Technology, Inc. Array plate short repair
US10418085B2 (en) * 2017-07-20 2019-09-17 Micron Technology, Inc. Memory plate segmentation to reduce operating power
CN108492847A (zh) * 2018-03-26 2018-09-04 湘潭大学 一种确定FeRAM敏感参数的方法及装置
US10573372B2 (en) 2018-05-31 2020-02-25 Micron Technology, Inc. Sensing operations in memory by comparing inputs in a sense amplifier
US10978130B1 (en) * 2020-03-25 2021-04-13 Micron Technology, Inc. Temperature-based access timing for a memory device
CN111785309B (zh) * 2020-07-01 2021-03-19 深圳市芯天下技术有限公司 非型闪存接口电路的实现方法、电路、存储介质和终端
US12237007B2 (en) 2021-07-09 2025-02-25 Stmicroelectronics International N.V. Selective bit line clamping control for an in-memory compute operation where simultaneous access is made to plural rows of a static random access memory (SRAM)
US12087356B2 (en) 2021-07-09 2024-09-10 Stmicroelectronics International N.V. Serial word line actuation with linked source voltage supply modulation for an in-memory compute operation where simultaneous access is made to plural rows of a static random access memory (SRAM)
US11984151B2 (en) 2021-07-09 2024-05-14 Stmicroelectronics International N.V. Adaptive bit line overdrive control for an in-memory compute operation where simultaneous access is made to plural rows of a static random access memory (SRAM)
US12176025B2 (en) 2021-07-09 2024-12-24 Stmicroelectronics International N.V. Adaptive body bias management for an in-memory compute operation where simultaneous access is made to plural rows of a static random access memory (SRAM)
US12354644B2 (en) 2021-07-09 2025-07-08 Stmicroelectronics International N.V. Adaptive word line underdrive control for an in-memory compute operation where simultaneous access is made to plural rows of a static random access memory (SRAM)
US11676649B2 (en) * 2021-07-22 2023-06-13 Micron Technology, Inc. Sense timing coordination for memory
US11869623B2 (en) * 2021-08-30 2024-01-09 Taiwan Semiconductor Manufacturing Company, Ltd. Latch type sense amplifier
CN114093398A (zh) * 2021-11-26 2022-02-25 无锡拍字节科技有限公司 一种铁电存储器的位线布局及铁电存储器

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JPH0750094A (ja) * 1993-08-05 1995-02-21 Nec Corp 半導体メモリ回路
JP2002260386A (ja) * 2000-12-26 2002-09-13 Toshiba Corp 半導体記憶回路
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JPH0750094A (ja) * 1993-08-05 1995-02-21 Nec Corp 半導体メモリ回路
JP2002260386A (ja) * 2000-12-26 2002-09-13 Toshiba Corp 半導体記憶回路
JP2005129151A (ja) * 2003-10-23 2005-05-19 Fujitsu Ltd 半導体記憶装置
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Non-Patent Citations (1)

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See also references of EP2149884A4 *

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2021093233A (ja) * 2019-05-21 2021-06-17 富士通セミコンダクターメモリソリューション株式会社 半導体記憶装置及び半導体記憶装置の試験方法
JP7417099B2 (ja) 2019-05-21 2024-01-18 富士通セミコンダクターメモリソリューション株式会社 半導体記憶装置及び半導体記憶装置の試験方法

Also Published As

Publication number Publication date
US20100039851A1 (en) 2010-02-18
KR101071212B1 (ko) 2011-10-10
CN101675480B (zh) 2013-01-23
JP5024374B2 (ja) 2012-09-12
US8064241B2 (en) 2011-11-22
EP2149884B1 (en) 2013-06-19
EP2149884A1 (en) 2010-02-03
CN101675480A (zh) 2010-03-17
KR20100005130A (ko) 2010-01-13
EP2149884A4 (en) 2011-07-27
JPWO2008142732A1 (ja) 2010-08-05

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