WO2008035392A1 - Semiconductor integrated circuit device - Google Patents

Abstract

If the phase change element in a memory cell formed at the intersection of, for example, a word line (WL0) and a bit line (BL0) is to be reset so as to drive the phase change element into an amorphous state, it is arranged that the rise and fall times (trb,tfb) of the bit line (BL0) be longer than the rise and fall times (trw,tfw) of the word line (WL0). The quenching of the phase change element required for that resetting is performed by use of the fall time (tfw) of the word line (WL0). In this way, a disturb current (IBL01) for the phase change element in an unselected memory cell formed at the intersection of the bit line (BL0) and a word line (WL1) can be reduced, thereby improving the reliability of the phase change memory.

Description

 Specification

 Semiconductor integrated circuit device

 Technical field

 TECHNICAL FIELD [0001] The present invention relates to a semiconductor integrated circuit device, and more particularly, a memory cell that discriminates stored information using a difference in resistance value, for example, a high-density integrated memory circuit including a memory cell using a phase change material The present invention relates to a technology effective when applied to a logic-embedded memory in which a memory circuit and a logic circuit are provided on the same semiconductor substrate, or a semiconductor integrated circuit device having an analog circuit.

 Background art

 [0002] The non-volatile memory market has been growing significantly, driven by demand for mopile equipment such as mobile phones. A typical example is FLASH memory. Because of its inherently low speed, it is used as a programmable ROM. On the other hand, high-speed RAM is required as work memory, and both FLASH and DRAM memory are installed in portable devices. If an element with these two memory features can be realized, it would be possible to integrate all the semiconductor memory by force if it is possible to integrate FLASH and DRAM on a single chip. Very big!

 [0003] One of candidates for realizing the element is a nonvolatile memory using a phase change film. Phase change memory is sometimes called PRAM (Phase change RAM) or OUM (Ovonic Unified Memory). As already known, phase change memory cells use materials that can be reversibly switched from one phase to another. These phase states can be read out depending on the difference in electrical characteristics. For example, these materials can change between a disordered phase in the amorphous state and an ordered phase in the crystalline state. In the amorphous state, information can be stored by utilizing this difference in electrical resistance, which is higher in electrical resistance than in the crystalline state. A suitable material for the phase change memory cell is an alloy containing at least one element of sulfur, selenium, and tellurium called chalcogenide. Currently, the most promising chalcogenide is an alloy of germanium, antimony and tellurium (Ge Sb Te), which has already been rewritten

 2 2 5

Widely used in information storage units in possible optical disks. [0004] As described above, information is stored using the difference in phase state of chalcogenide. The phase change is obtained by locally raising the temperature of the chalcogenide. Below 70 ° C or below 130 ° C, both phases are stable and information is retained. The 10-year data retention temperature for chalcogenides is generally 70-130 ° C, depending on the composition. Holding for 10 years above this temperature causes a phase change from the amorphous state to the thermodynamically stable crystalline state. When chalcogenide is held at a crystallization temperature of 200 ° C or higher for a sufficient period of time, the phase changes and becomes a crystalline state. The crystallization time depends on the chalcogenide composition and the temperature at which it is retained. In the case of Ge2Sb2Te5, it is 150 nanoseconds, for example. In order to return the chalcogenide to the amorphous state, the temperature is raised to the melting point (about 600 ° C) or more and rapidly cooled.

 [0005] As a method for raising the temperature, there is a method in which an electric current is passed through the chalcogenide and heated by Joule heat generated in the chalcogenide or in an adjacent electrode. Hereinafter, crystallizing the chalcogenide of the phase change memory cell is called a set operation, and making it amorphous is called a reset operation. The state in which the phase change part is crystallized is called a set state or a crystalline state, and the state in which the phase change part is amorphized is called a reset state or amorphous state. The set time is, for example, 150 nanoseconds, and the reset time is, for example, 50 nanoseconds.

 [0006] A read operation (hereinafter referred to as a read operation) is as follows. By applying a voltage to the chalcogenide and measuring the current passing through it, the resistance of the chalcogenide is read and information is identified. If the chalcogenide is in the set state at this time, even if the temperature is raised to the crystallization temperature, the chalcogenide is crystallized from the beginning, so the set state is maintained. However, in the case of a reset state, information is destroyed. Therefore, the read voltage must be a very small voltage such as 0.3V so that crystallization does not occur. The feature of phase change memory is that it changes by 2 to 3 digits depending on whether the resistance value of the phase change part is crystalline or non-crystalline, and this resistance value corresponds to binary information '0' and '1' Therefore, the sensing operation is easy and the reading is fast because the resistance difference is large! /. In addition, multi-value storage can be performed by supporting information in ternary or higher.

[0007] Although the structure of a phase change memory cell usually has an information storage portion and a selection transistor power in many cases, a cross-point type memory cell having no selection transistor is also conceivable. Affection The information storage unit includes a chalcogenide, an upper electrode and a lower electrode sandwiching the chalcogenide. Generally, the lower electrode has a plug structure with a smaller contact area with the chalcogenide than the upper electrode.

[0008] Non-Patent Document 1 describes a general operation of the phase change memory cell as described above. The reset operation is performed by starting the word line and applying a current pulse with a pulse width of 20 to 50 nanoseconds to the bit line. The set operation is performed by starting the word line and applying a current pulse with a pulse width of 60 to 200 nanoseconds to the bit line. Read operation is performed by starting the word line and applying a current pulse with a pulse width of 20 to: LOO nanoseconds to the bit line. In such an operation, a method of controlling the reset current using a word line has been proposed as described in FIG. 8 of Patent Document 1. Non-Patent Document 2 describes that the characteristics of an irregular solid such as an amorphous semiconductor can be expressed by an equivalent circuit based on the CTRW (continuous-time random-walk) approximation.

 Patent Document 1: Japanese Patent Laid-Open No. 2005-260014

 Non-Patent Document 1: “2004 IEEE International Solid-State Circuits Conference, Digest, International 'Solid State' Circuit Conference, Digest of Technical Technical Papers or rechnical Papers) ”, p. 40—41

 Non-Patent Document 2: “Universality of Dynamic Electrical Conduction in Disturbed Systems”, Applied Physics, 1996, Vol. 65, No. 3, p. 256-260

 Disclosure of the invention

 Problems to be solved by the invention

The memory cell of the phase change memory as described above has a configuration as shown in FIG. 16, for example.

FIG. 16 is a circuit diagram showing a configuration example around the memory cell in the semiconductor integrated circuit device studied as a premise of the present invention. Memory cell MC also has select element SW and phase change element R force. As the selection element SW, it is preferable to use an NMOS transistor having a good process compatibility as a microcomputer mixed memory and a large driving capability. NMOS transistors have a larger drive current than PMOS transistors. At this time, the current flowing through the phase change element R flows from the bit line BL toward the source line SL. In FIG. 16, the phase change element R is placed between the selection element SW and the bit line BL. When the selection element SW is placed between the phase change element R and the bit line BL, the source potential of the SW rises compared to the source line SL. descend. In that case, in order to secure the same reset current, the gate width of the selection element SW must be increased, which causes a problem that the memory cell area increases. Therefore, the phase change element R should be placed between the selection element SW and the bit line BL.

 FIG. 17 is a waveform diagram showing an example of the operation of the semiconductor integrated circuit device of FIG. In FIG. 17, for example, the memory cell MCOO is selected, the reset operation, the set operation, and the read operation are performed, and the memory cell MC01 is not selected. However, applying a rectangular wave pulse to the bit line BLO during the operation of the MCOO affects the memory cell MC01 connected to the same bit line BLO.

 That is, the voltage of the word line WL1 connected to MC01 is OV and is not selected. Therefore, the selection element SW01 is turned off, and the drain current ID01 does not flow. However, if the phase change element R01 of MC01 is in the reset state, the equivalent circuit of R01 uses the CTRW approximation described in Non-Patent Document 2, and a pair of capacitors and resistors as shown in FIG. It becomes a circuit connected to. Therefore, R01 accumulates electric charge, and as a result, as shown in FIG. 17, a current IBL01 is generated for R01 when the bit line BLO rises and falls. In the actual process, a capacitive interface layer may be formed between the phase change element R and the selection element SW. In this case as well, the current IBL01 is generated.

 When such a current IBL01 is generated, the data retention characteristic of the memory cell MC01 is degraded.

 Semiconductor memory is generally required to retain data for 10 years at a temperature of 70 to 120 ° C. On the other hand, the 10-year data retention temperature of amorphous chalcogenides is generally 70 to 130 ° C, depending on the composition, but there is little margin for 10 ° C on the high temperature side. Therefore, in order to ensure the data retention characteristics, it is necessary to minimize the current flowing through the unselected memory cell in the reset state.

FIG. 19 and FIG. 20 are diagrams for explaining the contents of an experiment conducted by the present inventors in order to investigate the influence of disturbance on unselected memory cells. The ambient temperature is room temperature, as shown in Figure 19. For the TEG (Test Element Group) equipped with such a circuit, the operation shown in Fig. 20 was performed. The memory cell MC shown in FIG. 19 includes a selection element SW and a phase change element R, and the source line SL is set to 0 V and the word line WL is set to 0.4. The selection element SW is an NMOS transistor, and its threshold voltage is 0.2 to 0.4 V, and is off. Normally, the current that flows when 3V is applied to the drain of the selection element SW is 100 nanoamperes or less, and even if such a current is applied, the resistance of the phase change element R does not change.

Accordingly, as shown in FIG. 20, a pulse having an amplitude of 3 V, a pulse width of 30 nanoseconds, a rising width of 2 nanoseconds, and a falling width of 2 nanoseconds was applied to the bit line BL. There are several types of definition of rise time and fall time. Here, the time until the pulse amplitude transitions from 10% (0.3V) to 90% (2.7V) and the pulse amplitude is 90%. % (2.7V) force is also the time to transition to 10% (0.3V). And such a pulse was applied 100,000 times continuously.

 FIG. 21 is a diagram showing an example of the experimental results of FIGS. 19 and 20. Figure 21 shows the resistance value of the TEG immediately after resetting and the resistance value of the TEG after performing a disturb test in which 100,000 pulses are applied. Conducting the disturb test resulted in an increase in resistance of an order of magnitude or more. After the resistance rises, the voltage required for the set operation increases, and it is difficult to transition to the set state in the normal set operation. In addition, the current flowing through the phase change element scale reduces the data retention characteristics of the phase change memory at high temperatures, and the reset state can be easily destroyed, and information can be lost by changing to the set state. is there. Thus, there is a concern that when the bit line BL is driven with a rectangular waveform pulse, the current flows through the non-selected memory cells MC connected to the bit line, thereby reducing the reliability of the phase change memory. Is done.

 The present invention has been made in view of such problems and the like. The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

 Means for solving the problem

[0018] Among the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows. A semiconductor integrated circuit device according to the present invention is controlled by a word line and a bit line, a phase change element (memory element) having one end connected to the bit line, and a word line connected to the other end of the memory element. When the memory element is written in a high resistance state, the rise time and fall time of the bit line is longer than that of the word line. As a result, disturbance to the non-selected storage elements connected to the same bit line is reduced, and the reliability of the phase change memory can be improved. Similarly, when the memory element is written in a low resistance state, it is possible to improve the reliability of the phase change memory by increasing the rise time and the fall time of the bit line.

 [0020] It should be noted that when writing the memory element into a high resistance state, the force required to quench the memory element can be realized by using the falling edge of the word line. In addition, as a specific means for extending the rise time and fall time of the bit line, for example, a capacitive element is provided in the write circuit in which the bit line force is also connected via the bit line selection switch (second transistor). A method of generating a CR delay by connecting this capacitive element when writing is used. Another example is a method of designing the writing circuit with a low driving capability. If the latter is used, the circuit area can be reduced compared to the former.

 In the latter case, more specifically, for example, the driving capability (eg, gate width) of the write switch (third transistor) that is provided in the write circuit and outputs voltage or current at the time of write is selected by the bit line. It is better to make it smaller than the drive capability (eg gate width) of the switch (second transistor). As a result, while maintaining high speed during the read operation, it is possible to improve the reliability during the write operation by reducing the disturbance to the non-selected storage elements connected to the same bit line. . Note that the disturbance to the non-selected memory element becomes more obvious when a capacitive interface layer for increasing the thermal efficiency is formed at the connection portion on the first transistor side of the memory element. It becomes more effective when the above-described configuration is applied to such a configuration.

[0022] In addition, as described above, in the method in which the rise time and the Z fall time of the bit line are increased by adjusting the driving capability of the write circuit, the memory element is put in a high resistance state and a low resistance state. Using the same write circuit, the same voltage toward the bit line A value can be output. In this case, currents of different magnitudes may be supplied to the memory element by using different word line voltage values for the high resistance state and the low resistance state. Thus, by realizing writing in the high resistance state and writing in the low resistance state with a common writing circuit, the circuit area can be further reduced.

 The invention's effect

 [0023] If the effects obtained by typical ones of the inventions disclosed in the present application are briefly described, the reliability of the phase change memory can be improved.

 Brief Description of Drawings

 FIG. 1 is a circuit diagram showing a configuration example of a part around a memory cell in a semiconductor integrated circuit device according to a first embodiment of the present invention.

 2 is a waveform diagram showing an example of the operation of the semiconductor integrated circuit device of FIG.

 3 is a main part layout diagram showing a configuration example of a memory cell array including the memory cell of FIG.

FIG. 4 is a cross-sectional view of a principal part showing a manufacturing process of the memory cell array of FIG. 3 in stages and showing a configuration example between XX ′ in FIG. 3 in each stage.

 FIG. 5 shows the manufacturing process of the memory cell array of FIG. 3 step by step, and is a cross-sectional view of the main part showing a configuration example between XX ′ of FIG. 3 in each step.

 6 is a cross-sectional view of the principal part showing a manufacturing process of the memory cell array of FIG. 3 in stages, and showing a configuration example between XX ′ in FIG. 3 in each stage.

 7 is a cross-sectional view of a principal part showing a manufacturing process of the memory cell array of FIG. 3 in stages, and showing a configuration example between XX ′ in FIG. 3 in each stage.

 FIG. 8 is a circuit diagram showing an example of the configuration of a semiconductor integrated circuit device according to a second embodiment of the present invention.

 9 is a waveform diagram showing an example of the operation of the semiconductor integrated circuit device of FIG.

 FIG. 10 is a circuit diagram showing an example of the configuration of a semiconductor integrated circuit device according to a third embodiment of the present invention.

 11 is a waveform diagram showing an example of the operation of the semiconductor integrated circuit device of FIG.

FIG. 12 shows a configuration of a semiconductor integrated circuit device according to Embodiment 4 of the present invention. It is a circuit diagram which shows an example.

 13 is a waveform diagram showing an example of the operation of the semiconductor integrated circuit device of FIG.

 FIG. 14 is a circuit diagram showing a configuration example of a memory cell included in a semiconductor integrated circuit device according to a fifth embodiment of the present invention.

 FIG. 15 is a circuit diagram showing a configuration example of a memory cell included in a semiconductor integrated circuit device according to a sixth embodiment of the present invention.

 FIG. 16 is a circuit diagram showing a configuration example around the memory cell in a semiconductor integrated circuit device studied as a premise of the present invention.

 17 is a waveform diagram showing an example of the operation of the semiconductor integrated circuit device of FIG.

 FIG. 18 is an equivalent circuit diagram showing a storage element in an amorphous state.

 FIG. 19 is a diagram for explaining the contents of an experiment conducted by the present inventors in order to investigate the influence of disturbance on unselected memory cells.

 FIG. 20 is a diagram for explaining the contents of experiments conducted by the present inventors in order to investigate the influence of disturbance on unselected memory cells.

 FIG. 21 is a diagram showing an example of the experimental results of FIGS. 19 and 20.

 BEST MODE FOR CARRYING OUT THE INVENTION

 Hereinafter, some preferred examples of the semiconductor device according to the present invention will be described with reference to the drawings. In the drawings, the PMOS transistor is distinguished from the NMOS transistor by adding an arrow symbol to the gate. In the drawing, the connection of the substrate potential of the MOS transistor is not specified, but the connection method is not particularly limited as long as the MOS transistor can operate normally. In this specification, the reset state is a low level 'L' (or '0,'), the set state is a noise level 'Η' (or '1,'). Of course, the reset state is 'H' and the set state is It can also be 'L'.

 (Embodiment 1)

As described above, the cause of the disturbance of the unselected memory cells is that when the voltage of the bit line changes, the current flows in the memory cells connected to the same bit line and having different word lines. As a solution to this, the first embodiment extends the charge / discharge time of the capacitance component included in the phase change element by reducing the speed of the voltage change of the bit line. this Therefore, the peak current can be reduced, so that the heat generation of the non-selected memory cells is reduced by thermal diffusion, and the influence of disturbance can be reduced.

 FIG. 1 is a circuit diagram showing a configuration example of a part around a memory cell in the semiconductor integrated circuit device according to the first embodiment of the present invention. In FIG. 1, the semiconductor integrated circuit device includes a bit line BLO, a plurality of word lines WLO and WL1 corresponding to the BLO, and memory cells MCOO and MC01 arranged at the intersections of these word lines and bit lines. Is included. The memory cell MCOO includes a selection element SWOO and a phase change element ROO. The phase change element ROO is connected between the selection element SWOO and the bit line BLO. When the SWOO is controlled to be turned on by the word line WLO, the phase change element ROO is connected to the source line SLO that is one end of SWOO via the ROO. A current path is formed. Similarly, the memory cell MC01 includes a selection element SW01 and a phase change element R01, which is connected between the selection element SW01 and the bit line BLO, and the selection element SW01 is controlled by the word line WL1.

 FIG. 2 is a waveform diagram showing an example of the operation of the semiconductor integrated circuit device of FIG. Here, the case where the memory cell MCOO is operated is taken as an example. At this time, the bit line BLO and the word line WLO are driven, and the other bit lines and the word line remain fallen. When reset operation is performed, first the bit line BLO is turned on. The rise time trb at this time is made longer than the rise time trw of the word line WLO described later. Next, the word line WLO is raised and a current is passed through the phase change element ROO to melt it. After that, the word line WLO falls to rapidly cool the ROO and make it amorphous. At this time, the falling time tfw of the word line WLO needs to be shortened for convenience of rapid cooling. After that, the bit line BLO falls. The fall time tfb at this time is longer than the fall time tfw of the word line WLO. Because the phase change element is not rapidly cooled by lowering the bit line, the bit line has a short fall time and is not necessary!

[0029] Thus, by increasing the rise time and fall time of the bit line BLO, the charge / discharge current IBLO 1 flowing through the phase change element RO 1 of the non-selected memory cell MCO 1 can be reduced. It becomes possible. In addition, since the rapid cooling required for the reset operation is performed using the fall of the word line WLO, the reset operation can be performed without problems even if the fall time of the bit line BLO is lengthened. Therefore, it is possible to reduce the influence of disturb while guaranteeing reliable memory operation. The reliability of the phase change memory can be improved.

 [0030] Normally, the current that flows through the bit line BLO is the largest during the reset operation. Therefore, it is necessary to increase the rise time Z fall time of the BLO during the reset operation. The force that is most effective Of course, it is also beneficial to increase the rise and fall times during set operation. In Figure 2, as with the reset operation, the rise time Z fall time of the bit line BLO is longer than the rise time Z fall time of the word line WLO during the set operation. In this case, the timing at which a voltage is applied to the phase change element ROO along with the set operation may be defined by the word line WLO or the bit line BLO. In addition, the voltage value applied to the phase change element ROO is determined here by the voltage value of the bit line BLO.

 FIG. 3 is a main part layout diagram showing a configuration example of a memory cell array including the memory cell of FIG. In the memory array shown in FIG. 3, a plurality of word lines WL are arranged in parallel, and a plurality of bit lines BL are arranged in parallel in a direction perpendicular thereto. A plug electrode PLG is provided on one side across a word line WL, and a source line SL is provided on the other side. The plug electrode PLG is located below the bit line BL in the cross-sectional structure, and a phase change element (not shown) is connected to the plug electrode PLG. The optimum distance between the source line SL and the bit line BL is selected according to the drive current of the memory cell.

 Next, an example of a method for manufacturing the memory cell array of FIG. 3 will be described. 4 to 7 show the manufacturing process of the memory cell array of FIG. 3 step by step, and are principal part cross-sectional views showing a configuration example between X and X ′ of FIG. 3 in each step. First, the structure shown in the cross-sectional view of the main part of FIG. 4 is fabricated using a normal semiconductor manufacturing process. In the structure shown in FIG. 4, the diffusion layer DF is separated by the field oxide film ISL 1. The gate electrode GT is in contact with the gate insulating film ISL2, the sidewall SDW, and the metal silicide SS. An adhesion layer (barrier layer) BR1 is formed to improve the adhesion between the contact CNT1 and the interlayer insulation film ISL3 and prevent peeling. A metal wiring layer Ml is formed on the contact CNT1.

Next, a contact hole toward the metal wiring layer Ml is formed in the interlayer insulating film ISL3, and the adhesion layer BR2 and the plug electrode PLG are formed by chemical vapor deposition (CVD). Plug electrode PLG is a material that forms non-omic contact with chalcogenide. select. In addition, by using a plug material with high thermal resistance, it is possible to prevent the diffusion of Joule heat, which is a plug force, and to reduce the power required for rewriting. TiN (titanium nitride) can be used as the composition of the adhesion layer BR2, and W (tungsten) can be used as the composition of the plug electrode PLG.

 Subsequently, as shown in FIG. 5, an interface layer L may be formed between the plug electrode PLG and the adhesion layer BR 2 and the chalcogenide CN. The interface layer L has a higher electric resistance than the plug electrode PLG, and efficiently converts current to Joule heat as a heater during the rewriting operation. The interface layer L can also be used as an adhesive layer. Interfacial layer L has good adhesive strength with interlayer insulating film IS L3, plug electrode PLG and chalcogenide CN. Can be prevented. As a result, the manufacturing yield and the reliability associated with rewriting are improved. As the interface layer L, for example, Ta O

 Examples include capacitive materials such as 25 (tantalum oxide).

 [0035] Further, a chalcogenide CN serving as a phase change element and an upper electrode U are formed by sputtering or vacuum evaporation to form an interlayer insulating film ISL4. As the composition of chalcogenide CN, for example, a Ge—Sb—Te alloy having a wide track record in a recordable optical disk, or an alloy containing an additive in the alloy is suitable.

 Thereafter, as shown in FIG. 6, a contact hole is formed, and an adhesion layer BR3 and a contact CNT2 with the bit line are formed by chemical vapor deposition (CVD). Further, as shown in FIG. 7, an adhesion layer BR4 is formed, and a bit line BL is formed by sputtering. Subsequently, by forming an interlayer insulating film ISL5 and further forming an upper wiring, a desired memory can be manufactured.

Such a manufacturing method can be manufactured in accordance with a normal CMOS logic mixed design rule, and is also suitable for manufacturing a logic embedded memory. Further, as described in FIG. 5, when the interface layer L is formed, the charge / discharge current flowing through the phase change element of the non-selected memory cell described above may be larger. Therefore, a more beneficial effect can be obtained by applying the operation of increasing the rise / fall time as described in FIG. 2 to the configuration having such an interface layer. As described above, by using the semiconductor integrated circuit device of the first embodiment, the reliability of the phase change memory can be improved. In particular, when the phase change memory includes an interface layer between the chalcogenide and the plug electrode, it is possible to improve the reliability of the phase change memory.

 [0039] (Embodiment 2)

 In the second embodiment, an example of a circuit configuration that realizes the function of extending the rise Z fall time described in the first embodiment will be described. FIG. 8 is a circuit diagram showing an example of the configuration of the semiconductor integrated circuit device according to the second embodiment of the present invention. The semiconductor integrated circuit device shown in FIG. 8 includes a memory array unit ARY, an X-system address decoder X—DEC, a Y-system address decoder Y—DEC, and a read / write circuit RWC. The memory array unit ARY also includes a plurality of word lines WLO to WLn, a plurality of bit lines BLO to BLm, and a plurality of memory cells MCO 0 to MCnm provided at the intersections of the word lines and the bit lines. . Actually, for example, a force that may include a plurality of source lines SLO to SLm paired with a plurality of bit lines BL 0 to BLm may be omitted. Ground as ground!

Each of the memory cells MCOO to MCnm has the same configuration except that the corresponding word line and bit line are different from each other, and therefore the configuration will be described by taking the memory cell MCOO as an example. The memory cell MCOO includes a selection element MNOO and a storage element ROO. The memory element R 00 is a phase change element, and has a low resistance of, for example, lk Q to 10 kQ in the crystalline state, and has a high resistance of, for example, 10 (¾ Ω to 100 μΩ). The selection element MNOO is The gate electrode of the selection element MNOO is connected to the word line WL 0, the drain electrode is connected to one end of the storage element ROO, and the source electrode is connected to the source line (ground GND). The other end of the storage element ROO is connected to the bit line BLO, where a bipolar transistor may be used instead of the force using a MOS transistor as the selection element MNOO. At the same time, the selection element of the phase change memory cell cannot be formed. Therefore, although there is a problem that the manufacturing cost increases as a microcomputer embedded memory, driving per area of the selection element Can force large, therefore, it can be advantageously reduced memory cell area. Each word line WL0 to WLn is connected to an X system address decoder X—DEC, and one word line WL is selected by an X system address signal generated by X—DEC. One end of the bit line BL is connected to a Y-system address decoder Y-DEC, and one of the bit line selection switches YS0 to YSm is selected by the Y-system address signal generated by the Y-DEC. Bit line BL is connected to RWC, which will be described later, via node N1. In this example, one read / write circuit RWC is provided for each memory array unit ARY. Of course, a plurality of RWCs may be provided. In that case, since multiple bits can be written and read simultaneously, there is an effect that high-speed operation is possible.

 [0042] Read 'Write circuit RWC includes a read current source Ird and a read switch R SW, a set current source Iset and a set switch SS—SW, a reset current source Irst and a reset switch RS—SW, and a sense Includes amp SA. In addition, the RWC includes a capacitance Cwt, a capacitance addition switch WC-SW, and a ground switch GSW! RSW, SS—SW, and RS—SW are switches that connect Ird, Iset, and Irst to nodes NI, respectively, and this node N1 is connected to the corresponding bit line when the bit line selection switch YS is selected. Is done. Note that the voltages Vrd, Vset and Vrst are supplied to one end different from the switch side of Ird, Iset and Irst, respectively. When the sense amplifier enable signal SE is activated, the sense amplifier SA amplifies the read signal of the selected bit line by comparing it with the reference voltage REF and outputs it to the data output line D.

 [0043] The capacity addition switch WC-SW is a switch for connecting the capacity Cwt to the node N1. C wt is formed using a MOS transistor, for example. The ground switch GSW connects node N1 to ground GND. WC-SW, Cwt, and GSW are means for increasing the rise and fall times of the bit line BL, as will be described later.

Next, the influence of MCnO connected to the same bit line BLO as MCOO will be described by taking as an example the case where memory cell MCOO is operated. FIG. 9 is a waveform diagram showing an example of the operation of the semiconductor integrated circuit device of FIG. As shown in FIG. 9, the reset operation (RESET) is performed as follows. Read switch RSW, set switch SS—SW, and ground switch GSW are turned off. First, turn on the additional switch WC—SW, Select BLO by Y—DEC and YSO, then turn on reset switch RS—SW. As a result, electric charge is accumulated in the capacitor Cwt in addition to the wiring capacitance such as BLO, so that the voltage of BLO does not rise instantaneously and the rise time can be made longer than the word line WLO described later.

 [0045] After that, by selecting WLO by X-DEC, a current larger than the set current described later is caused to flow through the memory cell MCOO. After supplying current for a certain time, the word line WLO is lowered. As a result, the storage element ROO becomes amorphous by being rapidly cooled from the molten state. After that, turn off the reset switch RS-SW and turn on the ground switch GSW. As a result, electric charge is discharged from the capacitance Cwt in addition to the wiring capacitance such as BLO. Therefore, the voltage of BLO does not decrease instantaneously, and the fall time can be made longer than that of the word line WLO described above. After BLO falls, turn off YSO, GSW and WC—SW. When such a reset operation is performed, the memory element RnO of the memory cell MCnO is hardly affected by the voltage change because the voltage change speed of the bit line BLO to which it is connected is slow. As a result, the current IcelnO flowing through RnO can be reduced.

 [0046] The set operation (SET) is performed as follows. Read switch RSW and reset switch RS- SW are turned off. First, the capacity addition switch WC-SW is turned on, and BLO is selected by Y-DEC and YSO. Next, turn on the set switch SS-SW. Then, charges are accumulated in the capacitor Cwt in addition to the wiring capacitance such as BLO. Therefore, the voltage of BLO does not rise instantaneously, and the rise time can be made longer than the word line WLO described later.

[0047] Subsequently, by selecting WLO by X-DEC, a current smaller than that in the above-described reset operation is caused to flow through the memory cell MCOO. After supplying a current for a longer time than the above-mentioned reset operation, the set switch SS—SW is turned off and the ground switch GSW is turned on. Then, in addition to the wiring capacitance such as BLO, the capacitance Cwt and others are also discharged, so the voltage of BLO does not decrease instantaneously, and the fall time can be made longer than the word line WLO described above. As a result, the storage element ROO is crystallized. When such a set operation is performed, the memory element RnO of the memory cell MCnO is connected !, and the speed of the voltage change of the bit line BLO is slow, so that it is hardly affected by the voltage change. As a result, the current IcelnO flowing through RnO is reduced. It is pretty easy to do.

[0048] The read operation (READ) is performed as follows. The reset switch RS-SW, ground switch GSW, set switch SS— SW, and capacitance addition switch WC— SW are turned off. The memory cell MCOO is selected by X—DEC and Y—DEC, and the read switch RSW is turned on. After a certain time, the read switch RSW is turned off. At this time, a current corresponding to the resistance value flows in the memory element ROO. That is, if the storage element ROO is in a high resistance state (amorphous state), the bit line BLO is charged at a higher voltage than in the low resistance state (crystalline state). By turning on the sense amplifier enable signal SE, this potential difference is amplified by the sense amplifier SA, and data can be obtained from the data output line D.

 In the read operation, since the capacitance addition switch WC-SW is off, the bit line capacitance is small and high-speed and power-saving reading is possible. That is, in the read operation, the voltage used is low unlike the set operation or the reset operation. Therefore, even if the capacitor addition switch WC-SW is turned off, the storage element of the non-selected memory cell is not easily affected. Information is not easily destroyed.

 As described above, by using the semiconductor integrated circuit device of the second embodiment, the reliability of the phase change memory is improved as described in the first embodiment while maintaining the reading speed. It becomes possible to make it. In practice, even if a capacitance Cwt is provided in the read / write circuit RWC, the area overhead is less affected. That is, as shown in FIG. 8, if a single capacitance Cwt is provided for a plurality of bit lines BLO to BLm, the capacitance can be covered to some extent by the wiring capacitance.

[0051] Furthermore, the provision of the capacitance Cwt in the read / write circuit RWC has the effect of stabilizing the bit line capacitance during writing. In other words, the capacity of the memory cell in terms of bit line strength is larger in the memory cell in the reset state than in the set state. Therefore, comparing the case where a large number of reset state memory cells are connected to the bit line and the case where a large number of set state memory cells are connected, the former has a larger bit line capacity. The change in bit capacity depending on the storage state of each memory cell affects the transition timing of the bit line at the time of writing, so that stable writing becomes difficult. So, by using the capacity Cwt, As a result, it is possible to keep the bit line capacity above a certain value, and to reduce relative changes in the bit line capacity. As a result, stable writing can be performed regardless of the storage state of the memory cell.

 [0052] (Embodiment 3)

 In the third embodiment, an example of a circuit configuration different from that of the second embodiment that realizes the function of extending the rise Z fall time described in the first embodiment will be described. FIG. 10 is a circuit diagram showing an example of the configuration of the semiconductor integrated circuit device according to the third embodiment of the present invention. The semiconductor integrated circuit device shown in FIG. 10 includes a memory array unit AR Ya, an X-system address decoder X-DECa, a Y-system address decoder Y-DECa, and a read / write circuit RWCa.

 [0053] The memory array unit ARYa has the same configuration as that of FIG. 8 described above, and includes a plurality of sub word lines SWL0 to SWLn, a plurality of bit lines BL0 to BLm, and intersections of the sub word lines and the bit lines. A plurality of memory cells MC00 to MCnm provided respectively. Again, as in Figure 8, the source line is omitted and is grounded. Each of the memory cells MCOO to MCnm has the same configuration as that in FIG. 8, for example, MCOO includes a selection element MNOO and a storage element R00, and the selection element MN00 is, for example, an NMOS transistor. The gate electrode of the selection element MN00 is connected to the sub word line SWL0, the drain electrode is connected to one end of the storage element R00, and the source electrode is connected to the source line (ground GND). The other end of the storage element R00 is connected to the bit line BL0.

Each sub word line SWL0 to SWLn is connected to an X system address decoder X-DECa. X— DECa turns on sub word line drivers XDRO to XDRn that drive sub word lines SWL0 to SWLn, main word lines M WLl to MWLp that control ON / OFF of XDRO to XDRn, and XDRO to XDRn, respectively. FX drivers FXDR1 to FXDR8, which set the drive voltage of SWLO to SWLn at the time, are also configured. For example, when XDRO is turned on, the output voltage FXO of FXDR1 is output to SWLO via the word line drive transistor XTR in XDRO. The output voltage FXO of FXDR1 becomes the power supply voltage VDD corresponding to the control signal FXI, and becomes the ground GND corresponding to the control signal FXB. Each bit line BLO˜: BLm is connected to a Y-system address decoder Y—DECa. Y—DE Ca includes bit line selection switches YSO to YSm that select and connect any of the plurality of bit lines BLO to BLm to node N1. For example, YSO includes a bit line connection transistor YTR 0, and this YTRO connects BLO and N 1 when the bit line selection signal BLSWO is activated. Here, YTRO is composed of, for example, a MOS transistor. Similarly, a bit line connection transistor (not shown) in YSm connects BLm and N1 when the bit line selection signal BLSWm is activated.

 [0056] A read / write circuit RWCa is connected to the node N1. RWCa includes a reset current source Irst and reset switch RS—SW, a set current source Iset and set switch SS—SW, and a readout circuit. The read circuit includes a voltage source Vpre for bit line precharge, a precharge switch PRE and a read switch TG for connecting Vpre to a node N1, and a sense amplifier SA connected to a node between TG and PRE. Is included. Note that the voltage V rst and the voltage Vset are supplied to one end different from the switch side of the Irst and Iset, respectively. RS-SW and SS-SW are composed of, for example, MOS transistors.

 In such a configuration, in the third embodiment, the rise time Z fall time of the bit line during the write operation is reduced by reducing the drive capability of the reset switch RS-SW and the set switch SS-SW. Make it longer. Specifically, for example, the gate width of the reset switch RS-SW and the set switch SS-SW is made smaller than the gate width of the word line drive transistor XTR in the sub word line driver XDR. Further, for example, the gate width of the reset switch RS-SW and the set switch SS-SW is made smaller than the gate width of the bit line connection transistor YTR in the bit line selection switch YS.

FIG. 11 is a waveform diagram showing an example of the operation of the semiconductor integrated circuit device of FIG. Here, a case where operation is performed on the memory cell MCOO will be described as an example. As shown in Fig. 11, when reset operation (RESET) is performed, the reset switch RS— SW and bit line selection switch YSO turns on the bit line connection transistor YTRO to select and start the bit line BLO. . At this time, the drive time of RS-SW is low, so the rise time of BLO becomes long. Therefore, for example, the memory cell MC10 connected to the same bit line BLO The current IcellO flowing through the storage element RIO can be reduced.

 [0059] After that, the control signal FXI and the main word line MWL1 for the FX driver FXDR1 are selected and the control signal FXB is deselected to start up the sub word line SWLO. After a sufficient time has elapsed for the memory element ROO to be heated to the melting point, FXI and MWL1 are deselected and SWLO is lowered by selecting the control signal FXB. At this time, each transistor in the sub word line driver XDRO including the word line drive transistor XTR is designed to have high driving capability, and SWLO can be rapidly lowered. As a result, the storage element ROO is rapidly cooled to be in an amorphous state. Next, turn off RS- SW and YT RO to bring down BLO. Even at this time, the LB-SW drive capability is designed to be low, so the BLO fall time is long. Therefore, for example, the current IcellO flowing through the memory element RIO can be reduced.

 [0060] When the set operation (SET) is performed, the bit line BLO is selected and started by turning on the bit line connection transistor YTRO in the set switch SS-SW and the bit line selection switch YSO. At this time, since the SS-SW drive capability is low, the rise time of BLO becomes long, and for example, the current IcellO flowing through the storage element RIO can be reduced. After that, the sub word line SWLO is started in the same manner as in the reset operation, and after passing a smaller current to the storage element ROO than in the reset operation for a longer time than in the reset operation, the SWLO is lowered. . Also, with the fall of SWLO, turn off SS- SW and YTRO to bring down BLO. At this time, because the SS-SW drive capability is designed to be low, the fall time of BLO becomes long. As a result, the storage element ROO is in a crystalline state, and further, for example, the current IcellO flowing through the storage element RIO can be reduced.

[0061] When performing a read operation (READ), the bit line BLO is selected by turning on the read switch TG, the precharge switch PRE, and the bit line connection transistor YTRO, and the voltage source Vpre is applied to the BLO. Is precharged. At this time, since the precharge voltage is low, for example, the current IcellO flowing as a disturb in the storage element RIO is small, and the influence of the disturb on the unselected memory cell is small. Then, turn off PRE and start up the sub word line SWLO in the same way as during reset operation. As a result, the voltage of BLO is maintained almost at the precharge voltage when the storage element ROO is in an amorphous state. In the crystal state, it is discharged toward the ground GND. Therefore, reading can be performed by sensing the difference in the voltage of the BLO with the sense amplifier SA. After the read data is confirmed, turn TG and YTRO off.

 [0062] By the way, in general, the drive capability (gate width) of the reset switch RS-SW or set switch SS-SW is designed to be somewhat large in order to supply the current or voltage to the bit line BL at high speed. The In particular, the RS-SW gate width must be made sufficiently large in a method that realizes rapid cooling in the reset operation by stopping the current to the bit line BL. In general, the bit line connection transistor YTR must be provided for each bit line unlike the RS-SW or SS-SW, and the number of transistors increases. Designed with a smaller gate width than SW.

 [0063] On the other hand, in the circuit of the third embodiment, the magnitude relationship is reversed, and a bit line connection transistor YTR having a gate width as large as possible within the allowable circuit area is designed. Design RS-SW or SS-SW so that the gate width is smaller than that. Then, during the read operation, the bit line connection transistor YTR is designed to have a certain gate width, so that a high-speed read operation is possible. Furthermore, during reset operation or set operation, the gate width of RS-SW or SS-SW is designed to be small, so that the transition time of the bit line during write operation can be lengthened, and disturbance to unselected memory cells can be prevented. The influence can be reduced. Even when the gate width of RS-SW is designed to be small, there is no problem because the rapid cooling during the reset operation is performed by the fall of the word line WL.

[0064] In general, in a phase change memory that requires a large current to flow at reset, the gate width of the word line drive transistor XTR in the sub word line driver XDR is set to the reset switch RS-SW or set switch SS— Designed to be smaller than the gate width of SW. This is because the number of only one RS-SW or SS-SW in the plurality of bit lines BL is smaller than XTR existing in each sub-word line SWL. On the other hand, in the circuit of the third embodiment, the XTR gate width sufficient to perform the rapid cooling of the reset operation by the falling of the word line WL is secured, and the gate width is smaller than this XTR! RS-SW or SS-SW is provided to reduce the influence of disturb on unselected memory cells. . That is, the magnitude relationship can be opposite to that of the general configuration described above.

 As described above, by using the semiconductor integrated circuit device of the third embodiment, the reliability of the phase change memory is improved as described in the first embodiment while maintaining the reading speed. It becomes possible to make it. In addition, since the transistor size of the reset switch RS-SW or set switch SS-SW can be reduced, the reliability of the phase change memory can be improved with a small circuit area.

 [0066] (Embodiment 4)

 In the fourth embodiment, an example of a circuit configuration different from the second and third embodiments that realizes the function of extending the rise Z fall time described in the first embodiment will be described. FIG. 12 is a circuit diagram showing an example of the configuration of the semiconductor integrated circuit device according to the fourth embodiment of the present invention. The semiconductor integrated circuit device shown in FIG. 12 includes a memory array unit AR Yb, an X-system address decoder X-DECb, a Y-system address decoder Y-DECb, and a read / write circuit RWCb. The configuration example shown in FIG. 12 is a modification of the configuration example shown in FIG. 10 described in the third embodiment, and the following description will be made with a focus on differences from the configuration example shown in FIG.

 [0067] ARYb and Y-DECb shown in FIG. 12 have the same configuration as ARYa and Y-DECa shown in FIG. X-DECb in Fig. 12 differs from X-DECa in Fig. 10 in the configuration of the FX driver, and is otherwise the same. That is, the FX driver FXDR in Fig. 10 is a driver that outputs two values of the power supply voltage VDD or ground GND, whereas the FX driver FXbDR in Fig. 12 has the power supply voltage for setting VWset or the power supply voltage for resetting VW rst or It is a driver that outputs three values of ground GND. The output voltage FXO of FXbDR becomes VWset corresponding to the control signal FXSET, becomes VWrst corresponding to the control signal FXRST, and becomes ground GND corresponding to the control signal FXB. This output voltage FXO is supplied to the sub word line dry DR as in FIG. 10, and when the main word line MWL is selected, the sub word line SWL is driven via the word line drive transistor XTR in the XDR. Voltage.

[0068] Further, unlike the read 'write circuit RWCa shown in Fig. 10, the read' write circuit RWCb shown in Fig. 12 has a write transistor controlled by the write control signal WT. The configuration includes a star WTR, a read transistor RTR controlled by a read control signal RD, and a sense amplifier SA. The RWCb in Figure 12 is different from the RWCa in Figure 10 in that it has a switch and current source for reset operation and a switch and current source for set operation. It is characterized by having a source Vw t. The WTR is composed of, for example, a MOS transistor.

 [0069] In such a configuration, in the fourth embodiment, as in the third embodiment, the rise time Z fall time of the bit line during the write operation is increased by lowering the drive capability of the WTR. To do. Specifically, for example, the gate width of the WTR is made smaller than the gate width of the bit line connection transistor YTR in the bit line selection switch YS.

 FIG. 13 is a waveform diagram showing an example of the operation of the semiconductor integrated circuit device of FIG. The operation of FIG. 13 differs from the operation of FIG. 11 in that the drive voltage of the sub word line is changed by the set operation and the reset operation. In the following, an example of operation will be described using the case of operating on the memory cell MCOO. As shown in Fig. 13, when reset operation (RESET) is performed, WTR is turned on by the write control signal WT and the bit line connection transistor YTRO in the bit line selection switch YSO is turned on. And supply voltage Vwt to BLO. At this time, since the drive capability of WTR is low, the rise time of BLO becomes long. Therefore, for example, the current IcelnO flowing through the storage element RnO of the memory cell MCnO connected to the same bit line BLO can be reduced.

[0071] Thereafter, the control signal FXRST and the main word line MWL1 for the FX driver FXbDRl are selected, and the control signal FXB is deselected to start up the sub word line SWLO. At this time, the reset power supply voltage VWrst is output by FXbDRl, and this voltage becomes the drive voltage of the sub word line SWLO via the lead line drive transistor XTR. After a sufficient time has elapsed for the storage element ROO to be heated to the melting point, FXRST and MWL1 are deselected and SWLO is lowered by selecting the control signal FXB. At this time, each transistor in the sub word line dry transistor XDRO including the word line drive transistor XTR is designed to have high drive capability, and SWLO can be rapidly lowered. As a result, the storage element ROO is rapidly cooled to be in an amorphous state. Next, WTR and YTR Turn off 0 to bring down BLO. In this case, the fall time of the BLO is long because the drive capability of the WTR is low. Therefore, for example, the current IcelnO flowing through the storage element RnO can be reduced.

 [0072] When set operation (SET) is performed, WTR is turned on by the write control signal WT and the bit line connection transistor YTRO is turned on to select the bit line BLO. Supply the same voltage Vwt. At this time, since the drive capability of the WTR is low, the rise time of BLO becomes long, and for example, the current IcelnO flowing through the storage element RnO can be reduced. After that, the control signal FXSET and main terminal line MWL1 for the FX driver FXbDRl are selected, and the control signal FXB is deselected to start up the sub word line SWLO. At this time, FXbDRl outputs a set power supply voltage VWset having a voltage value smaller than VWrst, and this voltage becomes the SWLO drive voltage via XTR.

 [0073] By using the difference in the drive voltage of SWLO, a current smaller than that in the reset operation is supplied to storage element ROO for a longer time than in the reset operation, and then SWLO is lowered. Also, along with the fall of S WLO, turn off WTR and YTRO to bring down BLO. At this time, since the drive capability of the WTR is designed to be low, the fall time of the BLO becomes long. As a result, the storage element ROO is in a crystalline state, and further, for example, the current IcelnO flowing through the storage element RnO can be reduced.

 [0074] Also, when performing a read operation (READ), the read transistor RTR is turned on by the read control signal RD, and the bit line connection transistor YTRO is turned on to select the bit line BLO and read to the BLO. Apply voltage Vrd. At this time, since the voltage or current for reading is small! /, For example, the current IcelnO flowing through the storage element RnO is also small! / ヽ. Thereafter, the sub word line SW LO is raised using the control signal FXRST, for example, as in the reset operation. As a result, the storage element ROO generates a discharge corresponding to its state, and the difference in the discharge state is sensed and amplified by the sense amplifier SA. After the read data is confirmed, the sub-word line SWLO is lowered and the read transistors RTR and YTR 0 are turned off.

In the configuration example of FIG. 12, similarly to the configuration example of FIG. 10, the gate width of the write transistor WTR is designed to be smaller than that of the bit line connection transistor YTRO, so that the read operation can be performed at high speed. In addition, the disturbance to unselected memory cells during reset operation or set operation can be reduced. Furthermore, since the write circuit is shared between the set operation and the reset operation by changing the drive voltage of the sub word line SWL, the circuit area can be further reduced compared to the configuration example of FIG. It becomes possible.

 As described above, by using the semiconductor integrated circuit device according to the fourth embodiment, the reliability of the phase change memory is improved as described in the first embodiment while maintaining the reading speed. It becomes possible to make it. Further, the circuit area can be further reduced as compared with the semiconductor integrated circuit device of the third embodiment.

 [0077] (Embodiment 5)

 In the semiconductor integrated circuit device of the fifth embodiment, the disturbance to the unselected memory cells is prevented by the configuration of the memory cells. FIG. 14 is a circuit diagram showing a configuration example of the memory cell included in the semiconductor integrated circuit device according to the fifth embodiment of the present invention. The memory cell MC of FIG. 14 includes a diode D in addition to a selection element SW and a storage element (phase change element) scale. The selection element SW is, for example, an NMOS transistor, and has a gate connected to the word line WL, a source connected to the source line SL, and a drain connected to one end of the phase change element R. The other end of phase change element R is connected to the force sword of diode D, and the anode of diode D is connected to bit line BL.

 [0078] When such a configuration is used, the current flowing in the reverse direction due to the diode D can be prevented, so that the influence of the disturb of the unselected memory cell can be halved. The diode D can be formed using a diffusion layer, for example.

 [0079] (Embodiment 6)

As in the fifth embodiment, the semiconductor integrated circuit device according to the sixth embodiment prevents disturbance to unselected memory cells by the configuration of the memory cells. FIG. 15 is a circuit diagram showing a configuration example of the memory cell included in the semiconductor integrated circuit device according to the sixth embodiment of the present invention. The memory cell MC shown in FIG. 15 includes two selection elements SWa and SWb, and a storage element change element (R) connected therebetween. The selection elements S Wa and SWb are, for example, NMOS transistors. SWa has a gate connected to word line WL, a drain connected to bit line BL, and a source connected to one end of phase change element R. The SWb has a gate connected to word line WL, a drain connected to the other end of phase change element R, and a source connected to source line SL.

When such a configuration is used, when the memory cell MC is not selected, the bit line BL and the phase change element R are cut off by the selection element SWa, so that the influence of disturbance hardly occurs. ! / ヽ

. Note that the selection element SWa is designed to have a threshold voltage lower than that of the selection element SWb, and the leakage current is large, but it has sufficient driving force. Therefore, the current flow during writing is actually adjusted by the SWb design.

[0081] As described above, the invention made by the present inventor has been specifically described based on the embodiment.

Needless to say, the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the scope of the invention.

 Industrial applicability

The semiconductor integrated circuit device of the present invention is a high-density integrated memory circuit including memory cells using a phase change material, or a logic mixed memory in which a memory circuit and a logic circuit are provided on the same semiconductor substrate. It is even more useful when such products are used under high temperature conditions.

Claims

The scope of the claims  [1] Multiple word lines,  A plurality of bit lines extending in a direction intersecting the plurality of word lines;  A plurality of memory cells respectively disposed at intersections of the plurality of word lines and the plurality of bit lines;  Each of the plurality of memory cells includes  One end of the plurality of bit lines is connected to one of the bit lines, and a memory element that stores information by being written in a high resistance state or a low resistance state;  A first transistor whose one end is connected to the other end of the memory element, and the on / off of the plurality of word lines is controlled by being shifted,  When writing the storage element in a high resistance state, the rise time of the plurality of bit lines is longer than the rise time of the plurality of word lines, or the fall time of the plurality of bit lines is equal to the plurality of words. A semiconductor integrated circuit device characterized by being longer than the fall time of the line.  [2] The semiconductor integrated circuit device according to claim 1, further comprising:  When writing the memory element in a low resistance state, the rise time of the plurality of bit lines is longer than the rise time of the plurality of word lines, or the fall time of the plurality of bit lines is the plurality of word lines. A semiconductor integrated circuit device characterized by being longer than the fall time of the line.  [3] The semiconductor integrated circuit device according to claim 1,  The plurality of bit lines are connected to a write circuit via a second transistor whose on-Z-off is controlled by a selection signal from an address decoder,  The write circuit uses the capacitive element provided in the write circuit to increase the rise time Z fall time of the plurality of bit lines when the memory element is written in a high resistance state. A semiconductor integrated circuit device. [4] The semiconductor integrated circuit device according to claim 1, The plurality of bit lines are connected to a write circuit via a second transistor whose on-Z-off is controlled by a selection signal from an address decoder, The write circuit is designed to increase the rise time Z fall time of the plurality of bit lines by being designed to have a low driving capability when writing the memory element in a high resistance state. apparatus.  [5] The semiconductor integrated circuit device according to claim 1,  A semiconductor integrated circuit device characterized in that when the memory element is written in a high resistance state, the memory element is rapidly cooled using a fall of a word line corresponding to the memory element.  [6] The semiconductor integrated circuit device according to claim 1,  The semiconductor integrated circuit is characterized in that a capacitive interface layer for efficiently transferring heat to the storage element is formed at a connection portion on the first transistor side of the storage element. Circuit device. [7] The semiconductor integrated circuit device according to claim 4,  The write circuit outputs a voltage signal or a current signal through a third transistor toward a bit line corresponding to the storage element when writing the storage element to a high resistance state.  The semiconductor integrated circuit device, wherein the third transistor has a driving capability smaller than that of the second transistor. [8] Multiple word lines,  A plurality of bit lines extending in a direction intersecting the plurality of word lines;  A plurality of memory cells respectively disposed at intersections of the plurality of word lines and the plurality of bit lines;  Each of the plurality of memory cells includes  One end of the plurality of bit lines is connected to one of the bit lines, and a memory element that stores information by being written in a high resistance state or a low resistance state;  A first transistor whose one end is connected to the other end of the storage element, and on / off of the plurality of word lines is controlled by being shifted, The plurality of bit lines are connected to a write circuit via a second transistor whose on-Z-off is controlled by a selection signal from an address decoder, The write circuit outputs a voltage value of the same level using the same circuit when writing the memory element into a high resistance state and when writing into the low resistance state,  The plurality of word lines output a first level voltage value when the storage element is written in a high resistance state, and output a second level voltage value when the storage element is written in a low resistance state. A semiconductor integrated circuit device driven by a drive circuit.  [9] The semiconductor integrated circuit device according to claim 8,  When writing to the storage element, rise times of the plurality of bit lines are longer than rise times of the plurality of word lines, or fall times of the plurality of bit lines are set to the plurality of bit lines. A semiconductor integrated circuit device characterized by being longer than the fall time of a word line. [10] The semiconductor integrated circuit device according to claim 8,  The write circuit outputs a voltage value of the same level via the fourth transistor when writing the memory element in a high resistance state and when writing to the low resistance state,  The semiconductor integrated circuit device, wherein the fourth transistor has a driving capability smaller than that of the second transistor. [11] The semiconductor integrated circuit device according to claim 8,  A semiconductor integrated circuit device characterized in that when the memory element is written in a high resistance state, the memory element is rapidly cooled using a fall of a word line corresponding to the memory element.  [12] The semiconductor integrated circuit device according to claim 8,  The semiconductor integrated circuit is characterized in that a capacitive interface layer for efficiently transferring heat to the storage element is formed at a connection portion on the first transistor side of the storage element. Circuit device. [13] Multiple word lines,  A plurality of bit lines extending in a direction intersecting the plurality of word lines; A plurality of memory cells respectively disposed at intersections of the plurality of word lines and the plurality of bit lines; Each of the plurality of memory cells includes  One end of the plurality of bit lines is connected to one of the bit lines, and a memory element that stores information by being written in a high resistance state or a low resistance state;  A first transistor whose one end is connected to the other end of the storage element, and on / off of the plurality of word lines is controlled by being shifted,  The plurality of bit lines are connected to a write circuit via a second transistor whose on-Z-off is controlled by a selection signal from an address decoder,  The write circuit outputs a voltage signal or a current signal through a third transistor toward a bit line corresponding to the storage element when writing the storage element to a high resistance state.  The semiconductor integrated circuit device, wherein the drive capability of the third transistor is smaller than the drive capability of the second transistor. 14. The semiconductor integrated circuit device according to claim 13, further comprising:  The write circuit outputs a voltage signal or a current signal via a fifth transistor toward a bit line corresponding to the storage element when writing the storage element to a low resistance state.  The semiconductor integrated circuit device, wherein the drive capability of the fifth transistor is smaller than the drive capability of the second transistor. [15] The semiconductor integrated circuit device according to claim 13,  A semiconductor integrated circuit device characterized in that when the memory element is written in a high resistance state, the memory element is rapidly cooled using a fall of a word line corresponding to the memory element.  [16] The semiconductor integrated circuit device according to claim 13,  The semiconductor integrated circuit is characterized in that a capacitive interface layer for efficiently transferring heat to the storage element is formed at a connection portion on the first transistor side of the storage element. Circuit device. [17] The semiconductor integrated circuit device according to claim 14, When writing the memory element to a high resistance state or a low resistance state, the plurality of bit lines The rise time of the plurality of word lines is longer than the rise time of the plurality of word lines, or the fall time of the plurality of bit lines is longer than the fall time of the plurality of word lines. .