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WO2008015212A1 - Structure de masque dur innovante pour tracer des motifs sur des éléments dans des dispositifs semi-conducteurs - Google Patents

Structure de masque dur innovante pour tracer des motifs sur des éléments dans des dispositifs semi-conducteurs Download PDF

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Publication number
WO2008015212A1
WO2008015212A1 PCT/EP2007/057899 EP2007057899W WO2008015212A1 WO 2008015212 A1 WO2008015212 A1 WO 2008015212A1 EP 2007057899 W EP2007057899 W EP 2007057899W WO 2008015212 A1 WO2008015212 A1 WO 2008015212A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
opening
lateral width
amorphous carbon
feature
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/EP2007/057899
Other languages
English (en)
Inventor
Marcel Eduard Irene Broekaart
Veronique De-Jonghe
François Leverd
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics Crolles 2 SAS
Koninklijke Philips NV
Original Assignee
STMicroelectronics Crolles 2 SAS
Koninklijke Philips Electronics NV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics Crolles 2 SAS, Koninklijke Philips Electronics NV filed Critical STMicroelectronics Crolles 2 SAS
Publication of WO2008015212A1 publication Critical patent/WO2008015212A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0338—Process specially adapted to improve the resolution of the mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/3088—Process specially adapted to improve the resolution of the mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks

Definitions

  • the present invention relates to a method for fabricating at least one feature, which has a target lateral width, in a substrate layer.
  • the invention also relates to a method for fabricating at least one first feature and at least one second feature in a substrate layer, the first and second features having a target lateral width and a mutual target lateral pitch.
  • the critical dimensions of a feature comprise a lateral extension of the feature attained by the employed fabrication technology.
  • CMOS Complementary Metal-Oxide-Semiconductor
  • the minimum feature size of features like holes, trenches, and lines are linked to the characteristics of the used mask, photoresist material and scanner technology, which are employed for exposure and development of a photoresist layer used for patterning of a substrate layer.
  • CMOS Complementary Metal-Oxide-Semiconductor
  • photolithography has moved from 248nm wavelength to 193 nm, and on to a 193 nm- immersion technology for a stepwise increase of resolution, i.e. reduction of critical dimension.
  • US 2005/0056823 Al describes a method for fabricating features in a substrate layer.
  • the process comprises depositing an antireflective material layer on a substrate layer, in which the features are to be fabricated.
  • a photoresist layer is deposited on top of the antireflective material layer.
  • the layer of antireflective material has general structural formula metal:carbon:hydrogen:inorganic element, an example of which is formed by the material Si:C:H:O.
  • the photoresist layer comprises carbon, hydrogen, and oxygen, and not any metal atoms, nor silicon.
  • the patterning process involves a plasma etch step, which in US
  • 2005/0056823 Al is used to deposit polymeric materials on the sidewalls of an opening in the radiation sensitive imaging layer in a gradually tapered configuration. This way, the lateral width is reduced from the original width of the opening in the exposed and developed radiation sensitive imaging layer to the target lateral width.
  • the composition of the antireflective material can be tuned for attaining a desired reduction in the critical dimensions of the feature to be fabricated by the amount of sidewall taper used during the taper-etch step.
  • the plasma etching step due to the high temperatures induced by the plasma generated, can cause damage to the antireflective layer, and thus also introduce edge irregularities in the mask, which are transferred on to the features to be formed in the substrate layer.
  • a method for fabricating at least one feature, which has a target lateral width, in a substrate layer comprises the steps: depositing an amorphous carbon layer on the substrate layer; depositing a capping layer on the amorphous carbon layer; - depositing a first resist layer structure on the capping layer; fabricating at least one first opening in the first resist layer structure, the first opening having a first lateral width larger than the target lateral width; taper etching the capping layer through the at least one first opening in the first resist layer structure, thus forming at least one second opening in the capping layer that has a tapered lateral width, which reduces from the first lateral width at an interface to the first resist layer structure to the target lateral width at an interface to the amorphous carbon layer; etching at least one third opening, which has the target lateral width, into the amorphous carbon layer through the at least one second
  • the method according to the first aspect of the invention allows fabricating a feature with a target lateral width that is smaller than can be obtained with the used lithographic equipment. In comparison with known methods, it provides an increased resistance to temperatures typically used during processing, in particular, during a plasma etching step.
  • the increased temperature resistance is achieved by using a layer structure that comprises an amorphous carbon layer on the substrate layer, a capping layer on the amorphous carbon layer, and a first resist layer structure on the capping layer.
  • a carbon contribution to the etching process which is usually provided by a resist material, is provided by the amorphous carbon layer, which forms a hard mask on the substrate layer.
  • Another carbon contribution can be provided by relevant gases that are in the plasma.
  • the method of the invention thus involves depositing two intermediate layers between the resist layer structure and the substrate layer to be patterned by etching: one capping layer and one amorphous carbon layer. Additional layers can be present, as will be explained in the context of preferred embodiments further below.
  • substrate layer is not to be interpreted in a limited manner, such as necessarily requiring a layer or film structure obtained, for instance, by deposition of a distinguished layer on a substrate wafer.
  • a substrate layer in the sense of the present invention can also be formed by a substrate wafer as such, like a silicon wafer.
  • resist is used herein in short for photoresist, as is usual in the art.
  • depositing the first resist layer structure on the capping layer is performed by depositing a single resist layer, which provides a particularly simple resist layer structure and thus allows shorter processing times.
  • depositing the first resist layer structure comprises depositing a bottom antireflective coating (BARC) on the capping layer, and subsequently depositing a resist layer on the BARC layer.
  • BARC bottom antireflective coating
  • the use of a BARC layer minimizes reflection of light back into the resist layer during exposure, which would otherwise degrade the lateral solution of the lithography process.
  • the BARC is in one embodiment a polymer with carbon. This can be removed in the same way as the resist, thus saving extra processing steps and chemistry.
  • a method for fabricating at least one first feature and at least one second feature in a substrate layer, the first and second features having a target lateral width and a mutual target lateral pitch. The method comprises performing the process of the first aspect of the invention for fabricating at least one first feature in the substrate layer up until the step of etching at least one third opening.
  • a step of removing the first resist layer structure is performed, keeping, however, the capping layer with the at least one second opening and the amorphous carbon layer with the at least one third opening defined in the process of the first aspect of the invention. Furthermore, the following steps are performed: - depositing a second resist layer structure on the capping layer; fabricating at least one fourth opening in the second resist layer structure, the fourth opening having the first lateral width and being arranged at the target lateral pitch from the first feature; taper-etching the capping layer through the at least one fourth opening in the second resist layer structure, thus forming at least one fifth opening in the capping layer that has a tapered lateral width, which reduces from the first lateral width at an interface to the second resist layer structure to the target lateral width at an interface to the amorphous carbon layer; etching at least one sixth opening, which has the target lateral width, into the amorphous carbon layer through the at least one fifth opening in the capping layer; and etching the at least one first feature and
  • the method of the present of the invention allows providing neighboring first and second features with a mutual lateral distance (pitch) that is smaller than can be obtained by standard processing with a given lithographic equipment.
  • the first and second feature themselves can be formed with lateral widths that are smaller than can be achieved by standard processing with a given lithographic equipment.
  • the method of the second aspect of the invention makes use of the features fabricated during the processing according to the method of the first aspect of the invention with a larger pitch.
  • a second resist layer structure on the capping layer and repeating the formation of openings in the same manner as during the previous processing, but with a lateral offset, at least one second feature fabricated in the substrate layer with a desired target pitch with respect to the first embodiment.
  • a plurality of first features is fabricated and each second feature is arranged between a respective pair of neighboring first features at equal distance to each of the respective neighboring first features.
  • Figs. 1 to 6 show schematic cross sectional views of a substrate layer during different processing stages of an embodiment of the method of the first aspect of the invention, for fabricating exemplary features, which have a target lateral width;
  • Figs. 7 to 12 show schematic cross sectional views of a substrate layer during different processing stages of an embodiment of the method of the second aspect of the invention, for fabricating exemplary first and second features with a target lateral width and a mutual target lateral pitch.
  • Figs. 1 to 6 show schematic cross sectional views of a substrate layer 100 during different processing stages of an embodiment of the method of the first aspect of the invention, for fabricating exemplary features in the substrate layer 100, which have a target lateral width.
  • the substrate layer 100 is to be patterned by the fabrication of trenches with a target lateral width.
  • any feature can be fabricated by the method of the invention.
  • Fig. 1 shows a first intermediate processing step, in which the substrate layer 100 has been covered by a layer stack that is formed by an amorphous carbon layer 102, a capping layer 104, a bottom antireflective coating (BARC) layer 106, and a resist layer 108.
  • the BARC layer and the resist layer form a first resist layer structure 110.
  • the resist layer 108 is patterned by fabricating first openings 112, 114, and 116.
  • the first openings extend only through the resist layer itself, and not through the BARC layer.
  • Standard lithographic equipment and processing can be used for the formation of the first openings 112 to 116.
  • the processing of the first openings as such is thus well known to a person skilled in the art.
  • the first openings are generated with a first lateral width that is attainable with standard lithographic techniques.
  • a next step cf. Fig.
  • the capping layer 104 is taper-etched using a chemistry that at the same time opens the BARC layer 106, thus finishing the formation of first openings in the resist layer structure 110 and at the same time providing second openings 118 to 122 in the capping layer 104.
  • a dry etcher is advisable for achieving the best control of the critical dimensions: a CF 4 chemistry can be used for the BARC step, whereas the chemistry used for the taper etching depends on the capping material.
  • a CF 4 ZC x F y chemistry can be used for an oxide capping layer.
  • a chemistry based on CH x F y can be used for a nitride capping layer.
  • the chemistry used in the present processing generates a taper in the capping layer. That means, by way of example, that the second opening 118 in the capping layer 104 has the first lateral width of the first opening 112 at an interface 124 to the BARC layer 106 of the first resist layer structure 110, and a smaller, namely, a target lateral width at an interface 126 between the capping layer 104 and the amorphous carbon layer 102.
  • the inclination of the sidewalls between the two interfaces 124 and 126 can be set by appropriate structural and processing parameters.
  • the thickness of the capping layer can be selected to achieve a desired target lateral width at the interface 126.
  • the second openings 118 to 122 will have a target lateral width at the interface 126 to the carbon layer, which target lateral width is in fact smaller than the resolution limit of the lithographic equipment.
  • third openings 128 to 132 are etched in the amorphous carbon layer 102 through the first openings 112 to 116 and through the second openings 118 to 122. Since the tapered second openings 118 to 122 are used for etching the third openings 128 to 132, the lateral width of the latter openings in the amorphous carbon layer 102 has the smaller lateral width achieved by the taper-etching step. The result of this processing is shown in Fig. 4.
  • the resist layer 108 will also be etched at least in part. Since it is the patterning of the capping layer 104 that is decisive for the reduction of the lateral width from the first to the second openings, the resist layer 108 of the first resist layer structure 110 can be rather thin. If the resist layer 108 is chosen thin enough (not shown here), it will be completely removed during the step of etching the amorphous carbon layer 102. Subsequently, as shown in Fig. 5, the amorphous carbon layer 102 is used as a hard mask for etching the desired features with the reduced target lateral width. In the present embodiment, the features are formed by trenches 134 to 138.
  • the final reduced thickness of the amorphous carbon layer after this step depends on the resistance of the ⁇ -carbon hard mask to the etching chemistry and on the time requested to etch completely 134 to 138 trenches.
  • the capping layer material identical to the material of the substrate layer 100, the capping layer will be etched at the beginning of the step for etching the trenches 134 to 138, thus also removing the BARC layer 106 and any remaining parts of the resist layer 108.
  • Figs. 7 to 12 show schematic cross sectional views of a substrate layer 200 during different processing stages of an embodiment of the method of the second aspect of the invention, for fabricating exemplary first and second features with a target lateral width and a mutual target lateral pitch.
  • Fig. 7 shows the substrate layer 200 at a first processing stage, i.e., covered an amorphous carbon layer 202, a capping layer 204, and a resist layer 208.
  • a first processing stage i.e., covered an amorphous carbon layer 202, a capping layer 204, and a resist layer 208.
  • no BARC layer is used.
  • an alternative embodiment may make use of BARC layer to avoid or minimize reflections during exposure to light in the lithography processing.
  • first, second, and third openings 212 to 214, 218 to 222, and 228 to 232, respectively, are formed in the layer stack of the resist layer 208, the capping layer 204, and the amorphous carbon layer 202.
  • the resulting structure is shown in Fig. 8. It can be fabricated by lithography, using a taper-etch step in the capping layer 204, which is arranged on top of the amorphous carbon layer 202.
  • the capping layer is an oxide
  • the taper etching can be performed using an optimized C x F y chemistry.
  • the tapered etch step in the capping layer is followed by a vertical over-etch through the second openings.
  • a target lateral width can be achieved by accordingly choosing the capping-layer thickness. The larger the capping-layer thickness, the smaller target lateral width TW that can be achieved.
  • the resist layer 208 is stripped, and a second resist layer 240 is deposited and laterally structured for preparing the formation of second features in the substrate layer 200.
  • the second resist layer 240 is deposited on the capping layer 204 and provided with fourth openings 242 to 246.
  • the fourth openings 242 to 246 have the same lateral width W as the first openings 212 to 216. In other embodiments, the lateral width may be different.
  • the lateral pitch P between the fourth openings 242 and 244, and between the fourth openings 244 and 246 is chosen identical to that of the first openings, cf. Fig. 8.
  • the second openings are provided at equal lateral distance to the second and third openings fabricated during the previous processing described in the context of Fig. 8.
  • Fig. 10 the processing of Fig. 8 is repeated in the fourth openings for fabricating tapered fifth openings 248 to 252 in the capping layer 204 and sixth openings 254 to 258 in the amorphous carbon layer.
  • the lateral pitch P between the fourth openings 242 and 244, and between the fourth openings 244 and 246 can be chosen different from that of the first openings.
  • the resist layer 240 is removed.
  • a hard mask is produced, which is formed by the capping layer 204 and the amorphous carbon layer 202 and which has openings with the reduced target lateral width TW and the reduced target lateral pitch TP. These target values would not be available to conventional lithographic processing.
  • the capping layer 204 is fabricated from the same material as the substrate layer 200, the capping layer will be removed in the following etching step in parallel with the desired feature formation in the substrate layer 200.
  • the chemistry that should be used at this point corresponds to that known from conventional processing in lithographic techniques, using the carbon of the amorphous carbon layer in way as the carbon present in a resist layer would be used.
  • trenches 260 can be formed in the substrate layer 200 by using the third openings 228 to 232 and the sixth openings 254 to 258 in the amorphous carbon layer 202, cf. Fig. 12.
  • the second features have an identical shape as the first features.
  • the second features may differ from the first feature in their shape and/or cross-sectional profile. While the invention has been illustrated and described in detail in the drawings and foregoing description, such illustration and description are to be considered illustrative or exemplary and not restrictive; the invention is not limited to the disclosed embodiments.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Photosensitive Polymer And Photoresist Processing (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

La présente invention concerne un procédé de fabrication d'au moins un élément comportant une largeur latérale cible, dans une couche de substrat. Le procédé permet de fabriquer un élément avec une largeur latérale cible dans une couche de substrat qui est inférieure à celle obtenue avec l'équipement lithographique usuel. Par rapport aux procédés connus, la présente invention permet d'augmenter la résistance aux températures généralement utilisées pendant le traitement, en particulier pendant une étape de gravure par plasma. La meilleure résistance à la température est obtenue en utilisant une structure de couches qui comprend une couche de carbone amorphe sur la couche de substrat, une couche de couverture sur la couche de carbone amorphe et une première structure de couche d'enduit protecteur sur la couche de couverture. Dans cette structure de couches, une contribution de carbone au processus de gravure, qui est généralement réalisée par un matériau d'enduit protecteur, est réalisée par la couche de carbone amorphe, qui constitue un masque dur sur la couche de substrat.
PCT/EP2007/057899 2006-08-02 2007-07-31 Structure de masque dur innovante pour tracer des motifs sur des éléments dans des dispositifs semi-conducteurs Ceased WO2008015212A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP06300851 2006-08-02
EP06300851.0 2006-08-02

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WO2008015212A1 true WO2008015212A1 (fr) 2008-02-07

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2025076190A1 (fr) * 2023-10-06 2025-04-10 Applied Materials, Inc. Atténuation de courbure dans des gravures à base d'oxyde et de nitrure à rapport de forme élevé

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0416809A2 (fr) * 1989-09-08 1991-03-13 AT&T Corp. Méthode d'attaque de motifs de dimensions réduites pour circuits intégrés
US20040192060A1 (en) * 2003-03-20 2004-09-30 Maik Stegemann Method for fabricating a semiconductor structure
US20050167394A1 (en) * 2004-01-30 2005-08-04 Wei Liu Techniques for the use of amorphous carbon (APF) for various etch and litho integration scheme
US20060046483A1 (en) * 2004-08-31 2006-03-02 Abatchev Mirzafer K Critical dimension control for integrated circuits
US20060046200A1 (en) * 2004-09-01 2006-03-02 Abatchev Mirzafer K Mask material conversion

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0416809A2 (fr) * 1989-09-08 1991-03-13 AT&T Corp. Méthode d'attaque de motifs de dimensions réduites pour circuits intégrés
US20040192060A1 (en) * 2003-03-20 2004-09-30 Maik Stegemann Method for fabricating a semiconductor structure
US20050167394A1 (en) * 2004-01-30 2005-08-04 Wei Liu Techniques for the use of amorphous carbon (APF) for various etch and litho integration scheme
US20060046483A1 (en) * 2004-08-31 2006-03-02 Abatchev Mirzafer K Critical dimension control for integrated circuits
US20060046200A1 (en) * 2004-09-01 2006-03-02 Abatchev Mirzafer K Mask material conversion

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2025076190A1 (fr) * 2023-10-06 2025-04-10 Applied Materials, Inc. Atténuation de courbure dans des gravures à base d'oxyde et de nitrure à rapport de forme élevé

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