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WO2008005023A1 - Source de courant à faible perte de niveau et procédé de mise en œuvre de cette source de courant - Google Patents

Source de courant à faible perte de niveau et procédé de mise en œuvre de cette source de courant Download PDF

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Publication number
WO2008005023A1
WO2008005023A1 PCT/US2006/026673 US2006026673W WO2008005023A1 WO 2008005023 A1 WO2008005023 A1 WO 2008005023A1 US 2006026673 W US2006026673 W US 2006026673W WO 2008005023 A1 WO2008005023 A1 WO 2008005023A1
Authority
WO
WIPO (PCT)
Prior art keywords
current
transistor
coupled
receive
input device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US2006/026673
Other languages
English (en)
Inventor
Hassan Chaoui
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Semiconductor Components Industries LLC
Original Assignee
Semiconductor Components Industries LLC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Semiconductor Components Industries LLC filed Critical Semiconductor Components Industries LLC
Priority to PCT/US2006/026673 priority Critical patent/WO2008005023A1/fr
Publication of WO2008005023A1 publication Critical patent/WO2008005023A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is DC
    • G05F3/10—Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/26—Current mirrors
    • G05F3/262—Current mirrors using field-effect transistors only
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current 
    • G05F1/46—Regulating voltage or current  wherein the variable actually regulated by the final control device is DC
    • G05F1/56—Regulating voltage or current  wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices
    • G05F1/575—Regulating voltage or current  wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices characterised by the feedback circuit

Definitions

  • the present invention relates, in general, to electronics, and more particularly, to methods of forming semiconductor devices and structures.
  • a current source that minimizes the effect of the output voltage on the output current, that improves accuracy for low values of the voltage on the output terminal, and that minimizes variations in the output current resulting from switching the output current by an external PWM controller.
  • FIG. 1 schematically illustrates an embodiment of a portion of a light emitting diode system having a current source in accordance with the present invention
  • FIG. 2 schematically illustrates an enlarged plan view of a semiconductor device that includes the current source of FIG. 1 in accordance with the present invention.
  • current carrying electrode means an element of a device that carries current through the device such as a source or a drain of an MOS transistor or an emitter or a collector of a bipolar transistor or a cathode or anode of a diode
  • a control electrode means an element of the device that controls current through the device such as a gate of an MOS transistor or a base of a bipolar transistor.
  • FIG. 1 schematically illustrates a portion of an exemplary embodiment of a light emitting diode (LED) control system 10 that includes a current source 30.
  • Current source 30 controls a value of a current 18 through an LED 17 in order to control the light emitted by LED 17.
  • the exemplary embodiment of system 10 receives power, for example from a battery 11, between a power input terminal 12 and a power return terminal 13.
  • a PWM controller 27 and a power switch, such as a transistor 28, that is controlled by controller 27 usually are utilized to control the amount of time that current 18 flows through LED 17 in order to easily change the amount of the light emitted by LED 17.
  • PWM controller 27 may include a control input 24 that is utilized to control the duty cycle of the PWM drive signal used to control the switching of transistor 28.
  • PWM signals generally are a periodical square wave signal with a constant period and a variable duty cycle.
  • Current source 30 receives an input voltage for operating source 30 between a power input 21 and a power return 22.
  • Current source 30 includes a first current source 40 that provides a first reference current, a second current source 31 that provides a second reference current, an output device implemented as a transistor 36, a reference device implemented as a transistor 35, and a current mirror that includes a current mirror input device implemented as a transistor 43, and a current mirror output device implemented as a transistor 34.
  • current source 30 receives an input voltage, such as from LED 17, on an output 44 of source 30.
  • Current sources 40 and 31 form respective first and second reference currents 41 and 32 that are substantially equal in value. Since transistor 43 is connected in a diode configuration, transistor 43 operates in the saturated region of the characteristics of transistor 43 and current 41 flows through transistor 43 to form a gate-to-source voltage (Vgs) for transistor 43. Because of the substantially equal value of currents 32 and 41 in addition to the current mirror configuration of transistors 43 and 34, current 32 forces the Vgs of transistor 34 to be substantially equal to the Vgs of transistor 43, thus, the source voltage of transistor 34 follows and is substantially equal to the source voltage of transistor 43 which is substantially equal to the input voltage on output 44.
  • the current mirror of transistors 34 and 43 forms a reference voltage on a node 38 that is at the same potential relative to return 22 as the input voltage on output 44.
  • Vds drain-to- source voltage
  • the gate of transistors 35 and 36 are connected to the drain of transistor 34, thus, the Vgs of transistors 34 and 35 are equal. Since the Vds and Vgs voltages of transistors 35 and 36 are substantially equal, the current through transistor 36 is forced to equal the current through transistor 35 times the active area ratio between the two transistors.
  • the active area ratio is 1:1000 and transistors 35 and 36 function as a current mirror with the current through transistor 36 controlled by transistor 35 to be approximately one thousand (1000) times the value of current 32 that flows through transistor 35.
  • the current through transistor 36 is equal to current 41 plus current 18. Since current 41 is equal to current 32, current 18is approximately equal to nine hundred ninety nine (999) times the value of current 32.
  • the active area ratio may be different than 1:1000 and as long as the ratio is greater than 1:1.
  • substantially equal currents to flow through transistors 34 and 43 assists in forming the current through transistor 36 to be substantially constant as the value of the voltage on output 44 varies. Since the Vds and Vgs of transistors 35 and 36 are substantially equal, the value of the current through transistor 36 is substantially independent of the value of the voltage on output 44. Because the gates of transistors 35 and 36 are connected to the drain of transistor 34, the Vgs of transistors 35 and 36 is free to vary from a low value of approximately equal to the Vds (sat) of transistor 34 to an upper limit of approximately the value of the input voltage on input 21 minus the Vds (sat) of current source 31.
  • the Vds (sat) usually is understood to be the minimum voltage needed across a device in order to carry the current that is requested to flow through the device. Because the Vgs of transistors 35 and 36 is free to vary over such a range, the current mirror of transistors 35 and 36 can vary between operating in the saturated region of the characteristics of transistors 35 and 36 to operating in the linear region of those characteristics. For example if the input voltage on output 44 is lower than the Vds (sat) of transistor 36, such as the voltage from battery 11 being low, transistors 35 and 36 may operate in the linear region, and if the input voltage on output 44 is higher than the Vds (sat) of transistor 36, transistors 35 and 36 may operate in the saturated region.
  • source 30 can provide a substantially constant current through output 44 even if the value of the voltage on output 44 approaches zero regardless of whether transistors 35 and 36 are operating in the linear or saturated operating regions. It is believed that source 30 can provide the substantially constant value of current 18 for input voltage values on output 44 that are less than about one hundred milli-volts (100 mv) and even as low as approximately five milli-volts (5 mv). In one particular example embodiment, the value of current 18 was set to a value of about one milli-amp (1 ma) and source 30 controlled current 18 to be substantially constant as the value of the input voltage on output 44 decreased to approximately ten milli-volts (10 mv).
  • Forming source 30 to keep current 18 substantially constant for such low values of the input voltage on output 44 facilitates using a very low value for the voltage that is received on output 44.
  • the voltage on output 44 causes power dissipation within transistors 35 and 36. Lowering the value of this voltage reduces the power that is dissipated in transistors 35 and 36 and increases the efficiency of system 10.
  • forming source 30 to keep current 18 substantially constant for low values of the input voltage also facilitates using source 30 in a PWM application that switches current 18 on and off by switching transistor 28. In the off state, current 18 is substantially zero, but current 41 still flows through transistor 36. Current 41 is much smaller than current 18 when it is flowing.
  • a drain of transistor 43 is coupled to receive current 41 from current source 40.
  • a first terminal of current source 40 is coupled to receive the input voltage from input 21 and a second terminal is commonly connected to the gate and a drain of transistor 43 and to the gate of transistor 34.
  • a source of transistor 43 and a drain of transistor 36 are coupled to receive the input voltage from output 44.
  • Output 44 is connected to a source of transistor 43 and to a drain of transistor 36.
  • a source of transistor 36 is connected to receive the common voltage on voltage return 22.
  • a source of transistor 35 is connected to return 22.
  • the gate of transistor 35 is connected to the gate of transistor 36 and is connected to receive current 32.
  • a drain of transistor 35 is connected to a source of transistor 34.
  • the drain of transistor 34 is commonly connected to a first terminal of current source 31 and to a gate of transistor 35.
  • a second terminal of source 31 is connected to the first terminal of source 40.
  • FIG. 2 schematically illustrates an enlarged plan view of a portion of an embodiment of a semiconductor device or integrated circuit 50 that is formed on a semiconductor die 51.
  • Current source 30 is formed on die 51.
  • Die 51 may also include other circuits that are not shown in FIG. 2 for simplicity of the drawing.
  • Current source 30 and device or integrated circuit 50 are formed on die 51 by semiconductor manufacturing techniques that are well known to those skilled in the art.
  • a novel device and method is disclosed. Included, among other features, is using two current sources to form the current though a first current mirror and using the first current mirror to control the Vds of a second current mirror. Configuring the first current mirror to operate in the saturated region assists in controlling the Vds of the second current mirror. Coupling the second current mirror to operate in either the linear region or the saturated region assists in allowing the current source to operate at low values of an input voltage that is received on a current output of the current source. Additionally, forming transistors 35 and 36 have the same Vds and Vgs facilitates the current mirror of transistors 35 and 36 operating in either the linear or saturated regions.
  • current source 30 is described as being used in an LED system that is switched by a PWM controller, current source 30 may be used in any application that requires an accurate current source. More specifically the subject matter of the invention has been described for a particular N-channel MOS transistor structure, the method is directly applicable to bipolar transistors, as well as to other MOS transistors, BiCMOS, metal semiconductor FETs (MESFETs), HFETs, and other transistor structures. Additionally, the word “connected” is used throughout for clarity of the description, however, it is intended to have the same meaning as the word “coupled”. Accordingly, “connected” should be interpreted as including either a direct connection or an indirect connection.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Automation & Control Theory (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Nonlinear Science (AREA)
  • Control Of Electrical Variables (AREA)

Abstract

Dans un mode de réalisation, deux sources de courant sont utilisées pour contrôler un miroir de courant. Le miroir de courant contrôle un second miroir de courant afin de former un courant de sortie destiné à être pratiquement constant.
PCT/US2006/026673 2006-07-07 2006-07-07 Source de courant à faible perte de niveau et procédé de mise en œuvre de cette source de courant Ceased WO2008005023A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
PCT/US2006/026673 WO2008005023A1 (fr) 2006-07-07 2006-07-07 Source de courant à faible perte de niveau et procédé de mise en œuvre de cette source de courant

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/US2006/026673 WO2008005023A1 (fr) 2006-07-07 2006-07-07 Source de courant à faible perte de niveau et procédé de mise en œuvre de cette source de courant

Publications (1)

Publication Number Publication Date
WO2008005023A1 true WO2008005023A1 (fr) 2008-01-10

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PCT/US2006/026673 Ceased WO2008005023A1 (fr) 2006-07-07 2006-07-07 Source de courant à faible perte de niveau et procédé de mise en œuvre de cette source de courant

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2846463A1 (fr) * 2013-08-22 2015-03-11 Freescale Semiconductor, Inc. Commutateur de puissance à limitation de courant et consommation d'énergie de courant continu (CC) à zéro

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19612269C1 (de) * 1996-03-28 1997-08-28 Bosch Gmbh Robert Stromspiegelschaltung
US20040046537A1 (en) * 2002-09-09 2004-03-11 Olivier Charlon High output impedance current mirror with superior output voltage compliance

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19612269C1 (de) * 1996-03-28 1997-08-28 Bosch Gmbh Robert Stromspiegelschaltung
US20040046537A1 (en) * 2002-09-09 2004-03-11 Olivier Charlon High output impedance current mirror with superior output voltage compliance

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2846463A1 (fr) * 2013-08-22 2015-03-11 Freescale Semiconductor, Inc. Commutateur de puissance à limitation de courant et consommation d'énergie de courant continu (CC) à zéro
CN104426533A (zh) * 2013-08-22 2015-03-18 飞思卡尔半导体公司 具有限流和零直流(dc)功耗的电源开关
US9092043B2 (en) 2013-08-22 2015-07-28 Freescale Semiconductor, Inc. Power switch with current limitation and zero direct current (DC) power consumption

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