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WO2008004151A3 - Réseau d'alimentation - Google Patents

Réseau d'alimentation Download PDF

Info

Publication number
WO2008004151A3
WO2008004151A3 PCT/IB2007/052354 IB2007052354W WO2008004151A3 WO 2008004151 A3 WO2008004151 A3 WO 2008004151A3 IB 2007052354 W IB2007052354 W IB 2007052354W WO 2008004151 A3 WO2008004151 A3 WO 2008004151A3
Authority
WO
WIPO (PCT)
Prior art keywords
supply
power supply
supply network
grid
current spreader
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/IB2007/052354
Other languages
English (en)
Other versions
WO2008004151A2 (fr
Inventor
De Wiel Petrus J A M Van
Andrew T Appleby
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NXP BV
Original Assignee
NXP BV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NXP BV filed Critical NXP BV
Priority to CN2007800245755A priority Critical patent/CN101479848B/zh
Priority to JP2009517517A priority patent/JP2009543325A/ja
Priority to EP07789732A priority patent/EP2038927A2/fr
Priority to US12/306,898 priority patent/US7928567B2/en
Publication of WO2008004151A2 publication Critical patent/WO2008004151A2/fr
Publication of WO2008004151A3 publication Critical patent/WO2008004151A3/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Layout of the interconnection structure
    • H01L23/5286—Arrangements of power or ground buses
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Geometry (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

L'invention concerne un réseau d'alimentation (2) pour un circuit intégré, le réseau d'alimentation (2) comprenant une grille d'alimentation (4) ; une pluralité de plages d'alimentation (6), chaque plage d'alimentation (6) étant en contact électrique avec un bord de la grille d'alimentation (4) ; un élément de distribution de courant (8) pour au moins une de la pluralité de plages d'alimentation (6), chaque élément de distribution de courant (8) étant en contact électrique avec une plage d'alimentation (6) respective et la grille d'alimentation (4). Chaque élément de distribution de courant (8) est en outre dimensionné de façon à chevaucher une partie respective de la grille d'alimentation (4) et possède une résistance électrique inférieure à celle de la grille d'alimentation (4). Dans d'autres modes de réalisation, l'invention concerne un circuit intégré doté de ce réseau d'alimentation.
PCT/IB2007/052354 2006-06-30 2007-06-19 Réseau d'alimentation Ceased WO2008004151A2 (fr)

Priority Applications (4)

Application Number Priority Date Filing Date Title
CN2007800245755A CN101479848B (zh) 2006-06-30 2007-06-19 供电网络
JP2009517517A JP2009543325A (ja) 2006-06-30 2007-06-19 電力供給ネットワーク
EP07789732A EP2038927A2 (fr) 2006-06-30 2007-06-19 Réseau d'alimentation
US12/306,898 US7928567B2 (en) 2006-06-30 2007-06-19 Power supply network

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP06116377.0 2006-06-30
EP06116377 2006-06-30

Publications (2)

Publication Number Publication Date
WO2008004151A2 WO2008004151A2 (fr) 2008-01-10
WO2008004151A3 true WO2008004151A3 (fr) 2008-03-06

Family

ID=38723869

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/IB2007/052354 Ceased WO2008004151A2 (fr) 2006-06-30 2007-06-19 Réseau d'alimentation

Country Status (6)

Country Link
US (1) US7928567B2 (fr)
EP (1) EP2038927A2 (fr)
JP (1) JP2009543325A (fr)
CN (1) CN101479848B (fr)
TW (1) TW200824086A (fr)
WO (1) WO2008004151A2 (fr)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8594604B2 (en) 2009-12-18 2013-11-26 Nxp, B.V. Fringe capacitor circuit
US8581343B1 (en) * 2010-07-06 2013-11-12 International Rectifier Corporation Electrical connectivity for circuit applications
CN111443652B (zh) * 2020-03-24 2021-06-18 深圳市紫光同创电子有限公司 Cpld逻辑单元阵列的供电结构
US11749670B2 (en) * 2020-05-18 2023-09-05 Taiwan Semiconductor Manufacturing Company Limited Power switch for backside power distribution

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1143513A1 (fr) * 2000-04-03 2001-10-10 Nec Corporation Dispositif semi-conducteur à mémoire et son procédé de fabrication
US20020084516A1 (en) * 2000-10-27 2002-07-04 Efland Taylor R. Individualized low parasitic power distribution lines deposited over active integrated circuits
US20050212141A1 (en) * 2004-03-29 2005-09-29 Nec Electronics Corporation Semiconductor appartus

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1995017007A1 (fr) * 1993-12-14 1995-06-22 Oki America, Inc. Procede d'acheminement efficace et structure resultante pour circuits integres
US6495442B1 (en) * 2000-10-18 2002-12-17 Magic Corporation Post passivation interconnection schemes on top of the IC chips
US7230340B2 (en) 2000-10-18 2007-06-12 Megica Corporation Post passivation interconnection schemes on top of the IC chips
JP2004111796A (ja) 2002-09-20 2004-04-08 Hitachi Ltd 半導体装置
US20060239102A1 (en) * 2003-02-26 2006-10-26 Atsushi Saita Semiconductor integrated circuit device and its power supply wiring method
JP2005150556A (ja) * 2003-11-18 2005-06-09 Sharp Corp 半導体集積回路のレイアウト設計補助システム、配線のスリット生成方法および自動スリット生成装置

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1143513A1 (fr) * 2000-04-03 2001-10-10 Nec Corporation Dispositif semi-conducteur à mémoire et son procédé de fabrication
US20020084516A1 (en) * 2000-10-27 2002-07-04 Efland Taylor R. Individualized low parasitic power distribution lines deposited over active integrated circuits
US20050212141A1 (en) * 2004-03-29 2005-09-29 Nec Electronics Corporation Semiconductor appartus

Also Published As

Publication number Publication date
US7928567B2 (en) 2011-04-19
US20090289372A1 (en) 2009-11-26
TW200824086A (en) 2008-06-01
WO2008004151A2 (fr) 2008-01-10
CN101479848A (zh) 2009-07-08
EP2038927A2 (fr) 2009-03-25
JP2009543325A (ja) 2009-12-03
CN101479848B (zh) 2011-06-29

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