WO2008004034A1

WO2008004034A1 - Integrated amplifier bias circuit

Info

Publication number: WO2008004034A1
Application number: PCT/IB2006/052668
Authority: WO
Inventors: Jean-Jacques Bouny
Original assignee: Freescale Semiconductor Inc
Current assignee: NXP USA Inc
Priority date: 2006-06-30
Filing date: 2006-06-30
Publication date: 2008-01-10
Anticipated expiration: 2008-12-30

Abstract

A wireless communication unit (300) comprises a semiconductor power amplifier device (324) for receiving a radio frequency (RF) input signal and a bias circuit (326) arranged to provide a bias voltage to the semiconductor power amplifier device (324). The bias circuit (326) comprises a reference bias field effect transistor (FET) (Tl 405) having a source port coupled to ground, and gate port providing a bias control output to the semiconductor power amplifier device (324), and drain port coupled to a bias control signal. A buffer FET (T2 420) has a source port coupled to the bias control output of the bias circuit (326), a gate port coupled to the drain port of the reference bias FET (Tl 405), and a drain port coupled to a power supply. When applied to a high-power base station power amplifiers, using LDMOS RF FETs, the inventive concept provides improved thermal tracking, provides low impedance at baseband frequencies, as well as improved process tracking to known bias circuit topologies, as no tuning is required during manufacture.

Description

INTEGRATED AMPLIFIER BIAS CIRCUIT

Field of the Invention

The present invention relates to biasing radio frequency

(RF) and microwave power amplifiers (PAs) , suitable for use in wireless telecommunication applications. The invention is applicable to, but not limited to, a biasing circuit using laterally diffused metal oxide semiconductor (LDMOS) technology.

Background of the Invention

In the area of radio frequency (RF) and microwave amplifiers, a large number of transistors used in the signal amplification process are biased in class ^ΛAB' mode, to achieve a quasi-linear behaviour whilst maintaining an acceptable level of efficiency. However, it is known that, when biasing class ^ΛAB' bias transistors :

(i) The bias circuit should be able to deliver the correct bias level with an appropriate thermal compensation performance, in order to maintain a particular bias point, irrespective of the varying temperature at which the RF device is operating.

(ii) The bias circuit should provide low impedance

(ideally zero Ohms) in order to avoid any parasitic modulation appearing at the input of the RF transistor, which would generate undesirable memory effects and non- linearity .

(iii) The bias circuit should also be easy to tune or be configured such that undesired effects may be readily compensated for. (iv) The bias circuit should also have a low power consumption, to avoid any degradation in the overall power efficiency of the RF amplifier.

(v) The bias circuit should also support use with small reference voltages and/or low cost Digital-to- Analogue Converters (DACs) .

Existing bias circuit topologies typically provide some, but not all, of the above functionalities and can be separated in two implementation types. A first implementation is when the bias circuit topology is integrated with the RF amplifier and supports mechanisms to compensate for variation between devices integrated on the die .

Referring now to FIG. 1, a known integrated hybrid bipolar transistor (HBT) class AB bias circuit 100, as described in WO2004049555A2, is illustrated. The class AB bias circuit 100 comprises a biasing transistor 105 operably coupled to a RF power amplifier (PA) transistor

125, where a current (Ire_f) 120 is applied to the biasing transistor 105 via resistor 110. The gate (base) voltage is then applied to the RF PA transistor 125. The RF PA transistor 125 is provided a drain current (I_dRF) 135 via inductance 130. In this manner, the reference transistor 105 acts as a current mirror to the RF PA transistor 125 and therefore supports good thermal tracking and device compensation providing both transistors are on the same semiconductor die.

One advantage of this technique is that it is simple, accurate and low cost. However, it has high impedance if the biasing transistor is small. It also requires high power consumption if the biasing transistor is large enough to provide adequate speed as well as providing low impedance in a high RF power application.

Referring now to FIG. 2, a second bias circuit 200, as described with respect to a GaAs hybrid bipolar transistor (HBT) in US6,486,724 B2, comprises a similar structure to that illustrated in FIG. 1. The bias circuit 200 provides an external reference based either on diodes or transistors. This circuit 205 may use some kind of buffer/shaping amplifier 210 to apply the right voltage to the gate (base) of the RF PA transistor 125 using a resistor network 215, 220, 225, 230.

In this second implementation, the bias circuit being built externally to the RF transistor, the bias circuit has to be adjusted for each RF transistor in the amplifier chain. As the reference transistor is located away from the RF transistor, the thermal tracking is not fast enough to prevent thermal memory effects. Furthermore, in effect, the bias circuit needs to have fast thermal tracking (up to approximately IMHz) and to have a high frequency cut-off in order to maintain low impedance up to approximately 100MHz.

It is also noteworthy that the bias circuit needs to provide low power consumption and low impedance across all of its frequency range, which may extend up to and beyond 60MHz in some current wireless telecommunications applications. Low impedance may be achieved at video frequencies by using appropriate video decoupling (i.e. large capacitors) and a buffer/shaping amplifier. This typically implies the use of video amplifiers, which inherently have high power consumption and high complexity . Furthermore, it is known that biasing of multi die transistors is a problem, particularly at very high power levels (known as die pairing) , because a single transistor includes several die having different threshold voltages and therefore requiring different bias levels .

Thus, a need exists for a wireless communication unit and an integrated bias circuit to support fast thermal tracking and cancellation of memory effects.

Summary of the Invention

In accordance with aspects of the present invention, there is provided a wireless communication unit and a radio frequency integrated bias circuit, as defined in the appended Claims .

Brief Description of the Drawings

FIG. 1 illustrates a first known hybrid bipolar transistor (HBT) Class AB bias circuit; and

FIG. 2 illustrates a second known hybrid bipolar transistor (HBT) Class AB bias circuit.

Exemplary embodiments of the present invention will now be described, by way of example only, with reference to the accompanying drawings, in which:

FIG. 3 illustrates a wireless communication unit, adapted in accordance with one embodiment of the present invention; FIG. 4 illustrates an integrated bias circuit in accordance with one embodiment of the present invention; and

FIG. 5 illustrates an integrated circuit of a power amplifier and biasing circuit in accordance with one embodiment of the present invention.

Description of Embodiments of the Present Invention

In one embodiment of the present invention, a wireless communication unit comprises a semiconductor power amplifier device for receiving a radio frequency (RF) input signal; and a bias circuit arranged to provide a bias voltage to the semiconductor power amplifier device. The bias circuit comprises a reference bias field effect transistor (FET) having a source port coupled to ground, and gate port coupled to an output of the bias circuit, and drain port coupled to a bias control signal. A buffer FET has a source port coupled to the output of the bias circuit, a gate port coupled to the drain port of the reference bias transistor, and a drain port coupled to a power supply.

The provision of a reference bias FET followed by a buffer FET in the above manner may provide improved thermal tracking over known bias circuit topologies because it is integrated on the RF transistor die and the reference bias FET does not provide any power to the load, so its bias current remains constant.

The provision of a reference bias FET followed by a buffer FET in the above manner may provide improved process tracking over known bias circuit topologies, as no bias tuning is required during manufacture. The provision of a reference bias FET followed by a buffer FET in the above manner may provide low impedance at base band frequencies because of the high gain of the loop reference/buffer FETs, especially when the control is a current source (as a high impedance leads to a high gain) . In effect, as the bias circuit operates as a kind of looped power supply, where the output impedance may be considered as being divided by the loop gain, thereby improving power consumption and efficiency of the power amplifier circuit.

In one embodiment of the present invention, the reference bias circuit and at least one power amplifier transistor are integrated onto the same die. In this manner, the reference bias FET and buffer FET find particular applicability when integrated with high-power base station power amplifiers (FETs) using LDMOS RF PA transistors. In this manner, the bias circuit transistors also support a multi-die configuration, thereby being particularly useful with very high power

(up to and beyond 100W) transistor designs.

In one embodiment of the present invention, the reference bias FET of the bias circuit may be a scaled version of the at least one power amplifier transistor (FET) in order to insure process variation compensation.

In one embodiment of the present invention, the FETs may be laterally diffused metal oxide semiconductor (LDMOS) field effect transistors. In one embodiment of the present invention, the bias circuit may be arranged to bias the power amplifier transistor in a Class AB mode. In one embodiment of the present invention, the bias circuit may be arranged to provide a low impedance voltage source, substantially equivalent to a gate voltage of the reference bias FET, to the semiconductor power amplifier transistor.

In one embodiment of the present invention, the reference bias FET and the semiconductor power amplifier transistor may be arranged to function as a high power current mirror .

In one embodiment of the present invention, the drain current (IdRF) of the semiconductor power transistor may be arranged to be proportional to a drain current (Ire_f) of the reference bias FET, where the current ratio is the scaling ratio between the power transistor and the reference bias FET, in effect the basic premise of the current mirror.

In one embodiment of the present invention, a radio frequency power amplifier integrated circuit comprises at least one semiconductor power amplifier for receiving a radio frequency (RF) input signal; and a bias circuit arranged to provide a bias voltage to the at least one semiconductor power amplifier transistor. The bias circuit comprises a reference bias field effect transistor (FET) having a source port coupled to ground, and gate port coupled to an output of the bias circuit and drain port coupled to a bias control signal. A buffer FET has a source port coupled to the output of the bias circuit, a gate port coupled to the drain port of the reference bias FET, and a drain port coupled to a power supply.

Embodiments of the present invention propose an integrated circuit topology aimed to address the aforementioned problems encountered in class AB bias circuit designs. Advantageously, the proposed integrated circuit topology aims to provide good compensation of variable device effects, sometimes referred to as process variation compensation, good thermal compensation, as well as low power consumption, high speed, and low impedance .

Thus, the proposed integrated circuit topology may allow integration of a bias circuit that is suitable for use with a high power radio frequency (RF) transistor, at a low manufacturing cost for both the transistor manufacturer and the wireless communication unit manufacturer (for example reduced or no tuning of the RF PA is required) . This is in contrast to the known prior art that uses very low power Gallium Arsenide (GaAs) hybrid bipolar transistors (HBT) intended solely for use as gain control. The known bias circuits do not support low impedance with small transistors, because of their use of bipolar transistor and associated resistors.

One embodiment of the present invention will be described in terms of a wireless communication unit capable of operation in accordance with the 3^rd generation cellular communication standard, as defined by the third generation partnership project (3GPP) . However, it will be appreciated by a skilled artisan that the inventive concept herein described may be embodied in any type of radio frequency amplifier arrangement where improving the efficiency or thermal tracking of one and/or more power amplifier stage (s) using class AB biasing is important.

Referring now to FIG. 3, there is shown a block diagram of a wireless communication unit 300, adapted to support the inventive concept of the preferred embodiments of the present invention. For example, the wireless communication unit 300 comprises an antenna 302, preferably coupled to a duplex filter or antenna switch 304 that provides isolation between a receiver chain 310 and a transmitter chain 320 within the wireless communication unit 300. As also known in the art, and for completeness, the receiver chain 310 typically includes a receiver front-end circuit 306 (effectively providing reception, filtering and intermediate or baseband frequency conversion) . The receiver front-end circuit is serially coupled to a signal processing function 308, typically implemented as a digital signal processor (DSP) . An output from the signal processing function 308 is provided to a suitable user interface 330 comprising, say, a speaker and/or display, and an input device such as a microphone and/or keypad.

The user interface 330 is operably coupled to a memory unit 316, and a timer 318 via a controller 314. The controller 314 is also coupled to the receiver front-end circuit 306 and the signal processing function 308. The controller 314 is coupled to the memory device 316 for storing operating regimes, such as decoding/encoding functions and the like. A timer 318 is typically coupled to the controller 314 to control the timing of operations

(transmission or reception of time-dependent signals) within the wireless communication unit 300. As regards the transmit chain 310, the input device is coupled to a transmitter/modulation circuit 322 via the signal processing function 308 (or 328 if the transmit and receive portions were distinctly implemented) . The transmitter/modulation circuitry 322 and receiver front- end circuitry 306 comprise frequency up-conversion and frequency down-conversion functions (not shown) . Thereafter, the transmit signal is passed through a power amplifier 324 to be radiated from the antenna 302. The transmitter/modulation circuit 322 and the power amplifier 324 are operationally responsive to the controller, with an output from the power amplifier coupled to the duplex filter or antenna switch 304.

In accordance with embodiments of the present invention, the power amplifier 324 is biased using bias circuit 326, which applies a bias control voltage (or current) to an input port 327 of the power amplifier 324 and an output port 328 of the power amplifier 324, as further described below with respect to FIG. 4 and FIG. 5.

In one embodiment of the present invention, the bias circuit 326 is fully integrated with high power laterally diffused metal oxide semiconductor (LDMOS) RF field effect transistors (FETs) . In particular, a high gain loop is arranged between two biasing FETs, thereby enabling the bias circuit 326 to achieve low impedance, high speed, low power consumption, and good thermal compensation and device variation compensation

It will be appreciated that the various components and circuits within the wireless communication unit 300 may be arranged in any suitable functional topology in order to utilise the inventive concept of the present invention. Furthermore, the various components within the wireless communication unit 300 can be realised in discrete or integrated component form, with an ultimate structure therefore being merely an application-specific selection.

Referring now to FIG. 4, the power amplifier bias circuit 326 of FIG. 3 is shown in greater detail. The power amplifier bias circuit 326 according to embodiments of the present invention comprises an arrangement of two metal oxide semiconductor (MOS) field effect transistors, Tl 405 and T2 420, arranged such that the drain of the reference bias FET Tl 405 is operably coupled to the gate of the buffer FET T2 420. The gate of the reference bias FET is operably coupled to the source port of the buffer FET T2 420. In one embodiment of the present invention, both the reference bias FET Tl 405 and the buffer FET T2 420 are scaled versions of the RF power amplifier/ transistor 425 to be biased. In the context of the present invention, a skilled artisan will appreciate that a high power RF transistor is typically built by placing in parallel a large number of elementary transistors, using one or a small number of the same elementary transistors to build the so-called ^Λscaled' version of the RF FET.

In this manner, the bias FET 405 is used as a reference transistor, and is configured to have a bias point

(receiving a quiescent current) that is fixed by a resistor 410 and voltage source, or alternatively by a current source. In this configuration, the (preferably

LDMOS) FET T2 420 acts as a buffer for the reference bias

(preferably LDMOS) FET Tl 405 and is arranged to provide a current to the load (for example RF PA 324) when necessary. Notably, both the bias FET Tl 405 and the buffer FET T2 420 are arranged in a loop configuration to ensure that the (Vbias) voltage on the reference controls the output voltage 440. In this manner, the output impedance is divided by the gain of the loop.

In one embodiment of the present invention, the loop concept may be considered as the following: if a change in voltage appears at the output of the bias circuit (error) , it appears on the gate of the reference bias FET. Hence, the error voltage is multiplied and applied to the gate of the buffer (gain being gm*Rd, Rd being very high if the control is a current source) . Such an amplified error voltage will then appear on the source of the buffer, in an opposite phase to the initial error voltage, and therefore tends to cancel the error voltage.

As will be appreciated by a skilled artisan, the bias circuit of the present invention may be understood as providing a low impedance voltage source substantially providing a voltage equal to the gate voltage of the reference bias FET Tl 405, as any difference tends to appear to be cancelled by the loop, as explained above.

Similarly, it can also be appreciated that the bias circuit of the present invention may be understood as a high power current mirror, the two sides of the current mirror being the RF PA transistor 326 and the reference bias FET Tl 405, where the drain (collector) current I_dRF 335 is a replica of I_re_f 415, according to the size ratio

(where the size ration may be understood as being a transistor periphery ratio, or number of elementary transistor ratio) . The control of the bias level of the reference bias FET Tl 405 is the drain (collector) I_ref current 415, which in embodiments of the present invention may be set either externally to the RF PA (and/or the bias circuit) IC or internally to the IC.

Advantageously, in one embodiment of the present invention when the bias circuit is integrated on the same die as the RF PA transistor 326, the reference bias FET Tl 405 is configured to provide good part-to-part compensation, or process variation compensation. The bias circuit designer then configures the bias circuit

326 so that only the drain (collector) current I_ref 415 is set through the series resistor 410, the external voltage, or an external current source. Thus, there is no need to adjust the quiescent current of each of a plurality of RF power transistors in a power amplifier chain, thereby saving manufacturing time and cost.

In addition, the bias circuit 326 also concurrently provides significant thermal compensation improvement. It is noteworthy that this thermal compensation is achieved very fast compared to any potential external compensation circuit. This also provides an advantage over known bias circuits by reducing memory effects, whilst improving the ability to linearise the RF PA 324.

In one embodiment of the present invention, the reference bias FET Tl 405 may be chosen to be a very small size, thereby ensuring that the drain (collector) current I_re_f

415 may be very small. This allows low power consumption of the complete bias circuit 326, whilst the output impedance is divided by the total loop gain, which in turn allows very low impedances to be achieved even with small transistors.

In one embodiment of the present invention, the frequency cut-off of such an arrangement is high, even when loaded with a high capacitor (not shown) . For instance, a cutoff frequency of 100MHz can be achieved with two transistors being scaled down in size (sometimes referred to as transistor periphery or power-handling capability) , say by 200 times, compared with the RF PA transistor 324.

Referring now to FIG. 5, an integrated circuit comprising a power amplifier and bias circuit 500 in accordance with one embodiment of the present invention is illustrated. A single stage RF power amplifier transistor 324 is biased according to the inventive concept of the present invention. In one example, it has been found that the RF power at the output of the transistor may be generated up to IOOW at 2.0GHz, with current consumption at full power being in the range of 7.0A. Thus, such a circuit is particularly suited to a base station power amplifier, which is required to support such high power transmissions. In this case, the total consumption of the bias circuit has been measured at less than 1.5mA.

Thus, employing a biasing circuit according to the aforementioned design allows supply of a bias current through small low cost voltage reference or through small Digital-to-Analogue Converters (not shown) , following the use of low power consumption biasing transistors. As such, the biasing circuit has minimal impact on the overall power efficiency of the power amplifier circuit. It is also noteworthy that, as the biasing circuit is very small and utilises low power transistors, it does not require any increase in die size. Thus, in integrated circuit design and manufacture, the biasing circuit may be located in a ^Λdead' (free) zone of the RF die, and therefore is cost neutral in terms of silicon area .

It is within the contemplation of the invention that, although one embodiment of the present invention has been described with reference to LDMOS technology, it is envisaged that the inventive concept is equally applicable to any field effect transistor, particularly any high power MOS transistor technology.

Advantageously, the current consumption in the aforementioned embodiments remains low. Furthermore, a skilled artisan will appreciate that the proposed new topology is very easy to integrate using only one ^Λtype' of active device (i.e. only using LDMOS and thereby simplifying the process and reducing the cost) . Furthermore, this topology can be implemented using the same type of device as the RF power amplifier transistor to be biased. In this case, the bias level that is generated is effectively self-compensating, taking into account any device variations.

A skilled artisan will appreciate that alternative circuit configurations, elements and devices than those illustrated in FIG. 4 and FIG. 5 may be employed that utilise the inventive concept of the present invention, without necessarily utilising the same connections or topographies between circuit elements. It will be understood that the improved wireless communication unit and integrated bias control circuit, therefor, as described above, aims to provide one or more of the following advantages: (i) The inventive concept provides improved thermal tracking over known bias circuit topologies.

(ii) The inventive concept provides improved process tracking over known bias circuit topologies, as no tuning is required during manufacture. (iϋ) The inventive concept provides low impedance at baseband frequencies.

(iv) The inventive concept finds particular applicability with integration in high-power base station power amplifiers using LDMOS RF transistors. (v) The inventive concept supports a multi- die configuration, thereby being particularly useful with very high power transistor designs.

In particular, it is envisaged that the aforementioned inventive concept may be applied by a semiconductor manufacturer to any power amplifier circuit that employs

LDMOS technology or similar. It is further envisaged that, for example, a semiconductor manufacturer may employ the inventive concept in a design of a stand-alone power amplifier device and associated bias control circuit, and/or an application-specific integrated circuit (ASIC) and/or any other sub-system element capable of use in a radio frequency wireless communication unit.

It will be appreciated that any suitable distribution of functionality between different functional units or controllers may be used without detracting from the inventive concept herein described. Hence, references to specific functional devices or elements are only to be seen as references to suitable means for providing the described functionality, rather than indicative of a strict logical or physical structure or organization.

Aspects of the invention may be implemented in any suitable form including hardware, software, firmware or any combination of these. The elements and components of an embodiment of the invention may be physically, functionally and logically implemented in any suitable way. Indeed, the functionality may be implemented in a single unit or IC, in a plurality of units or ICs or as part of other functional units.

Although the present invention has been described in connection with some embodiments, it is not intended to be limited to the specific form set forth herein. Rather, the scope of the present invention is limited only by the accompanying claims. Additionally, although a feature may appear to be described in connection with particular embodiments, one skilled in the art would recognize that various features of the described embodiments may be combined in accordance with the invention. In the claims, the term ^Λcomprising' does not exclude the presence of other elements or steps.

Furthermore, although individual features may be included in different claims, these may possibly be advantageously combined, and the inclusion in different claims does not imply that a combination of features is not feasible and/or advantageous. Also, the inclusion of a feature in one category of claims does not imply a limitation to this category, but rather indicates that the feature is equally applicable to other claim categories, as appropriate .

Furthermore, the order of features in the claims does not imply any specific order in which the features must be performed and in particular the order of individual steps in a method claim does not imply that the steps must be performed in this order. Rather, the steps may be performed in any suitable order. In addition, singular references do not exclude a plurality. Thus, references to "a", "an", "first", "second" etc. do not preclude a plurality.

Thus, an improved wireless communication unit and power amplifier integrated circuit have been described, wherein the aforementioned disadvantages with prior art arrangements have been substantially alleviated.

Claims

Claims (PCT)

1. A wireless communication unit (300) comprising: a semiconductor power amplifier device (324) for receiving a radio frequency (RF) input signal; and a bias circuit (326) arranged to provide a bias voltage to the semiconductor power amplifier device (324), wherein the wireless communication unit (300) is characterised in that the bias circuit (326) comprises: a reference bias field effect transistor (FET) (Tl 405) having a source port coupled to ground, and gate port coupled to an output of the bias circuit (326), and drain port coupled to a bias control signal; and a buffer field effect transistor (FET) (T2 420) having a source port coupled to the output of the bias circuit (326), a gate port coupled to the drain port of the reference bias FET (Tl 405) , and a drain port coupled to a power supply.

2. A wireless communication unit (300) according to Claim 1 further characterised in that the semiconductor power amplifier device (324) comprises at least one power amplifier transistor integrated onto the same die as the bias circuit (326) .

3. A wireless communication unit (300) according to Claim 1 or Claim 2 further characterised in that the at least one FET (Tl 405, T2 420) of the bias circuit (326) is a scaled version of at least one power amplifier FET of the semiconductor power amplifier device (324) .

4. A wireless communication unit (300) according to any preceding Claim further characterised in that the FETs are laterally diffused metal oxide semiconductor (LDMOS) transistors.

5. A wireless communication unit (300) according to any preceding Claim further characterised in that the semiconductor power amplifier device comprises a high power radio frequency power amplifier.

6. A wireless communication unit (300) according to any preceding Claim further characterised in that the bias circuit is arranged to bias at least one power amplifier transistor of the semiconductor power amplifier device (324) in a Class AB mode.

7. A wireless communication unit (300) according to any preceding Claim further characterised in that the bias circuit is arranged to provide a low impedance voltage source substantially equivalent to a gate voltage of the reference bias FET (Tl 405) to the power amplifier device (324) .

8. A wireless communication unit (300) according to any preceding Claim further characterised in that the reference bias FET (Tl 405) and at least one power amplifier transistor of the power amplifier device (324) function as a high power current mirror.

9. A wireless communication unit (300) according to Claim 8 further characterised in that the drain current (I_dRF) of the at least one power amplifier transistor is arranged to be proportional to a drain current (Ire_f) °f the reference bias FET (415) .

10. A radio frequency power amplifier integrated circuit comprising: a semiconductor power amplifier device (324) for receiving a radio frequency (RF) input signal; and a bias circuit (326) arranged to provide a bias voltage to the semiconductor power amplifier device (324), wherein the radio frequency power amplifier integrated circuit is characterised in that the bias circuit (326) comprises: a reference bias field effect transistor (FET) (Tl 405) having a source port coupled to ground, and gate port coupled to an output of the bias circuit (326), and drain port coupled to a bias control signal; and a buffer FET (T2 420) having a source port coupled to the output of the bias circuit (326), a gate port coupled to the drain port of the reference bias FET (Tl 405), and a drain port coupled to a power supply.

11. A radio frequency power amplifier integrated circuit according to Claim 10 further characterised in that the semiconductor power amplifier device (324) comprises at least one power amplifier transistor integrated onto the same die as the bias circuit (326) .

12. A radio frequency power amplifier integrated circuit according to Claim 10 or Claim 11 further characterised in that at least one FET (Tl 405, T2 420) of the bias circuit (326) is a scaled version of at least one power amplifier field effect transistor of the semiconductor power amplifier device (324) .

13. A radio frequency power amplifier integrated circuit according to any of preceding Claims 10 to 12 further characterised in that the FETs are laterally diffused metal oxide semiconductor (LDMOS) transistors.

14. A radio frequency power amplifier integrated circuit according to any of preceding Claims 10 to 14 further characterised in that the power amplifier device (324) comprises a high power radio frequency power amplifier .

15. A radio frequency power amplifier integrated circuit according to any of preceding Claims 10 to 14 further characterised in that the bias circuit is arranged to bias at last one power amplifier transistor of the semiconductor power amplifier device (324) in a Class AB mode.

16. A radio frequency power amplifier integrated circuit according to any of preceding Claims 10 to 15 further characterised in that the bias circuit is arranged to provide a low impedance voltage source substantially equivalent to a gate voltage of the reference bias FET (Tl 405) to the power amplifier device (324) .

17. A radio frequency power amplifier integrated circuit according to any of preceding Claims 10 to 16 further characterised in that the reference bias FET (Tl 405) and at least one power amplifier transistor of the semiconductor power amplifier device (324) function as a high power current mirror.

18. A radio frequency power amplifier integrated circuit according to Claim 17 further characterised in that the drain current (I_dRF) of the at least one power amplifier transistor is arranged to be proportional to a drain current (I_re_f) °f the reference bias FET (415) .