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WO2008093399A1 - 情報処理システムおよび情報処理方法 - Google Patents

情報処理システムおよび情報処理方法 Download PDF

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Publication number
WO2008093399A1
WO2008093399A1 PCT/JP2007/051457 JP2007051457W WO2008093399A1 WO 2008093399 A1 WO2008093399 A1 WO 2008093399A1 JP 2007051457 W JP2007051457 W JP 2007051457W WO 2008093399 A1 WO2008093399 A1 WO 2008093399A1
Authority
WO
WIPO (PCT)
Prior art keywords
information processing
processing system
utilization information
storage part
utilization
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2007/051457
Other languages
English (en)
French (fr)
Inventor
Takashi Toyoshima
Shuji Yamamura
Atsushi Mori
Takashi Aoki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP2008555969A priority Critical patent/JP4491500B2/ja
Priority to PCT/JP2007/051457 priority patent/WO2008093399A1/ja
Publication of WO2008093399A1 publication Critical patent/WO2008093399A1/ja
Priority to US12/510,510 priority patent/US8671246B2/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0862—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with prefetch
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F8/00—Arrangements for software engineering
    • G06F8/40—Transformation of program code
    • G06F8/41—Compilation
    • G06F8/44—Encoding
    • G06F8/443—Optimisation
    • G06F8/4441—Reducing the execution time required by the program code
    • G06F8/4442—Reducing the number of cache misses; Data prefetching

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • Memory System Of A Hierarchy Structure (AREA)

Abstract

　情報処理システム（１）のキャッシュ（２０）は、プリフェッチされたデータがアクセスされたか否かを示す利用情報と、プリフェッチする原因となった命令を一意に識別する命令識別子とを対応付けて格納する利用情報格納部（２０ａ）を備える。このような構成のもと、情報処理システム（１）は、プリフェッチされたデータの利用情報を利用情報格納部（２０ａ）に書き込む。そして、情報処理システム（１）は、ＣＰＵ（１０）からプリフェッチされたデータに対してアクセスが行われた場合には、利用情報をセットする。その後、情報処理システム（１）は、キャッシュ（２０）のデータが破棄される際に、破棄されるデータの利用情報を利用情報格納部（２０ａ）から読み出す。具体的には、情報処理システム（１）は、利用情報格納部（２０ａ）から利用情報を読み出し、利用されたか否かを判別してプリフェッチミスを検出する。
PCT/JP2007/051457 2007-01-30 2007-01-30 情報処理システムおよび情報処理方法 Ceased WO2008093399A1 (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2008555969A JP4491500B2 (ja) 2007-01-30 2007-01-30 演算処理装置、情報処理装置及び演算処理装置の制御方法
PCT/JP2007/051457 WO2008093399A1 (ja) 2007-01-30 2007-01-30 情報処理システムおよび情報処理方法
US12/510,510 US8671246B2 (en) 2007-01-30 2009-07-28 Information processing system and information processing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2007/051457 WO2008093399A1 (ja) 2007-01-30 2007-01-30 情報処理システムおよび情報処理方法

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US12/510,510 Continuation US8671246B2 (en) 2007-01-30 2009-07-28 Information processing system and information processing method

Publications (1)

Publication Number Publication Date
WO2008093399A1 true WO2008093399A1 (ja) 2008-08-07

Family

ID=39673719

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2007/051457 Ceased WO2008093399A1 (ja) 2007-01-30 2007-01-30 情報処理システムおよび情報処理方法

Country Status (3)

Country Link
US (1) US8671246B2 (ja)
JP (1) JP4491500B2 (ja)
WO (1) WO2008093399A1 (ja)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014067250A (ja) * 2012-09-26 2014-04-17 Nec Corp メモリアクセス制御装置、メモリアクセス制御システム、及び、メモリアクセス制御方法
JP2016130948A (ja) * 2015-01-14 2016-07-21 富士通株式会社 演算処理装置および演算処理装置の制御方法
US11003581B2 (en) 2018-07-19 2021-05-11 Fujitsu Limited Arithmetic processing device and arithmetic processing method of controlling prefetch of cache memory

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US8583894B2 (en) * 2010-09-09 2013-11-12 Advanced Micro Devices Hybrid prefetch method and apparatus
US8949579B2 (en) * 2010-10-04 2015-02-03 International Business Machines Corporation Ineffective prefetch determination and latency optimization
CN102566936B (zh) * 2010-12-28 2015-04-29 联想(北京)有限公司 一种磁盘数据读取方法、装置及磁盘驱动装置
US20150286571A1 (en) * 2014-04-04 2015-10-08 Qualcomm Incorporated Adaptive cache prefetching based on competing dedicated prefetch policies in dedicated cache sets to reduce cache pollution
JP6252348B2 (ja) * 2014-05-14 2017-12-27 富士通株式会社 演算処理装置および演算処理装置の制御方法
US9910880B2 (en) 2014-07-16 2018-03-06 Wipro Limited System and method for managing enterprise user group
US10310981B2 (en) * 2016-04-07 2019-06-04 Advanced Micro Devices, Inc. Method and apparatus for performing memory prefetching
US20210390053A1 (en) * 2020-06-15 2021-12-16 Micron Technology, Inc. Host-Assisted Memory-Side Prefetcher
US11409657B2 (en) 2020-07-14 2022-08-09 Micron Technology, Inc. Adaptive address tracking
US11422934B2 (en) 2020-07-14 2022-08-23 Micron Technology, Inc. Adaptive address tracking
US11080283B1 (en) * 2020-09-29 2021-08-03 Atlassian Pty Ltd. Systems and methods for selectively prefetching data
US11366749B2 (en) * 2020-11-10 2022-06-21 Western Digital Technologies, Inc. Storage system and method for performing random read
US12399650B2 (en) * 2023-02-01 2025-08-26 SanDisk Technologies, Inc. Data storage device and method for host-assisted deferred defragmentation and system handling

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JPS63318654A (ja) * 1987-06-23 1988-12-27 Fujitsu Ltd 中間バッファリプレ−ス決定方式
JPH09319652A (ja) * 1996-03-28 1997-12-12 Hitachi Ltd 先読み制御方法
JP2001331793A (ja) * 2000-05-22 2001-11-30 Fuji Xerox Co Ltd 画像処理装置及びキャッシュメモリ
JP2002215456A (ja) * 2001-01-23 2002-08-02 Nec Corp 情報処理装置

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JPS63318654A (ja) * 1987-06-23 1988-12-27 Fujitsu Ltd 中間バッファリプレ−ス決定方式
JPH09319652A (ja) * 1996-03-28 1997-12-12 Hitachi Ltd 先読み制御方法
JP2001331793A (ja) * 2000-05-22 2001-11-30 Fuji Xerox Co Ltd 画像処理装置及びキャッシュメモリ
JP2002215456A (ja) * 2001-01-23 2002-08-02 Nec Corp 情報処理装置

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014067250A (ja) * 2012-09-26 2014-04-17 Nec Corp メモリアクセス制御装置、メモリアクセス制御システム、及び、メモリアクセス制御方法
JP2016130948A (ja) * 2015-01-14 2016-07-21 富士通株式会社 演算処理装置および演算処理装置の制御方法
US11003581B2 (en) 2018-07-19 2021-05-11 Fujitsu Limited Arithmetic processing device and arithmetic processing method of controlling prefetch of cache memory

Also Published As

Publication number Publication date
JPWO2008093399A1 (ja) 2010-05-20
JP4491500B2 (ja) 2010-06-30
US20090287884A1 (en) 2009-11-19
US8671246B2 (en) 2014-03-11

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