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WO2008091923A3 - Processus d'extraction de résidu de gravure dans la fabrication de semi-conducteurs - Google Patents

Processus d'extraction de résidu de gravure dans la fabrication de semi-conducteurs Download PDF

Info

Publication number
WO2008091923A3
WO2008091923A3 PCT/US2008/051758 US2008051758W WO2008091923A3 WO 2008091923 A3 WO2008091923 A3 WO 2008091923A3 US 2008051758 W US2008051758 W US 2008051758W WO 2008091923 A3 WO2008091923 A3 WO 2008091923A3
Authority
WO
WIPO (PCT)
Prior art keywords
electrically conductive
dielectric layer
semiconductor fabrication
conductive region
steps
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US2008/051758
Other languages
English (en)
Other versions
WO2008091923A2 (fr
Inventor
Russell T. Herrin
Peter J. Lindgren
Anthony K. Stamper
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of WO2008091923A2 publication Critical patent/WO2008091923A2/fr
Anticipated expiration legal-status Critical
Publication of WO2008091923A3 publication Critical patent/WO2008091923A3/fr
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
    • H01L23/5223—Capacitor integral with wiring layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041—Cleaning
    • H01L21/02057—Cleaning during device manufacture
    • H01L21/0206—Cleaning during device manufacture during, before or after processing of insulating layers
    • H01L21/02063—Cleaning during device manufacture during, before or after processing of insulating layers the processing being the formation of vias or contact holes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D1/00—Resistors, capacitors or inductors
    • H10D1/60—Capacitors
    • H10D1/68—Capacitors having no potential barriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

L'invention concerne une structure semi-conductrice et ses procédés de fabrication. Un procédé de fabrication de semi-conducteurs comporte l'étape consistant à obtenir une structure. Une structure comporte (a) une couche diélectrique, (b) une première région électriquement conductrice enfouie dans la couche diélectrique, la première région électriquement conductrice comprenant un premier matériau électriquement conducteur, et (c) une seconde région électriquement conductrice enfouie dans la couche diélectrique, la seconde région électriquement conductrice comprenant un second matériau électriquement conducteur différent du premier matériau électriquement conducteur. Le procédé comporte en outre les étapes de création d'un premier trou et d'un second trou dans la couche diélectrique se traduisant par l'exposition de la première et la seconde région électriquement conductrice à un environnement ambiant à travers le premier trou et le second trou, respectivement. Ensuite, le procédé comporte en outre l'étape d'application d'un solvant de base sur les parois inférieures et les parois latérales du premier trou et du second trou.
PCT/US2008/051758 2007-01-23 2008-01-23 Processus d'extraction de résidu de gravure dans la fabrication de semi-conducteurs Ceased WO2008091923A2 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/626,054 2007-01-23
US11/626,054 US20080174015A1 (en) 2007-01-23 2007-01-23 Removal of etching process residual in semiconductor fabrication

Publications (2)

Publication Number Publication Date
WO2008091923A2 WO2008091923A2 (fr) 2008-07-31
WO2008091923A3 true WO2008091923A3 (fr) 2009-12-30

Family

ID=39640454

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2008/051758 Ceased WO2008091923A2 (fr) 2007-01-23 2008-01-23 Processus d'extraction de résidu de gravure dans la fabrication de semi-conducteurs

Country Status (3)

Country Link
US (1) US20080174015A1 (fr)
TW (1) TW200839948A (fr)
WO (1) WO2008091923A2 (fr)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100824627B1 (ko) * 2006-12-22 2008-04-25 동부일렉트로닉스 주식회사 반도체 소자의 제조방법
KR20090070447A (ko) * 2007-12-27 2009-07-01 주식회사 동부하이텍 반도체 소자 및 그 제조 방법
US8084289B2 (en) * 2010-02-26 2011-12-27 United Microelectronics Corp. Method of fabricating image sensor and reworking method thereof
CN102194836B (zh) * 2010-03-16 2016-03-16 联华电子股份有限公司 图像感测元件的制造方法及其重新制作方法
US9666660B2 (en) 2013-08-16 2017-05-30 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor structures including metal insulator metal capacitor
US10483344B1 (en) * 2018-04-26 2019-11-19 International Business Machines Corporation Fabrication of a MIM capacitor structure with via etch control with integrated maskless etch tuning layers
US11049820B2 (en) * 2018-07-30 2021-06-29 Texas Instruments Incorporated Crack suppression structure for HV isolation component

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040197991A1 (en) * 2003-04-03 2004-10-07 Samsung Electronics Co., Ltd. Dual damascene interconnection with metal-insulator-metal capacitor and method of fabricating the same
US20050266683A1 (en) * 1998-07-06 2005-12-01 Lee Wai M Remover compositions for dual damascene system

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6417112B1 (en) * 1998-07-06 2002-07-09 Ekc Technology, Inc. Post etch cleaning composition and process for dual damascene system
US6485988B2 (en) * 1999-12-22 2002-11-26 Texas Instruments Incorporated Hydrogen-free contact etch for ferroelectric capacitor formation
US6342734B1 (en) * 2000-04-27 2002-01-29 Lsi Logic Corporation Interconnect-integrated metal-insulator-metal capacitor and method of fabricating same
JP2002009248A (ja) * 2000-06-26 2002-01-11 Oki Electric Ind Co Ltd キャパシタおよびその製造方法
US6750113B2 (en) * 2001-01-17 2004-06-15 International Business Machines Corporation Metal-insulator-metal capacitor in copper
US6461914B1 (en) * 2001-08-29 2002-10-08 Motorola, Inc. Process for making a MIM capacitor
JP2004022551A (ja) * 2002-06-12 2004-01-22 Oki Electric Ind Co Ltd 半導体素子の製造方法
US6933191B2 (en) * 2003-09-18 2005-08-23 International Business Machines Corporation Two-mask process for metal-insulator-metal capacitors and single mask process for thin film resistors
KR100976790B1 (ko) * 2004-06-11 2010-08-20 동부일렉트로닉스 주식회사 반도체 소자의 캐패시터 제조 방법
TWM259350U (en) * 2004-06-24 2005-03-11 Tyco Electronics Amp Kk Card connector
JP4593204B2 (ja) * 2004-08-24 2010-12-08 Ｏｋｉセミコンダクタ株式会社 強誘電体メモリの製造方法

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050266683A1 (en) * 1998-07-06 2005-12-01 Lee Wai M Remover compositions for dual damascene system
US20040197991A1 (en) * 2003-04-03 2004-10-07 Samsung Electronics Co., Ltd. Dual damascene interconnection with metal-insulator-metal capacitor and method of fabricating the same

Also Published As

Publication number Publication date
US20080174015A1 (en) 2008-07-24
TW200839948A (en) 2008-10-01
WO2008091923A2 (fr) 2008-07-31

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