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WO2008087763A1 - Dispositif à semi-conducteur et son procédé de fabrication - Google Patents

Dispositif à semi-conducteur et son procédé de fabrication Download PDF

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Publication number
WO2008087763A1
WO2008087763A1 PCT/JP2007/067011 JP2007067011W WO2008087763A1 WO 2008087763 A1 WO2008087763 A1 WO 2008087763A1 JP 2007067011 W JP2007067011 W JP 2007067011W WO 2008087763 A1 WO2008087763 A1 WO 2008087763A1
Authority
WO
WIPO (PCT)
Prior art keywords
mask
conductive type
semiconductor layer
manufacturing
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2007/067011
Other languages
English (en)
Japanese (ja)
Inventor
Koichi Hashimoto
Shin Hashimoto
Kyoko Egashira
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Corp
Panasonic Holdings Corp
Original Assignee
Panasonic Corp
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Panasonic Corp, Matsushita Electric Industrial Co Ltd filed Critical Panasonic Corp
Priority to JP2008553951A priority Critical patent/JP4435847B2/ja
Priority to US12/523,073 priority patent/US7981817B2/en
Priority to CN2007800499520A priority patent/CN101584029B/zh
Publication of WO2008087763A1 publication Critical patent/WO2008087763A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/66—Vertical DMOS [VDMOS] FETs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/0445—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising crystalline silicon carbide
    • H01L21/0455—Making n or p doped regions or layers, e.g. using diffusion
    • H01L21/046—Making n or p doped regions or layers, e.g. using diffusion using ion implantation
    • H01L21/0465—Making n or p doped regions or layers, e.g. using diffusion using ion implantation using masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/01—Manufacture or treatment
    • H10D12/031—Manufacture or treatment of IGBTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/028—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs
    • H10D30/0291—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/028—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs
    • H10D30/0291—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs
    • H10D30/0293—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs using formation of insulating sidewall spacers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
    • H10D62/832—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
    • H10D62/8325—Silicon carbide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/266—Bombardment with radiation with high-energy radiation producing ion implantation using masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/124—Shapes, relative sizes or dispositions of the regions of semiconductor bodies or of junctions between the regions
    • H10D62/126—Top-view geometrical layouts of the regions or the junctions
    • H10D62/127—Top-view geometrical layouts of the regions or the junctions of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/13—Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
    • H10D62/149—Source or drain regions of field-effect devices
    • H10D62/151—Source or drain regions of field-effect devices of IGFETs 
    • H10D62/152—Source regions of DMOS transistors
    • H10D62/153—Impurity concentrations or distributions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/13—Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
    • H10D62/149—Source or drain regions of field-effect devices
    • H10D62/151—Source or drain regions of field-effect devices of IGFETs 
    • H10D62/152—Source regions of DMOS transistors
    • H10D62/155—Shapes 
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/942—Masking
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/942—Masking
    • Y10S438/943—Movable
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/942—Masking
    • Y10S438/945—Special, e.g. metal
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/942—Masking
    • Y10S438/948—Radiation resist
    • Y10S438/951—Lift-off

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

L'invention a pour objet un procédé de fabrication d'un dispositif à semi-conducteur comprenant les étapes consistant à : (a) prévoir un substrat semi-conducteur sur lequel est déposée une couche semi-conductrice d'un premier type conducteur (2) ; (b) former un premier masque (30) qui recouvre une région donnée de la couche semi-conductrice (2) ; (c) injecter des ions d'impureté d'un second type conducteur dans la couche semi-conductrice (2) munie du premier masque (30) pour former ainsi une région de puits d'un second type conducteur (6) ; (d) retirer une partie du premier masque (30) de manière à réduire l'épaisseur (t1) du premier masque (30) ; (e) appliquer une photolithographie pour former ainsi un second masque (34) recouvrant une zone de la région de puits (6) ; et (f) injecter des ions d'impureté d'un premier type conducteur dans la couche semi-conductrice (2) munie du second masque (34) et du premier masque (30') qui a une épaisseur réduite pour former ainsi une région de source d'un premier type conducteur (8).
PCT/JP2007/067011 2007-01-16 2007-08-31 Dispositif à semi-conducteur et son procédé de fabrication Ceased WO2008087763A1 (fr)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2008553951A JP4435847B2 (ja) 2007-01-16 2007-08-31 半導体装置およびその製造方法
US12/523,073 US7981817B2 (en) 2007-01-16 2007-08-31 Method for manufacturing semiconductor device using multiple ion implantation masks
CN2007800499520A CN101584029B (zh) 2007-01-16 2007-08-31 半导体装置的制造方法

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2007006804 2007-01-16
JP2007-006804 2007-01-16

Publications (1)

Publication Number Publication Date
WO2008087763A1 true WO2008087763A1 (fr) 2008-07-24

Family

ID=39635770

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2007/067011 Ceased WO2008087763A1 (fr) 2007-01-16 2007-08-31 Dispositif à semi-conducteur et son procédé de fabrication

Country Status (4)

Country Link
US (1) US7981817B2 (fr)
JP (1) JP4435847B2 (fr)
CN (1) CN101584029B (fr)
WO (1) WO2008087763A1 (fr)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2011013364A1 (fr) * 2009-07-28 2011-02-03 パナソニック株式会社 Procédé de production d'élément semi-conducteur
WO2013035300A1 (fr) * 2011-09-07 2013-03-14 パナソニック株式会社 Elément à semi-conducteurs, dispositif à semi-conducteurs et procédé de fabrication d'éléments à semi-conducteurs
CN111128745A (zh) * 2019-12-04 2020-05-08 深圳第三代半导体研究院 一种SiC基MOS器件的制作方法
JP2023174547A (ja) * 2020-08-31 2023-12-07 ジェネシック セミコンダクタ インク． 改良型パワーデバイスの設計と製造
JP2024041511A (ja) * 2022-09-14 2024-03-27 株式会社東芝 半導体装置及びその製造方法
WO2024257527A1 (fr) * 2023-06-16 2024-12-19 ローム株式会社 Dispositif à semi-conducteur et procédé de fabrication de dispositif à semi-conducteur

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20130141338A (ko) 2010-12-22 2013-12-26 스미토모덴키고교가부시키가이샤 탄화규소 반도체 장치의 제조 방법
WO2013177552A1 (fr) * 2012-05-24 2013-11-28 Microsemi Corporation Mosfet sic intégré monolithique et diode schottky
KR102143431B1 (ko) 2013-12-06 2020-08-28 삼성전자주식회사 불순물 영역 형성 방법 및 반도체 소자의 제조 방법
WO2019171678A1 (fr) 2018-03-07 2019-09-12 三菱電機株式会社 Dispositif à semi-conducteurs au carbure de silicium, son procédé de fabrication et dispositif de conversion de courant
RU183901U1 (ru) * 2018-07-16 2018-10-08 Закрытое акционерное общество "ГРУППА КРЕМНИЙ ЭЛ" Маска для ионного легирования полупроводниковых приборов на основе карбида кремния
US12328932B2 (en) * 2020-02-06 2025-06-10 Lg Electronics Inc. Metal-oxide semiconductor field effect transistor device and manufacturing method therefor
CN112820643B (zh) * 2020-12-28 2022-11-08 中国电子科技集团公司第十三研究所 氧化镓sbd的制备方法及结构
CN114883194A (zh) * 2021-02-05 2022-08-09 华为技术有限公司 一种半导体器件的制造方法和半导体器件
CN113611608A (zh) * 2021-06-16 2021-11-05 深圳基本半导体有限公司 碳化硅平面栅mosfet的制备方法
CN113782445B (zh) * 2021-09-18 2024-05-03 杭州芯迈半导体技术有限公司 超结器件及其制造方法
US12308237B2 (en) * 2021-12-03 2025-05-20 Applied Materials, Inc. Ion implantation to increase MOSFET threshold voltage
IT202300001482A1 (it) * 2023-01-31 2024-07-31 St Microelectronics Int Nv Dispositivo mosfet di potenza di carburo di silicio con prestazioni migliorate e relativo processo di fabbricazione

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JPH01189174A (ja) * 1988-01-23 1989-07-28 Matsushita Electric Works Ltd 二重拡散型電界効果半導体装置の製法
JPH10233503A (ja) * 1997-02-20 1998-09-02 Fuji Electric Co Ltd 炭化けい素縦型ｍｏｓｆｅｔおよびその製造方法
FR2767964A1 (fr) * 1997-09-04 1999-03-05 St Microelectronics Sa Procede de realisation de la zone de canal d'un transistor dmos
JP2000077532A (ja) * 1998-09-03 2000-03-14 Mitsubishi Electric Corp 半導体装置およびその製造方法
JP2001168210A (ja) * 1999-10-27 2001-06-22 Texas Instr Inc <Ti> 集積回路用ドレイン拡張型トランジスタ
JP2002299620A (ja) * 2001-03-30 2002-10-11 Denso Corp 炭化珪素半導体装置の製造方法

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JPH0286136A (ja) 1988-09-22 1990-03-27 Hitachi Ltd 半導体素子およびその製造方法
JP3037053B2 (ja) * 1994-01-28 2000-04-24 三洋電機株式会社 縦型ｍｏｓ半導体装置の製造方法
EP0689238B1 (fr) 1994-06-23 2002-02-20 STMicroelectronics S.r.l. Procédé de manufacture d'un dispositif de puissance en technologie MOS
JP3216804B2 (ja) 1998-01-06 2001-10-09 富士電機株式会社 炭化けい素縦形ｆｅｔの製造方法および炭化けい素縦形ｆｅｔ
US20030127694A1 (en) 2000-09-26 2003-07-10 Alec Morton Higher voltage transistors for sub micron CMOS processes
JP2005353877A (ja) 2004-06-11 2005-12-22 Matsushita Electric Ind Co Ltd 半導体装置
US7157342B1 (en) * 2004-12-29 2007-01-02 T-Ram Semiconductor, Inc Thyristor-based semiconductor memory device and its method of manufacture
JP2006237116A (ja) 2005-02-23 2006-09-07 Matsushita Electric Ind Co Ltd 半導体装置
JP4627211B2 (ja) 2005-04-22 2011-02-09 三菱電機株式会社 炭化珪素半導体装置、及びその製造方法

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01189174A (ja) * 1988-01-23 1989-07-28 Matsushita Electric Works Ltd 二重拡散型電界効果半導体装置の製法
JPH10233503A (ja) * 1997-02-20 1998-09-02 Fuji Electric Co Ltd 炭化けい素縦型ｍｏｓｆｅｔおよびその製造方法
FR2767964A1 (fr) * 1997-09-04 1999-03-05 St Microelectronics Sa Procede de realisation de la zone de canal d'un transistor dmos
JP2000077532A (ja) * 1998-09-03 2000-03-14 Mitsubishi Electric Corp 半導体装置およびその製造方法
JP2001168210A (ja) * 1999-10-27 2001-06-22 Texas Instr Inc <Ti> 集積回路用ドレイン拡張型トランジスタ
JP2002299620A (ja) * 2001-03-30 2002-10-11 Denso Corp 炭化珪素半導体装置の製造方法

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2011013364A1 (fr) * 2009-07-28 2011-02-03 パナソニック株式会社 Procédé de production d'élément semi-conducteur
US8222107B2 (en) 2009-07-28 2012-07-17 Panasonic Corporation Method for producing semiconductor element
WO2013035300A1 (fr) * 2011-09-07 2013-03-14 パナソニック株式会社 Elément à semi-conducteurs, dispositif à semi-conducteurs et procédé de fabrication d'éléments à semi-conducteurs
CN103548142A (zh) * 2011-09-07 2014-01-29 松下电器产业株式会社 半导体元件、半导体装置、及其制造方法
US8878194B2 (en) 2011-09-07 2014-11-04 Panasonic Corporation Semiconductor element, semiconductor device, and semiconductor element manufacturing method
CN103548142B (zh) * 2011-09-07 2016-05-04 松下知识产权经营株式会社 半导体元件、半导体装置、及其制造方法
CN111128745A (zh) * 2019-12-04 2020-05-08 深圳第三代半导体研究院 一种SiC基MOS器件的制作方法
CN111128745B (zh) * 2019-12-04 2022-10-18 深圳第三代半导体研究院 一种SiC基MOS器件的制作方法
JP2023174547A (ja) * 2020-08-31 2023-12-07 ジェネシック セミコンダクタ インク． 改良型パワーデバイスの設計と製造
JP2024041511A (ja) * 2022-09-14 2024-03-27 株式会社東芝 半導体装置及びその製造方法
WO2024257527A1 (fr) * 2023-06-16 2024-12-19 ローム株式会社 Dispositif à semi-conducteur et procédé de fabrication de dispositif à semi-conducteur

Also Published As

Publication number Publication date
CN101584029B (zh) 2011-05-04
US20100048004A1 (en) 2010-02-25
CN101584029A (zh) 2009-11-18
US7981817B2 (en) 2011-07-19
JP4435847B2 (ja) 2010-03-24
JPWO2008087763A1 (ja) 2010-05-06

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