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WO2008081740A1 - Ｓｒａｍセル及びｓｒａｍ装置 - Google Patents

Ｓｒａｍセル及びｓｒａｍ装置 Download PDF

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Publication number
WO2008081740A1
WO2008081740A1 PCT/JP2007/074547 JP2007074547W WO2008081740A1 WO 2008081740 A1 WO2008081740 A1 WO 2008081740A1 JP 2007074547 W JP2007074547 W JP 2007074547W WO 2008081740 A1 WO2008081740 A1 WO 2008081740A1
Authority
WO
WIPO (PCT)
Prior art keywords
terminal double
double gate
gate fets
conductivity type
fets
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2007/074547
Other languages
English (en)
French (fr)
Inventor
Shinichi Ouchi
Yongxun Liu
Meishoku Masahara
Takashi Matsukawa
Kazuhiko Endo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
National Institute of Advanced Industrial Science and Technology AIST
Original Assignee
National Institute of Advanced Industrial Science and Technology AIST
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by National Institute of Advanced Industrial Science and Technology AIST filed Critical National Institute of Advanced Industrial Science and Technology AIST
Priority to JP2008552094A priority Critical patent/JP5004251B2/ja
Priority to US12/521,408 priority patent/US8040717B2/en
Publication of WO2008081740A1 publication Critical patent/WO2008081740A1/ja
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices
    • H10B10/12—Static random access memory [SRAM] devices comprising a MOSFET load element
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/62—Fin field-effect transistors [FinFET]
    • H10D30/6217—Fin field-effect transistors [FinFET] having non-uniform gate electrodes, e.g. gate conductors having varying doping
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/011—Manufacture or treatment comprising FinFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/201—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates the substrates comprising an insulating layer on a semiconductor body, e.g. SOI
    • H10D86/215—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates the substrates comprising an insulating layer on a semiconductor body, e.g. SOI comprising FinFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/62—Fin field-effect transistors [FinFET]

Landscapes

  • Semiconductor Memories (AREA)
  • Thin Film Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

　基板上に起立し相互に平行に配置され、各々第１伝導型の第１の４端子ダブルゲートＦＥＴ、第２伝導型で直列接続された第２、第３の４端子ダブルゲートＦＥＴ、第２伝導型で直列接続された第４、第５の４端子ダブルゲートＦＥＴ、第１伝導型の第６の４端子ダブルゲートＦＥＴが形成される第１乃至第４の半導体薄板を含み、第３、第４の４端子ダブルゲートＦＥＴは選択トランジスタを構成し、第１、第２、第５、第６の４端子ダブルゲートＦＥＴは相補型インバータを構成するＳＲＡＭセルにおいて、第１及び第６の４端子ダブルゲートＦＥＴの論理信号入力ゲートは第２、第３の半導体薄板側に配置され、第２乃至第５の４端子ダブルゲートＦＥＴのしきい値制御ゲートは、互いに対向する位置に配置され且つ第１のバイアス配線に共通接続され、第１及び第６の４端子ダブルゲートＦＥＴのしきい値制御ゲートは第２のバイアス配線に共通接続されており、ワード線、第１及び第２のバイアス配線は、第１乃至第４の半導体薄板の配列方向に直交して配置される。
PCT/JP2007/074547 2006-12-28 2007-12-20 Ｓｒａｍセル及びｓｒａｍ装置 Ceased WO2008081740A1 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2008552094A JP5004251B2 (ja) 2006-12-28 2007-12-20 Ｓｒａｍセル及びｓｒａｍ装置
US12/521,408 US8040717B2 (en) 2006-12-28 2007-12-20 SRAM cell and SRAM device

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2006-354537 2006-12-28
JP2006354537 2006-12-28

Publications (1)

Publication Number Publication Date
WO2008081740A1 true WO2008081740A1 (ja) 2008-07-10

Family

ID=39588424

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2007/074547 Ceased WO2008081740A1 (ja) 2006-12-28 2007-12-20 Ｓｒａｍセル及びｓｒａｍ装置

Country Status (3)

Country Link
US (1) US8040717B2 (ja)
JP (1) JP5004251B2 (ja)
WO (1) WO2008081740A1 (ja)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2009119666A1 (ja) * 2008-03-28 2009-10-01 独立行政法人産業技術総合研究所 Ｓｒａｍセル及びｓｒａｍ装置

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9865330B2 (en) * 2010-11-04 2018-01-09 Qualcomm Incorporated Stable SRAM bitcell design utilizing independent gate FinFET
US8830732B2 (en) 2012-11-30 2014-09-09 Taiwan Semiconductor Manufacturing Company, Ltd. SRAM cell comprising FinFETs
CN105719688B (zh) * 2014-12-04 2019-03-29 中芯国际集成电路制造(上海)有限公司 Sram存储器和形成sram存储器的方法
US9786385B2 (en) * 2015-03-02 2017-10-10 Oracle International Corporation Memory power selection using local voltage regulators
CN119785854B (zh) * 2023-10-08 2025-11-11 长江存储科技有限责任公司 存储器装置及其操作方法、存储器系统

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05167073A (ja) * 1991-12-17 1993-07-02 Hitachi Ltd 半導体集積回路装置及びその製造方法
JP2002270850A (ja) * 2001-03-13 2002-09-20 National Institute Of Advanced Industrial & Technology 二重ゲート電界効果トランジスタ
JP2005064459A (ja) * 2003-07-31 2005-03-10 Toshiba Corp 半導体装置およびその製造方法
JP2005167163A (ja) * 2003-12-05 2005-06-23 National Institute Of Advanced Industrial & Technology 二重ゲート電界効果トランジスタ
JP2005174960A (ja) * 2003-12-05 2005-06-30 National Institute Of Advanced Industrial & Technology 二重ゲート電界効果トランジスタ
WO2005079182A2 (en) * 2004-01-22 2005-09-01 International Business Machines Corporation Vertical fin-fet mos devices
JP2005260607A (ja) * 2004-03-11 2005-09-22 National Institute Of Advanced Industrial & Technology 二重絶縁ゲート電界効果トランジスタを用いたｃｍｏｓ回路
JP2007201107A (ja) * 2006-01-25 2007-08-09 Toshiba Corp 半導体装置

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6630388B2 (en) * 2001-03-13 2003-10-07 National Institute Of Advanced Industrial Science And Technology Double-gate field-effect transistor, integrated circuit using the transistor and method of manufacturing the same
WO2005055326A1 (ja) * 2003-12-05 2005-06-16 National Institute Of Advanced Industrial Science And Technology 二重ゲート電界効果トランジスタ
US7417889B2 (en) * 2006-02-27 2008-08-26 International Business Machines Corporation Independent-gate controlled asymmetrical memory cell and memory using the cell
JP5131788B2 (ja) * 2008-03-28 2013-01-30 独立行政法人産業技術総合研究所 Ｓｒａｍセル及びｓｒａｍ装置

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05167073A (ja) * 1991-12-17 1993-07-02 Hitachi Ltd 半導体集積回路装置及びその製造方法
JP2002270850A (ja) * 2001-03-13 2002-09-20 National Institute Of Advanced Industrial & Technology 二重ゲート電界効果トランジスタ
JP2005064459A (ja) * 2003-07-31 2005-03-10 Toshiba Corp 半導体装置およびその製造方法
JP2005167163A (ja) * 2003-12-05 2005-06-23 National Institute Of Advanced Industrial & Technology 二重ゲート電界効果トランジスタ
JP2005174960A (ja) * 2003-12-05 2005-06-30 National Institute Of Advanced Industrial & Technology 二重ゲート電界効果トランジスタ
WO2005079182A2 (en) * 2004-01-22 2005-09-01 International Business Machines Corporation Vertical fin-fet mos devices
JP2005260607A (ja) * 2004-03-11 2005-09-22 National Institute Of Advanced Industrial & Technology 二重絶縁ゲート電界効果トランジスタを用いたｃｍｏｓ回路
JP2007201107A (ja) * 2006-01-25 2007-08-09 Toshiba Corp 半導体装置

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
DAVIS J. ET AL.: "A 5.6GHz 64kB Dual-Read Data Cache for the POWER Processor", 2006 IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE DIGEST OF TECHNICAL PAPERS, 6 February 2006 (2006-02-06), pages 2564 - 2571, XP010940666 *
O'UCHI M. ET AL.: "Flex-Pass-Gate SRAM Design for Static Noise Margin Enhancement Using FinFET-Based Technology", PROCEEDINGS OF THE IEEE 2007 CUSTOM INTEGRATED CIRCUITS CONFERENCE, 16 September 2007 (2007-09-16), XP031223536 *

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2009119666A1 (ja) * 2008-03-28 2009-10-01 独立行政法人産業技術総合研究所 Ｓｒａｍセル及びｓｒａｍ装置
JP5131788B2 (ja) * 2008-03-28 2013-01-30 独立行政法人産業技術総合研究所 Ｓｒａｍセル及びｓｒａｍ装置
US8659088B2 (en) 2008-03-28 2014-02-25 National Institute Of Advanced Industrial Science And Technology SRAM cell and SRAM device

Also Published As

Publication number Publication date
US8040717B2 (en) 2011-10-18
JP5004251B2 (ja) 2012-08-22
JPWO2008081740A1 (ja) 2010-04-30
US20100315861A1 (en) 2010-12-16

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