[go: up one dir, main page]

WO2008079684A3 - Electron blocking layers for electronic devices - Google Patents

Electron blocking layers for electronic devices Download PDF

Info

Publication number
WO2008079684A3
WO2008079684A3 PCT/US2007/087167 US2007087167W WO2008079684A3 WO 2008079684 A3 WO2008079684 A3 WO 2008079684A3 US 2007087167 W US2007087167 W US 2007087167W WO 2008079684 A3 WO2008079684 A3 WO 2008079684A3
Authority
WO
WIPO (PCT)
Prior art keywords
electronic devices
layer control
dielectric
electron blocking
blocking layers
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US2007/087167
Other languages
French (fr)
Other versions
WO2008079684A2 (en
WO2008079684B1 (en
Inventor
Jian Chen
Xiangfeng Duan
Karen Cruden
Chao Liu
Madhuri L Nallabolu
Srikanth Ranganathan
Francisco Leon
J Wallace Parce
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nanosys Inc
Original Assignee
Nanosys Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US11/641,956 external-priority patent/US20080150003A1/en
Priority claimed from US11/688,087 external-priority patent/US20080150004A1/en
Priority claimed from US11/743,085 external-priority patent/US20080150009A1/en
Priority to CN200780046789.2A priority Critical patent/CN101589461B/en
Priority to JP2009543077A priority patent/JP2010531048A/en
Priority to KR1020097012821A priority patent/KR101443731B1/en
Application filed by Nanosys Inc filed Critical Nanosys Inc
Publication of WO2008079684A2 publication Critical patent/WO2008079684A2/en
Publication of WO2008079684A3 publication Critical patent/WO2008079684A3/en
Priority to US12/247,917 priority patent/US7847341B2/en
Publication of WO2008079684B1 publication Critical patent/WO2008079684B1/en
Priority to US12/390,275 priority patent/US8686490B2/en
Anticipated expiration legal-status Critical
Priority to US14/164,065 priority patent/US9214525B2/en
Ceased legal-status Critical Current

Links

Classifications

    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/031—Manufacture or treatment of data-storage electrodes
    • H10D64/035—Manufacture or treatment of data-storage electrodes comprising conductor-insulator-conductor-insulator-semiconductor structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/031—Manufacture or treatment of data-storage electrodes
    • H10D64/037—Manufacture or treatment of data-storage electrodes comprising charge-trapping insulators
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/68—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
    • H10D64/681—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator having a compositional variation, e.g. multilayered
    • H10D64/685—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator having a compositional variation, e.g. multilayered being perpendicular to the channel plane
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/68—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
    • H10D64/691—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator comprising metallic compounds, e.g. metal oxides or metal silicates 

Landscapes

  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Nanotechnology (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Mathematical Physics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)

Abstract

Methods and apparatus for electronic devices such as non-volatile memory devices are described. The momory devices include a multi-layer control dielectric, such as a double or triple layer. The multi-layer control electric includes a combination of high-k dielectric meterials such as aluminium oxide (A12O3), Hafnium oxide (HfO2), and/or hybrid films of Hafnium aluminium oxide. The multi-layer control dielectric provides enhanced characteristics, including increased charge retention, enhanced memory program/erase window, improved reliability and stability, with feasibility for single or multistate (e.g, two, three or four bit) operation.
PCT/US2007/087167 2006-12-20 2007-12-12 Electron blocking layers for electronic devices Ceased WO2008079684A2 (en)

Priority Applications (6)

Application Number Priority Date Filing Date Title
CN200780046789.2A CN101589461B (en) 2006-12-20 2007-12-12 Electron blocking layers for electronic devices
JP2009543077A JP2010531048A (en) 2006-12-20 2007-12-12 Electronic block layer for electronic devices
KR1020097012821A KR101443731B1 (en) 2006-12-20 2007-12-12 Electron blocking layers for electronic devices
US12/247,917 US7847341B2 (en) 2006-12-20 2008-10-08 Electron blocking layers for electronic devices
US12/390,275 US8686490B2 (en) 2006-12-20 2009-02-20 Electron blocking layers for electronic devices
US14/164,065 US9214525B2 (en) 2006-12-20 2014-01-24 Gate stack having electron blocking layers on charge storage layers for electronic devices

Applications Claiming Priority (10)

Application Number Priority Date Filing Date Title
US11/641,956 2006-12-20
US11/641,956 US20080150003A1 (en) 2006-12-20 2006-12-20 Electron blocking layers for electronic devices
US11/688,087 US20080150004A1 (en) 2006-12-20 2007-03-19 Electron Blocking Layers for Electronic Devices
US11/688,087 2007-03-19
US11/743,085 US20080150009A1 (en) 2006-12-20 2007-05-01 Electron Blocking Layers for Electronic Devices
US11/743,085 2007-05-01
US93148807P 2007-05-23 2007-05-23
US60/931,488 2007-05-23
EP07252410A EP1936672A1 (en) 2006-12-20 2007-06-14 Electron blocking layers for gate stacks of nonvolatile memory devices
EP07252410.1 2007-06-14

Related Parent Applications (2)

Application Number Title Priority Date Filing Date
US11/688,087 Continuation-In-Part US20080150004A1 (en) 2006-12-20 2007-03-19 Electron Blocking Layers for Electronic Devices
US11/743,085 Continuation-In-Part US20080150009A1 (en) 2006-12-20 2007-05-01 Electron Blocking Layers for Electronic Devices

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US12/247,917 Continuation-In-Part US7847341B2 (en) 2006-12-20 2008-10-08 Electron blocking layers for electronic devices

Publications (3)

Publication Number Publication Date
WO2008079684A2 WO2008079684A2 (en) 2008-07-03
WO2008079684A3 true WO2008079684A3 (en) 2008-09-04
WO2008079684B1 WO2008079684B1 (en) 2008-10-23

Family

ID=39563160

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2007/087167 Ceased WO2008079684A2 (en) 2006-12-20 2007-12-12 Electron blocking layers for electronic devices

Country Status (2)

Country Link
KR (1) KR101443731B1 (en)
WO (1) WO2008079684A2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7847341B2 (en) 2006-12-20 2010-12-07 Nanosys, Inc. Electron blocking layers for electronic devices
US8686490B2 (en) 2006-12-20 2014-04-01 Sandisk Corporation Electron blocking layers for electronic devices

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8383479B2 (en) 2009-07-21 2013-02-26 Sandisk Technologies Inc. Integrated nanostructure-based non-volatile memory fabrication

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6586785B2 (en) * 2000-06-29 2003-07-01 California Institute Of Technology Aerosol silicon nanoparticles for use in semiconductor device fabrication
US20050074982A1 (en) * 2001-02-02 2005-04-07 Samsung Electronics Co., Ltd. Dielectric layer for semiconductor device and method of manufacturing the same
US20060054943A1 (en) * 2004-09-14 2006-03-16 Infineon Technologies North America Corp. Flash EEPROM with metal floating gate electrode
US20060186457A1 (en) * 2005-02-18 2006-08-24 Burnett James D Methods for programming a floating body nonvolatile memory

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004281662A (en) 2003-03-14 2004-10-07 Toshiba Corp Semiconductor storage device and method of manufacturing the same
JP4040534B2 (en) 2003-06-04 2008-01-30 株式会社東芝 Semiconductor memory device
KR100652402B1 (en) * 2005-02-21 2006-12-01 삼성전자주식회사 Nonvolatile Memory Device and Manufacturing Method Thereof

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6586785B2 (en) * 2000-06-29 2003-07-01 California Institute Of Technology Aerosol silicon nanoparticles for use in semiconductor device fabrication
US20050074982A1 (en) * 2001-02-02 2005-04-07 Samsung Electronics Co., Ltd. Dielectric layer for semiconductor device and method of manufacturing the same
US20060054943A1 (en) * 2004-09-14 2006-03-16 Infineon Technologies North America Corp. Flash EEPROM with metal floating gate electrode
US20060186457A1 (en) * 2005-02-18 2006-08-24 Burnett James D Methods for programming a floating body nonvolatile memory

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7847341B2 (en) 2006-12-20 2010-12-07 Nanosys, Inc. Electron blocking layers for electronic devices
US8686490B2 (en) 2006-12-20 2014-04-01 Sandisk Corporation Electron blocking layers for electronic devices
US9214525B2 (en) 2006-12-20 2015-12-15 Sandisk Corporation Gate stack having electron blocking layers on charge storage layers for electronic devices

Also Published As

Publication number Publication date
WO2008079684A2 (en) 2008-07-03
KR101443731B1 (en) 2014-09-23
KR20090113253A (en) 2009-10-29
WO2008079684B1 (en) 2008-10-23

Similar Documents

Publication Publication Date Title
EP2357662A3 (en) Electron blocking layers for gate stacks of nonvolatile memory devices
WO2016030081A1 (en) Method for identifying a short circuit in a first light emitting diode element, and optoelectronic subassembly
GB2418535A (en) Non-volatile memory device
EP3537483A3 (en) Oxide-nitride-oxide stack having multiple oxynitride layers
US7566618B2 (en) Non-volatile memory device having SONOS structure and manufacturing method thereof
TW201803093A (en) Integrated structures including material containing silicon, nitrogen, and at least one of carbon, oxygen, boron and phosphorus
TW200518281A (en) Method for fabricating flash memory device and structure thereof
WO2007018821A3 (en) Dual-gate device and method
WO2008008171A3 (en) Bandgap engineered charge storage layer for 3d tft
CN103460383B (en) Nonvolatile memory element and manufacturing method thereof
TW200733309A (en) Semiconductor device having electrode and manufacturing method thereof
WO2008079684A3 (en) Electron blocking layers for electronic devices
JP2009094480A (en) Flash memory device and manufacturing method thereof
US8389358B2 (en) Manufacturing method and structure of non-volatile memory
WO2007149720A3 (en) Semiconductive device having resist poison aluminum oxide barrier and method of manufacture
WO2007004223A3 (en) Electroluminescent cable and method of fabrication thereof
CN101097965A (en) Nonvolatile memory device and manufacturing method thereof
Breuil et al. A novel multilayer inter-gate dielectric enabling up to 18V program/erase window for planar NAND flash
TW200711056A (en) Memory device with barrier layer
JP2011082581A (en) Memory device
US8901633B2 (en) Semiconductor storage device and method for manufacturing the same
JP2010027715A (en) Memory apparatus
JP2008166682A (en) Formation method of contact plug of semiconductor element
CN101211856A (en) Method for manufacturing semiconductor device
TW200638535A (en) Programmable and erasable digital switch device and manufacturing method and operating method thereof

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 200780046789.2

Country of ref document: CN

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 07865540

Country of ref document: EP

Kind code of ref document: A2

ENP Entry into the national phase

Ref document number: 2009543077

Country of ref document: JP

Kind code of ref document: A

WWE Wipo information: entry into national phase

Ref document number: 1020097012821

Country of ref document: KR

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 07865540

Country of ref document: EP

Kind code of ref document: A2