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WO2008073493A3 - Methods and apparatus for reducing storage usage in devices - Google Patents

Methods and apparatus for reducing storage usage in devices Download PDF

Info

Publication number
WO2008073493A3
WO2008073493A3 PCT/US2007/025498 US2007025498W WO2008073493A3 WO 2008073493 A3 WO2008073493 A3 WO 2008073493A3 US 2007025498 W US2007025498 W US 2007025498W WO 2008073493 A3 WO2008073493 A3 WO 2008073493A3
Authority
WO
WIPO (PCT)
Prior art keywords
ram
buffer
methods
flash
rom
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US2007/025498
Other languages
French (fr)
Other versions
WO2008073493A2 (en
Inventor
Paul T Breed
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NETBURNER Inc
Original Assignee
NETBURNER Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US12/001,511 external-priority patent/US20080256271A1/en
Application filed by NETBURNER Inc filed Critical NETBURNER Inc
Publication of WO2008073493A2 publication Critical patent/WO2008073493A2/en
Publication of WO2008073493A3 publication Critical patent/WO2008073493A3/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0866—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches for peripheral storage systems, e.g. disk cache
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/90—Buffering arrangements
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/90—Buffering arrangements
    • H04L49/901—Buffering arrangements using storage descriptor, e.g. read or write pointers
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
    • H04L69/16—Implementation or adaptation of Internet protocol [IP], of transmission control protocol [TCP] or of user datagram protocol [UDP]
    • H04L69/163—In-band adaptation of TCP data exchange; In-band control procedures
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/22—Employing cache memory using specific memory technology
    • G06F2212/225—Hybrid cache memory, e.g. having both volatile and non-volatile portions
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/26—Using a specific storage system architecture
    • G06F2212/264—Remote server
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
    • H04L69/16—Implementation or adaptation of Internet protocol [IP], of transmission control protocol [TCP] or of user datagram protocol [UDP]

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Security & Cryptography (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Information Transfer Systems (AREA)
  • Storing Facsimile Image Data (AREA)
  • Facsimiles In General (AREA)

Abstract

Transmission buffer apparatus and methods configured to minimize the storage requirements for transmission/retransmission of data by allocating retransmission data to two or more types of storage. In one embodiment, RAM usage in a RAM-limited embedded device is minimized by storing only a reference or pointer to ROM- or Flash-sourced within the retransmission buffer (e.g., RAM), thereby reducing the storage burden on the buffer. For example, web pages having largely non-volatile components can be stored in ROM or Flash, while only the dynamic or volatile portions are stored in RAM. Apparatus and methods for implementing an exemplary serial-to-Ethernet interface are disclosed, as well as use of Flash or ROM to store configuration data in the form of e.g., a web page image. A circular buffer approach implementing the aforementioned methodologies is also described.
PCT/US2007/025498 2006-12-12 2007-12-12 Methods and apparatus for reducing storage usage in devices Ceased WO2008073493A2 (en)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US87465106P 2006-12-12 2006-12-12
US60/874,651 2006-12-12
US12/001,511 US20080256271A1 (en) 2006-12-12 2007-12-11 Methods and apparatus for reducing storage usage in devices
US12/001,511 2007-12-11

Publications (2)

Publication Number Publication Date
WO2008073493A2 WO2008073493A2 (en) 2008-06-19
WO2008073493A3 true WO2008073493A3 (en) 2008-08-28

Family

ID=39512342

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2007/025498 Ceased WO2008073493A2 (en) 2006-12-12 2007-12-12 Methods and apparatus for reducing storage usage in devices

Country Status (1)

Country Link
WO (1) WO2008073493A2 (en)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8677009B2 (en) * 2010-01-22 2014-03-18 Microsoft Corporation Massive structured data transfer optimizations for high-latency, low-reliability networks
US9849372B2 (en) 2012-09-28 2017-12-26 Sony Interactive Entertainment Inc. Method and apparatus for improving efficiency without increasing latency in emulation of a legacy application title
EP2723031B1 (en) * 2012-10-16 2019-07-24 Robert Bosch Gmbh Distributed measurement arrangement for an embedded automotive acquisition device with tcp acceleration
CN110266315B (en) * 2013-03-15 2023-10-27 索尼电脑娱乐公司 Compression of state information for data transmission over cloud-based networks
CN110120922B (en) * 2019-05-14 2022-09-20 中核控制系统工程有限公司 FPGA-based data interaction network management system and method

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5584038A (en) * 1994-03-01 1996-12-10 Intel Corporation Entry allocation in a circular buffer using wrap bits indicating whether a queue of the circular buffer has been traversed
US6393504B1 (en) * 1994-07-05 2002-05-21 Monolithic System Technology, Inc. Dynamic address mapping and redundancy in a modular memory device
US20050010723A1 (en) * 2003-07-12 2005-01-13 Sang-Yeun Cho Cache memory systems having a flexible buffer memory portion and methods of operating the same
US6968358B2 (en) * 2002-07-25 2005-11-22 International Business Machines Corporation Method and apparatus for network communication card memory management

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5584038A (en) * 1994-03-01 1996-12-10 Intel Corporation Entry allocation in a circular buffer using wrap bits indicating whether a queue of the circular buffer has been traversed
US6393504B1 (en) * 1994-07-05 2002-05-21 Monolithic System Technology, Inc. Dynamic address mapping and redundancy in a modular memory device
US6968358B2 (en) * 2002-07-25 2005-11-22 International Business Machines Corporation Method and apparatus for network communication card memory management
US20050010723A1 (en) * 2003-07-12 2005-01-13 Sang-Yeun Cho Cache memory systems having a flexible buffer memory portion and methods of operating the same

Also Published As

Publication number Publication date
WO2008073493A2 (en) 2008-06-19

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