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WO2007150009A1 - Système et procédé de traitement de tranches de semi-conducteur - Google Patents

Système et procédé de traitement de tranches de semi-conducteur Download PDF

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Publication number
WO2007150009A1
WO2007150009A1 PCT/US2007/071846 US2007071846W WO2007150009A1 WO 2007150009 A1 WO2007150009 A1 WO 2007150009A1 US 2007071846 W US2007071846 W US 2007071846W WO 2007150009 A1 WO2007150009 A1 WO 2007150009A1
Authority
WO
WIPO (PCT)
Prior art keywords
processing
wafer
workstations
workstation
input station
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US2007/071846
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English (en)
Inventor
Kurt Pelsue
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Novanta Inc
Original Assignee
GSI Group Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by GSI Group Corp filed Critical GSI Group Corp
Publication of WO2007150009A1 publication Critical patent/WO2007150009A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67155—Apparatus for manufacturing or treating in a plurality of work-stations
    • H01L21/67161—Apparatus for manufacturing or treating in a plurality of work-stations characterized by the layout of the process chambers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67155—Apparatus for manufacturing or treating in a plurality of work-stations
    • H01L21/67207—Apparatus for manufacturing or treating in a plurality of work-stations comprising a chamber adapted to a particular process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67242—Apparatus for monitoring, sorting or marking
    • H01L21/67276—Production flow monitoring, e.g. for increasing throughput

Definitions

  • the invention generally relates to wafer processing systems, and relates in particular to systems and methods for selectively directing laser illumination to desired locations on wafers for the purpose of modifying circuits on the wafers.
  • Resistor trimming, link removal and memory repair processing are well known techniques for modifying circuits in a semiconductor wafer by selectively ablating very small portions of circuits on semiconductor wafers.
  • U.S. Patent No. 6,483,071 discloses a system and method for positioning a waist of a laser beam on a microstructure for such laser processing.
  • Memory repair for example, is generally a process of severing links in a memory circuit to isolate portions of the memory circuit that fail a test while the circuit is still in the wafer form. The circuits are manufactured with extra rows and columns of memory cells that are used if the wafer includes any defects.
  • each wafer must typically be processed under a set of parameters that are specific to that wafer. For example, wafers being processed for memory repair may require different links to be blown on each wafer since the factors that may cause certain memory cells to be unsatisfactory will vary from wafer to wafer.
  • a semiconductor wafer processing system for providing concurrent processing of wafers includes an input station for receiving a plurality of wafers for processing, and a plurality of workstations.
  • Each of the plurality of workstations is coupled to the input station and each includes a stage system for providing relative motion of the wafer and a laser beam, a chuck for holding a wafer to be processed, optics for directing laser illumination toward the wafer to be processed, and a wafer buffer system for providing that wafer transfer between the input station and the workstation may be asynchronous with respect to wafer processing at the respective workstation.
  • the invention provides a method of processing substrates that includes the steps of receiving a plurality of substrates via an input station, providing each of the substrates to a different workstation that is coupled to the input station, processing each of the substrates using a different set of processing instructions, and providing each of the substrates to the input station following processing, wherein the input station moves one substrate at a time.
  • the invention provides a substrate processing system including an input station and a plurality of workstations.
  • Each of the plurality of workstations is coupled to an input station and each includes optics for directing laser illumination toward a substrate to be processed, a stage system for providing relative movement between the laser illumination and the substrate, and a chuck for holding a substrate to be processed.
  • the substrate processing system provides that each workstation may process substrates independent of the other of the plurality of substrates.
  • each of the plurality of workstations may have a dual transfer arms to overcome handling bottlenecks that may result from simultaneous wafer transfer requests and rapid unload and load cycles during processing.
  • Figure 1 shows an illustrative diagrammatic plan view of a wafer processing system in accordance with an embodiment of the invention
  • Figure 2 shows an illustrative diagrammatic side view of the system of Figure 1;
  • Figures 3 A - 3E show illustrative diagrammatic plan views of wafer processing systems in accordance with further embodiments of the invention.
  • Figure 4 shows an illustrative flowchart of processing steps during a startup operation in a system in accordance with an embodiment of the invention
  • Figures 5a and b show illustrative flowcharts of processing steps during operation in accordance with an embodiment of the invention.
  • the invention generally provides for plural laser processing workstations that are coupled to a common input station by a wafer transfer system. This, together with dynamic processing capabilities provides for substrate processing systems that may efficiently process a larger number of substrates.
  • a system in accordance with an embodiment of the invention includes an input handler station 10 and two wafer processing workstations 12, 14.
  • the input handler station 10 includes one or more loadports 16, a wafer robot 18 and an aligner unit 20.
  • the wafers are introduced into and retrieved from the system through the one or more loadports 16.
  • the wafer robot 18 then ferries the wafers along tracks 40 to either of the stations 12, 14.
  • Each station 12, 14 is aligned and attached to the handler station 10 by keyed locking units 42, and the wafers pass into and out from each station 12, 14 via openings 44.
  • the system also includes a user interface console 48 that may include a monitor screen and a keyboard.
  • each wafer processing workstation 12, 14 includes a frame 22 with a computer control unit 24 and a power and air conditioning unit 26, and a stage system.
  • the stage system includes a vibration isolation unit 28, a fine stage 36b, a chuck 32, a coarse stage 34 and a beam box 30 including a laser 38.
  • Each vibration isolation unit 28 may include vibration isolated legs on which an optical table and fine stage are mounted, and in certain embodiments, the isolation unit 28 may further include geophones or accelerometers as vibration sensors.
  • Each fine stage 36a, 36b also includes a plurality of actuator units 50 for moving the fine stage as well as a plurality of force cancellation units 51 as disclosed, for example in U.S. Patent No. 6,144,118, the disclosure of which is hereby incorporated by reference.
  • the force cancellation units 51 may provide for cancellation of forces that result from the work station in which they reside.
  • the multiple workstations may operate in synchronous or asynchronous modes. In the synchronous mode the multiple workstations wait until all have completed a particular tile of processing before making simultaneous course stage moves so any transmitted vibrations would not affect processing. In this regard, the course stages of the plurality of workstations may move synchronously. Because many laser fine tuning processes such as redundant memory repair or resistor trimming have variable process times due to the characteristics of the specific device it is advantageous to operate asynchronously minimizing process delays.
  • the vibration isolation system 28 isolates vibrations that result from workstations caused principally by the course stage and vibrations introduced by other workstations that share a common input station in accordance with various embodiments of the invention. Furthermore staggered wafer processing either in asynchronous or synchronous operation allows staggered wafer exchange timing preventing waiting periods for load - unload operations.
  • Each laser 38 may be, for example, a Q-switched Nd: YAG laser having a pre- determined pulse width, repetition rate, and wavelength as disclosed in U.S. Pat. No. 5,998,759, the disclosure of which is hereby incorporated by reference.
  • a fiber laser using a semiconductor diode seed laser and a fiber laser may be used to provide improved control over the temporal pulse shape, thereby allowing for processing of smaller links with less risk of damage to surrounding structures as described, for example, in U.S. Patent No. 6,281,471, the disclosure of which is hereby incorporated by reference.
  • the input handler station is an equipment front end module (EFEM) having a front opening unified load port 16, a wafer robot 18 to transfer wafers from the load port 16 to the workstations 12, 14, and a wafer aligner 20 to correct the position error of the wafer on the robot arm resulting from a loose tolerance of position and location in the load port such that it is placed accurately on the workstation chuck 32a, 32b.
  • the EFEM is about 40% of the wafer repair system footprint, and about 30% of the system cost.
  • a load controller 25 which is a computer that manages the loading and unloading of the wafers from castes to transfer arms and communicating the wafer information to the various workstations 12 or 14.
  • the laser processing workstations each include a moving fine wafer stage 32a and 32b for very high acceleration moves and a course stage for repositioning the laser beam box 30 with low acceleration such as disclosed, for example, in U.S. Patent No. 6,483,071, the disclosure of which is hereby incorporated by reference.
  • stage systems for inducing relative motion of the wafer and the laser beam such a split stage construction where the wafer moves in a full range on one axis and the laser beam moves in the full range of the orthogonal axes.
  • the fine stage could be replaced with a galvanometer scanning system.
  • an H frame stage could be used where the first axis moves laterally across the cross bar of the H by a single motor and the cross bar structure is carried by two motors moving along the vertical bars of the H.
  • a processing workstation may comprise the remaining 60% of footprint and 70% of the system cost.
  • the process for link blowing may generally require processing (i.e., laser ablation) of a subset of a large number of links on a wafer.
  • the information that defines the links to be processed is provided to a control program via a network connection to the factory host.
  • the link blast plan data will define a set of reference locations surrounding a number of die with links to be processed, and the locations will generally include a sufficient number of points to accurately define a trajectory to be followed by the wafer based upon commands generated for blast location in the blast map data.
  • height may be measured using an auto-focus depth- from- focus sensor as follows.
  • the system scans a laser beam occur over a fixed x, y location target and adjusts the beam waist position within a range of heights (z-axis positions).
  • the contrast in each scan is recorded.
  • the contrast in the scan will be maximized and the JC, y, z location of the target known relative to the beam focus can be determined.
  • a high power processing beam may be used in conjunction with a reflection sensor and a beam modulator to control the power delivered to the surface such as not to cause damage during alignment.
  • the reference information and computed surface provide compensation for planar topology that is either parallel or non-parallel to the focal plane.
  • Multiple reference sites may provide improved estimates of a surface and improved measurement and statistical confidence in the presence of sensor noise and mechanism errors.
  • a best-fit focus plane may be used.
  • a plane may closely approximate many surface shapes as long as the minimum radii of curvature of the actual surface is large, recognizing that a plane is a curve with infinite radius of curvature.
  • the best-fit plane approximation is sufficient to compensate for the majority of wafer topology with residual errors (deviation from best-fit plane).
  • a user interface includes a keyboard and monitor that is of relatively low cost, but may require about 1 m 2 of floor space and in the cluster configuration multiple workstations sharing one user interface 48.
  • Alternative user interfaces such as integral flat panel displays and input pads or touch sensitive displays may use substantially less floor space.
  • the workstation also houses power conditioning and air management systems.
  • multiple workstations may share a single utilities management system.
  • Each wafer handling subsystem may be designed for 300 mm semiconductor wafer handling standards, and may be converted to handle 200 mm wafers by replacing the load port with an open-cassette shelf.
  • the wafer handler includes a high-efficiency particulate air (HEPA) system to maintain cleanliness during handling operations, load port openers and a track to allow the robot to access the load ports.
  • HEPA high-efficiency particulate air
  • One type of fine stage assembly includes a single moving body, a platen, four actuator units 50 and the associated electronics.
  • Each actuator unit 50 contains top and bottom planar coils for the one of four fine stage motors. Adjacent to the fine stage motors are force cancellation motors 51 for moving a force-cancellation actuator mass.
  • the stage motors generate force at a theoretical point that lies at the centerline of the fine stage magnets.
  • the fine stage body is the movable portion of the fine stage assembly, and contains two magnet pieces bonded on each actuator unit.
  • the fine stage magnets interact with the top and bottom coils (and return iron) of the respective actuator units.
  • the top surface of the fine stage that holds a semiconductor wafer includes a waffle pattern that has been lapped to be of uniform height.
  • Vacuum retains a wafer against the surface, and the space between each crown allows the vacuum to be ported to a single point underneath a wafer yet effective over the entire area of the wafer.
  • the common wafer robot 18 is made to travel along railway 40 for access to the wafer cassettes 16 for input or output of wafers from the system.
  • the EFEM 10 also contains a wafer aligner 20 on which the wafer robot places a wafer for precise setting of x, y and ⁇ orientation. Subsequently the robot may place the wafer in the process workstation 12 with the desired orientation on the transfer arms 11 and 13.
  • Each workstation incorporates two transfer arms 11, 13 and 15, 17 respectively for the purpose of rapidly loading wafers onto and off of the wafer chuck 32b, 32a. Because a swap wafer can be buffered locally delay is minimized.
  • Two-position rotary actuators drive the transfer arms. Vacuum retains the wafer on the transfer arm.
  • the wafer chuck lift pins pass through clearance holes in the fine stage and extend above the wafer chuck surface to pickup wafers from the a ⁇ ns (not shown).
  • the lift pins also use vacuum to retain the wafer as do the transfer arms.
  • the wafer robot loads wafers on and of the transfer arms.
  • Individual processing workstations may have a production and an engineering mode of operation and function that is independent of other workstations in the system with respect to all processing functions.
  • production mode the wafer having been placed on the wafer chuck requires alignment to the beam box.
  • the load controller 25 will identify the specific wafer loaded to the workstation.
  • the transfer arm 11 locates the wafer on the wafer chuck 32 and the beam box is moved by the course stage to the first process tile on the wafer.
  • the workstation then aligns to the targets on the wafer as previously described.
  • the control computer 24 then identifies the correct blast plan data for the wafer now calibrated and computes a blast trajectory for the fine stage to execute relative to that alignment.
  • Production modes of the graphical user interface allow an operator to start, stop, and intervene in routine production operations through a few on-screen push-buttons or their keyboard equivalents.
  • the specific operations and the range of system control that are accessible to an operator are predefined by a process engineer through an engineering mode interface.
  • Engineering mode allows laser process engineers to setup production mode processes for such systems. For each new wafer type the laser process needs to be prototyped and tested. This generally is a manual task where the process engineers execute a series of standard tests and evaluates the results optically through the systems microscope or with of system inspection and test.
  • the invention provides in accordance with various embodiments, therefore, a wafer processing system including an input handler station and a plurality of wafer processing stations.
  • Each wafer processing station includes a stage system for inducing relative motion of the wafer and a laser beam.
  • the invention provides a wafer processing system including an input handler station and a plurality of wafer processing stations, each wafer processing station including dual optical paths to a subject platform.
  • the invention provides a wafer processing system including an input handler station and a plurality of wafer processing stations, each wafer processing station including a link blowing system for ablating portions of a semiconductor substrate.
  • the invention provides a wafer processing system including an input handler station and a plurality of wafer processing stations, each wafer processing station including a memory repair system for repair a memory circuit in a semiconductor substrate.
  • Figures 3 A — 3E show illustrative examples of further embodiments of the invention wherein each includes a single input unit and multiple processing units.
  • Figure 3 A shows an input unit 64 that includes input ports 60 and 62.
  • the input unit 64 is in communication with processing units 66 and 68.
  • the system provides a rate of wafers per hour of processing / square meter of 1.08, and a percentage cost of 83% where a single processing unit coupled to a single input unit provides 1.04 wafers per hour of processing / square meter, and a percentage cost of 100%.
  • Figure 3B shows an input unit 74 that includes input ports 70 and 72.
  • the input unit 74 is in communication with processing units 76 and 78, and the system provides a rate of wafers per hour of processing / square meter of 1.22, and a percentage cost of 83%.
  • Figure 3 C shows an input unit 84 that includes input ports 80 and 82.
  • the input unit 84 is in communication with processing units 86 and 88, and the system provides a rate of wafers per hour of processing / square meter of 1.41, and a percentage cost of 77%.
  • Figure 3D shows an input unit 98 that includes input ports 90, 92, 94 and 96.
  • the input unit 98 is in communication with processing units 100, 102 and 104, and the system provides a rate of wafers per hour of processing / square meter of 0.84, and a percentage cost of 72.6%.
  • Figure 3E shows an input unit 110 that includes input robot 112 that provides wafers to tracks 114. From the tracks 114, the system is in communication with processing units 116, 118, 120 and 122, and the system provides a rate of wafers per hour of processing / square meter of 1.21, and a percentage cost of 83%.
  • wafers may be independently processed by workstations that share a common input station.
  • the independent processing may further be scheduled such that wafer processing input and output operations are staggered, providing that a wafer is never required to wait to be handled by the input station while another wafer is being handled by the input station.
  • each workstation may be employ shared utilities such as power and vacuum, yet may be independently processed through the use of switches that may isolate a work station from the others.
  • each workstation may employ one or more shared laser sources that are distributed, for example, along a branched fiber optic beam path.
  • a system of the invention begins (step 400) by downloading all blast data (step 402) to all of the workstations so that during operation any workstation may process any wafer.
  • This process is run by the load controller 25 independently but coordinated with the various workstations 12, 14 and their respective controllers 24.
  • the setup process proceeds to put a first wafer in each workstation (step 404) and identifying the wafer to the workstation (step 406) so processing can begin with minimum delay (step 408).
  • step 410 After all workstations have been populated with at least one wafer (step 410) and identified to a second station (step 412) processing of a wafer begins, the robot uses this down time to populate the unused transfer arm of each workstation with another wafer (steps 414,416, 418, 420) so there will be no delays when a wafer is completed caused by the robot servicing another workstation.
  • the system then begins the execution of a process cycle (step 408) of Figure 5 A.
  • the loading of further wafers onto the transfer arm involves loading a wafer on the first workstation second transfer arm (step 414), identifying the wafer to the first workstation (step 416), loading a wafer on the second workstation second transfer arm (step 418), and identifying the wafer to the second workstation (step 420).
  • the setup procedure then ends (step 422).
  • the process cycle from step 408 loads blast plan data in the real time controller (step 502) while the transfer arm loads the wafer onto the fine stage chuck (step 504) for alignment of the first wafer tile (step 506). Once the first process tile is aligned the trajectories for that wafer tile are calculated (step 508) and processing begins (step 510).
  • the processing involves aligning the next wafer tile, calculating the next trajectories in the control computer and processing the next wafer tile. If further tiles are to be processed, the above processing steps repeat (step 512). Once all tiles are processed for the wafer, the wafer is presented to the wafer robot on the transfer arm (step 514).
  • the multiple workstations may perform this process asynchronously due to the individual vibration isolation systems (28) in each workstation.
  • step 515) if a new wafer is available on the transfer arm (step 516) it is loaded on the chuck, the process cycle restarts immediately (step 408) and the load controller is notified that service is needed (step 518).
  • the wafer robot controller determines if there are more wafers to process (step 520). The robot may move the complete wafer to the cassette and pick a replacement for replenishing the transfer arm (step 522) or wait for the next service request (step 524).
  • the processing of the wafer (step 520) in particular involves loading a wafer from the transfer arm to the cassette, obtaining the new wafer from the cassette, loading a wafer on the just vacated transfer arm, and identifying the wafer to the station.
  • This buffering system is extremely efficient and compensates for the uncertainties of processing. Time to process may vary from 1 to 10 minutes depending on the number of links to be processed and considerable downtime would occur if the wafers transferred directly by a single robot. It is apparent, therefore, that one EFEM system only may be utilized to service multiple workstations efficiently. Another important aspect of this configuration is that each workstation functions autonomously when loaded so it is possible to not only run production lots in multiple workstations but to perform applications, setup and service to the units in an independent manner having the same advantages as stand alone systems. Service to the EFEM may affect multiple workstations, and highly reliable EFEMs with minimum service time are preferred.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Automation & Control Theory (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)

Abstract

La présente invention concerne un système de traitement de tranches de semi-conducteur permettant un traitement simultané de tranches. Le système de traitement de tranches de semi-conducteur comprend un poste d'entrée pour recevoir une pluralité de tranches à traiter, et une pluralité de postes de travail. Chaque poste de travail est couplé au poste d'entrée et comprend un dispositif étagé permettant un mouvement relatif de la tranche et un faisceau laser, un mandrin qui maintient une tranche à traiter et un système optique qui dirige une lumière laser vers la tranche à traiter. Un système intermédiaire assurant un transfert de la tranche entre le poste d'entrée et le poste de travail peut être asynchrone par rapport au traitement de la tranche sur le poste de travail respectif.
PCT/US2007/071846 2006-06-23 2007-06-22 Système et procédé de traitement de tranches de semi-conducteur Ceased WO2007150009A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US81612506P 2006-06-23 2006-06-23
US60/816,125 2006-06-23

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WO2007150009A1 true WO2007150009A1 (fr) 2007-12-27

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9048271B2 (en) 2011-09-29 2015-06-02 Asm International N.V. Modular semiconductor processing system

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6176667B1 (en) * 1996-04-30 2001-01-23 Applied Materials, Inc. Multideck wafer processing system
US6496927B1 (en) * 1999-06-09 2002-12-17 Amx Corporation Method and configuring a user interface for controlling a controlled device based upon a device class
US6573473B2 (en) * 2000-05-16 2003-06-03 General Scanning Inc. Method and system for precisely positioning a waist of a material-processing laser beam to process microstructures within a laser-processing site
US20050247891A1 (en) * 2004-05-06 2005-11-10 Mehran Asdigha Mechanical oscillator for wafer scan with spot beam

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6176667B1 (en) * 1996-04-30 2001-01-23 Applied Materials, Inc. Multideck wafer processing system
US6496927B1 (en) * 1999-06-09 2002-12-17 Amx Corporation Method and configuring a user interface for controlling a controlled device based upon a device class
US6573473B2 (en) * 2000-05-16 2003-06-03 General Scanning Inc. Method and system for precisely positioning a waist of a material-processing laser beam to process microstructures within a laser-processing site
US20050247891A1 (en) * 2004-05-06 2005-11-10 Mehran Asdigha Mechanical oscillator for wafer scan with spot beam

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9048271B2 (en) 2011-09-29 2015-06-02 Asm International N.V. Modular semiconductor processing system

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