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WO2007014115A1 - Dispositif electronique comportant des elements de stockage discontinus - Google Patents

Dispositif electronique comportant des elements de stockage discontinus Download PDF

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Publication number
WO2007014115A1
WO2007014115A1 PCT/US2006/028575 US2006028575W WO2007014115A1 WO 2007014115 A1 WO2007014115 A1 WO 2007014115A1 US 2006028575 W US2006028575 W US 2006028575W WO 2007014115 A1 WO2007014115 A1 WO 2007014115A1
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WO
WIPO (PCT)
Prior art keywords
gate electrode
trench
discontinuous storage
substrate
storage elements
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US2006/028575
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English (en)
Inventor
Gowrishankar L. Chindalore
Cheong M. Hong
Craig T. Swift
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NXP USA Inc
Original Assignee
Freescale Semiconductor Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US11/188,910 external-priority patent/US7205608B2/en
Priority claimed from US11/188,909 external-priority patent/US7226840B2/en
Application filed by Freescale Semiconductor Inc filed Critical Freescale Semiconductor Inc
Publication of WO2007014115A1 publication Critical patent/WO2007014115A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/69—IGFETs having charge trapping gate insulators, e.g. MNOS transistors
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/10—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B41/27—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/10—EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/68—Floating-gate IGFETs
    • H10D30/681—Floating-gate IGFETs having only two programming levels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/68—Floating-gate IGFETs
    • H10D30/687—Floating-gate IGFETs having more than two programming levels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/68—Floating-gate IGFETs
    • H10D30/6891—Floating-gate IGFETs characterised by the shapes, relative sizes or dispositions of the floating gate electrode
    • H10D30/6893—Floating-gate IGFETs characterised by the shapes, relative sizes or dispositions of the floating gate electrode wherein the floating gate has multiple non-connected parts, e.g. multi-particle floating gate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/68—Floating-gate IGFETs
    • H10D30/6891—Floating-gate IGFETs characterised by the shapes, relative sizes or dispositions of the floating gate electrode
    • H10D30/6894—Floating-gate IGFETs characterised by the shapes, relative sizes or dispositions of the floating gate electrode having one gate at least partly in a trench
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/69—IGFETs having charge trapping gate insulators, e.g. MNOS transistors
    • H10D30/691—IGFETs having charge trapping gate insulators, e.g. MNOS transistors having more than two programming levels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/69—IGFETs having charge trapping gate insulators, e.g. MNOS transistors
    • H10D30/693—Vertical IGFETs having charge trapping gate insulators
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/69—IGFETs having charge trapping gate insulators, e.g. MNOS transistors
    • H10D30/694—IGFETs having charge trapping gate insulators, e.g. MNOS transistors characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H10D30/697—IGFETs having charge trapping gate insulators, e.g. MNOS transistors characterised by the shapes, relative sizes or dispositions of the gate electrodes having trapping at multiple separated sites, e.g. multi-particles trapping sites
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/69—IGFETs having charge trapping gate insulators, e.g. MNOS transistors
    • H10D30/694—IGFETs having charge trapping gate insulators, e.g. MNOS transistors characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H10D30/699—IGFETs having charge trapping gate insulators, e.g. MNOS transistors characterised by the shapes, relative sizes or dispositions of the gate electrodes having the gate at least partly formed in a trench
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
    • G11C16/0441—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing multiple floating gate devices, e.g. separate read-and-write FAMOS transistors with connected floating gates
    • G11C16/0458—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing multiple floating gate devices, e.g. separate read-and-write FAMOS transistors with connected floating gates comprising two or more independent floating gates which store independent data
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0466—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS]
    • G11C16/0475—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] comprising two or more independent storage sites which store independent data
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2216/00—Indexing scheme relating to G11C16/00 and subgroups, for features not directly covered by these groups
    • G11C2216/02—Structural aspects of erasable programmable read-only memories
    • G11C2216/06—Floating gate cells in which the floating gate consists of multiple isolated silicon islands, e.g. nanocrystals
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology

Definitions

  • the present invention relates to electronic devices, and more particularly, to electronic devices that include discontinuous storage elements.
  • Floating gate non-volatile memories are conventional and are commonly used in many applications.
  • the three most common types of programming mechanisms for FG NVM include Fowler-Nordheim tunneling, conventional hot carrier injection, and source-side injection.
  • Fowler-Nordheim tunneling is efficient but is very slow. Efficiency can be measured by dividing the number of carriers that enter a floating gate or one or more other storage elements divided by the number of carriers that enter a memory cell having the floating or the other storage element(s). The latter number can be approximated by using the product of the programming current and the programming time.
  • Hot carrier injection can include conventional hot carrier injection and source-side injection. Both involve the generation of hot carriers, some of which are injected into the floating or the other storage element(s).
  • conventional hot carrier injection when using a floating gate, an electrical field is generated along a channel region of a memory cell. Within the channel region, the electrical field is the highest near the drain region. The electrical field accelerates carriers flowing within the channel region, such that, within the channel region, the carriers are traveling the fastest near the drain region. A small fraction of carriers collide with silicon or one or more other atoms within the channel region, redirecting the energetic carriers to the floating gate or other charge storage element(s). An electrical field generated by a control gate electrode can help inject some of that small fraction of the hot carriers into the floating gate.
  • Conventional hot carrier injection is inefficient and has high programming current.
  • Source-side injection is a popular compromise, with respect to efficiency and programming current, between Fowler-Nordheim tunneling and conventional hot carrier injection. With source-side injection, hot carriers are still generated, however, most of the hot carriers are generated within a portion of the channel region that is spaced apart from the drain region. Memory cells designed to be programmed by source-side injection are not without problems. Typically, the memory cells require one or more additional critical lithographic sequences and result in larger memory cells.
  • High density floating gate memories are becoming more difficult to fabricate in commercial volumes.
  • the thickness of the gate dielectric layer decreases, the likelihood of a pinhole or other defect extending through the thickness of the gate dielectric layer increases.
  • Such a defect can cause an electrical short or leakage path between the substrate and the floating gate.
  • the electrical short or leakage path can affect the voltage on the floating gate, and therefore, the memory cell may not be able to retain data.
  • One or more materials may be used for the gate dielectric layer instead of silicon dioxide, however, such material(s) may have other issues, such as material compatibility with other materials used in the memory cell, require new equipment, increase manufacturing costs, etc.
  • FIG. 1 includes an illustration of a cross-sectional view of a portion of a workpiece after formation of a protective layer.
  • FIG. 2 includes an illustration of a cross-sectional view of the workpiece of FIG. 1 after formation of trenches.
  • FIG. 3 includes an illustration of a cross-sectional view of a workpiece of FIG. 2 after formation of an insulating layer within the trenches.
  • FIGs. 4 and 5 include illustrations of a top view and a cross-sectional view, respectively, of the workpiece of FIG. 3 after formation of doped regions at the bottom the trenches.
  • FIG. 6 includes an illustration of a cross-sectional view of the workpiece of FIG. 5 after formation of a charge storage stack including discontinuous storage elements.
  • FIG. 7 includes an illustration of a cross-sectional view of the workpiece of FIG. 6 after formation of a conductive layer over the substrate.
  • FIG. 8 and 9 include illustrations of a top view and a cross-sectional view, respectively, of the workpiece in FIG. 7 after formation of gate electrodes.
  • FIG. 10 includes an illustration of a cross-sectional view of the workpiece of FIGs. 8 and 9 after removal of the dielectric layer from exposed portions of the charge storage stack within the array.
  • FIG. 11 includes an illustration of a cross-sectional view of the workpiece of FIG. 10 after removal of the remainder of the exposed portions of charge storage stack within the array.
  • FIG. 12 includes an illustration of a cross-sectional -view of the workpiece of FIG. 11 after formation of a dielectric layer including portions overlying gate electrodes within trenches.
  • FIG. 13 includes an illustration of a cross-sectional view of the workpiece of FIG. 12 after formation of a conducting layer.
  • FIG. 14 includes an illustration of a top view of the workpiece of FIG. 13 after formation of conductive lines.
  • FIG. 15 includes an illustration of a cross-sectional view of the workpiece of FIG. 12 after formation of conductive lines in accordance with an alternative embodiment.
  • FIG. 16 includes an illustration of a top view of the workpiece of FIG. 15 after formation of an implant masking layer.
  • FIGs. 17 and 18 include illustrations of a top view and a cross-sectional view, respectively of the workpiece of FIG. 16 after fabrication of an electronic device is substantially completed.
  • FIG. 19 includes an illustration of a top view of the workpiece of FIG. 14 after formation of doped regions within the substrate.
  • FIGs. 20 and 21 include illustrations of a top view and a cross-sectional view, respectively, of the workpiece of FIG. 19 after fabrication of an electronic device is substantially completed.
  • FIGs. 22 and 23 include illustrations of a top view and a cross-sectional view, respectively, of the workpiece of FIG. 13 after formation of doped regions within the substrate.
  • FIGs. 24 and 25 include illustrations of a top view and a cross-sectional view, respectively, of the workpiece of FIGs. 22 and 23 after fabrication of an electronic device is substantially completed.
  • FIG. 26 includes an illustration of a cross-sectional view of the workpiece of FIGs. 13 except with trenches that are more widely spaced apart from each other.
  • FIG. 27 includes an illustration of a top view of the workpiece of FIG. 26 after formation of overlying conducting lines.
  • FIGs. 28 and 29 include illustrations of a top view and a cross-sectional view of the workpiece of FIG. 27 after fabrication of an electronic device is substantially completed.
  • FIGs. 30 includes an illustration of a cross-sectional view of the workpiece of FIG. 6 after formation of a conductive layer.
  • FIGs. 31 includes an illustration of a cross-sectional view of the workpiece of FIG. 30 after formation of gate electrodes.
  • FIGs. 32 through 43 includes circuit schematic diagrams, cross-sectional views of exemplary physical embodiments of the circuit schematic diagrams, and operating voltage tables for memory cell along a row within an NVM array.
  • An electronic device can include discontinuous storage elements.
  • the electronic device can include a substrate that includes a first trench.
  • the trench can include a wall and a bottom and extends from a primary surface of the substrate.
  • the electronic device can also include discontinuous storage elements, wherein a first portion of the discontinuous storage elements lie at least within the first trench, and a second portion of the discontinuous storage elements lie along the primary surface of the substrate adjacent to the first trench.
  • the second portion of the discontinuous storage elements can be spaced apart from the first portion of the discontinuous storage elements.
  • the electronic device can further include a first gate electrode overlying at least the second set of the discontinuous storage elements, wherein an upper surface of the first gate electrode lies below the primary surface of the substrate.
  • the electronic device can also include a second gate electrode overlies the first gate electrode.
  • Embodiments described herein also include processes for forming the electronic device.
  • the electronic device can include a memory array in which bit lines, gate lines, or any combination thereof can take advantage of the trench design and buried bit lines.
  • at least one of the memory cells can include a gate electrode that includes a control gate portion and a select gate portion.
  • a select gate line may be electrically connected to a different number of rows or columns of memory cells as compared to a control gate line.
  • a select gate line may be electrically connected to one row or one column of memory cells, and the control gate line may be electrically connected to two rows or two columns of memory cells.
  • a similar relationship may exist for bit lines.
  • a select gate line and a control gate line may be substantially perpendicular to each other.
  • the select gate line may be electrically connected to a different number of rows or columns of memory cells as compared to the control gate line.
  • a select gate line may be electrically connected to one row or one column of memory cells, and the control gate line maybe electrically connected to two columns or two rows of memory cells.
  • discontinuous storage elements is intended to mean spaced-apart objects capable of storing a charge.
  • substantially all discontinuous storage elements may be initially formed and remain separate from one another.
  • a substantially continuous layer of material formed an later separated into discontinuous storage elements.
  • substantially all discontinuous storage elements may be initially formed separate from one another, and later during the formation, some but not all of the discontinuous storage elements may coalesce.
  • the term "primary surface" is intended to mean a surface of a substrate from which memory cells within a memory array are subsequently formed.
  • the primary surface may be an original surface of a substrate before forming any electronic components or may be a surface from which trenches or other permanent structures within the memory array are formed.
  • the memory array may be formed at least partly within an epitaxial layer overlying a base material, and electronic components within peripheral area (outside the memory array) may be formed from the base material.
  • the primary surface refers to the upper surface of the epitaxial layer, and not the original surface of the base material.
  • a non-volatile memory stack can include layers used to form at least part of a non-volatile memory cell.
  • a stack may be part of a larger stack.
  • a non- volatile memory stack can include a charge storage stack that is used to store charge within a non-volatile memory cell.
  • the terms “comprises,” “comprising,” “includes,” “including,” “has,” “having” or any other variation thereof, are intended to cover a non-exclusive inclusion.
  • a process, method, article, or apparatus that comprises a list of elements is not necessarily limited to only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus.
  • "or” refers to an inclusive or and not to an exclusive or. For example, a condition A or B is satisfied by any one of the following: A is true (or present) and B is false (or not present), A is false (or not present) and B is true (or present), and both A and B are true (or present).
  • FIG. 1 includes an illustration of a cross-sectional view of a portion of electronic device 10, such as an integrated circuit.
  • the integrated circuit can be a standalone memory, a microcontroller, or other integrated circuit that includes a memory.
  • electronic device 10 can include non- volatile memory ('TSIVM") array 14, a portion of which is illustrated in FIG. 1.
  • Substrate 12 can include a monocrystalline semiconductor wafer, a semiconductor-on-insulator wafer, a flat panel display (e.g., a silicon layer over a glass plate), or other substrate conventionally used to form electronic devices.
  • the upper surface of substrate 12 is primary surface 13.
  • the doping concentration of substrate 12 along primary surface 13 within NVM array 14 can be increased using a conventional doping operation to potentially reduce leakage current between subsequently- formed gate electrodes that may overlie portions of primary surface 13.
  • shallow trench field isolation may be formed over portions of substrate 12 in peripheral areas, which are outside the NVM array 14.
  • an optional sacrificial layer may be formed and removed. A sacrificial layer can improve the properties of subsequently-formed dielectric layers.
  • Charge storage stack 16, including dielectric layer 18, discontinuous storage elements 110, and dielectric layer 112 can then formed, as illustrated in FIG. 1. In one embodiment, charge storage stack 16 is formed immediately adjacent to primary surface 13.
  • Dielectric layer 18 may be thermally grown using an oxidizing or nitridizing ambient, or deposited using a conventional chemical vapor deposition technique, physical vapor deposition technique, atomic layer deposition technique, or a combination thereof.
  • Dielectric layer 18 can include one or more films of silicon dioxide, silicon nitride, silicon oxynitride, a high dielectric constant ("high-k”) material (e.g., dielectric constant greater than 8), or any combination thereof.
  • high-k high dielectric constant
  • the high-k material can include Hf 3 O b N 0 , Hf a Si b O c , Hf a Si b O c N d , Hf a Zr b O c N d , Hf a Zr b Si c O d Ne, Hf a Zr b O c , Zr a Si b O c , Zr a Si b O c N d , ZrO 2 , other Hf-containing or Zr- containing dielectric material, a doped version of any of the foregoing (lanthanum doped, niobium doped, etc.), or any combination thereof.
  • Dielectric layer 18 can have a thickness in a range of approximately 1 to approximately 10 nm. The thickness and material selection of dielectric layer 18 will substantially determine its electrical properties. In one embodiment the thickness and material are chosen such that dielectric layer 18 has a silicon dioxide equivalent thickness of less than 10 nm.
  • Discontinuous storage elements 110 are then formed over NVM array 14.
  • Discontinuous storage elements 110 are substantially physically separated one from another.
  • Discontinuous storage elements 110 can include a material capable of storing a charge, such as silicon, a nitride, a metal-containing material, another suitable material capable of storing charge, or any combination thereof.
  • discontinuous storage elements 110 can include silicon nanocrystals or metal nanoclusters.
  • a substantially continuous layer of amorphous silicon can be formed over exposed surfaces of substrate 12. The substantially continuous layer can be exposed to heat or other processing conditions that can cause the layer to "ball up" or otherwise form silicon nanocrystals.
  • Discontinuous storage elements 110 may be undoped, doped during deposition, or doped after deposition.
  • discontinuous storage elements 110 can be formed from one or more materials whose properties are not significantly adversely affected during a thermal oxidation process.
  • a material can include platinum, palladium, iridium, osmium, ruthenium, rhenium, indium-tin, indium-zinc, aluminum-tin, or any combination thereof.
  • Each of such materials, other than platinum and palladium, may form a conductive metal oxide.
  • each of discontinuous storage elements 110 is no greater than approximately 10 nm in any dimension.
  • discontinuous storage elements 110 can be larger, however, discontinuous storage elements 110 are not formed so large as to form a continuous structure (i.e., all discontinuous storage elements 84 are not fused together). Thus, during formation of the discontinuous storage elements 110, some individual portions may coalesce to form clusters, however, such clusters are discontinuous storage elements 110.
  • Dielectric layer 112 is then formed over discontinuous storage elements 110.
  • Dielectric layer 112 can include one or more dielectric films.
  • Dielectric layer 112 can include any one or more materials or be formed using any of the embodiments as described with respect to dielectric 18 layer.
  • Dielectric layer 112 can have the same or different composition compared to dielectric 18 layer and may be formed using the same or different formation technique compared to dielectric layer 18.
  • a protective layer 114 can be formed which includes intervening layer 116 and oxidation-resistant layer 118.
  • Intervening layer 116 can function as a pad layer during processing.
  • remaining portions of intervening layer 116 can be conductive or made to be conductive (e.g., by doping) and can set the work function for charge storage stack 16.
  • intervening layer 116 can be polysilicon, doped polysilicon, metal, or a metal-containing material.
  • intervening layer 116 can be less than approximately 200 nm in thickness.
  • Oxidation-resistant layer 118 can be formed using one or more conventional techniques.
  • Protective layer 114 can include intervening layer 116 and oxidation-resistant layer 118.
  • oxidation-resistant layer 118 includes a nitride.
  • a patterned resist layer (not illustrated), which includes openings at locations within NVM array 14 where trenches are to be formed, is formed over substrate 12 by a conventional technique. Exposed portions of overlying layers can then be removed by a conventional technique to expose primary surface 13. hi one embodiment, trenches 22 and 23, as illustrated in FIG. 2, are formed prior to removal of the patterned resist layer. In another embodiment, the patterned resist layer is removed, and trenches 22 and 23 can then be formed by a conventional technique. Trenches 22 and 23 are spaced apart from each other, extend into substrate 12 from primary surface 13, and each includes a wall and a bottom.
  • the depth of trenches 22 and 23 can, at least in part, determine the channel length of one or more of the memory cells being formed adjacent to trenches 22 and 23. In one embodiment, the depths of trenches 22 and 23 are in a range of approximately 50 to approximately 500 nm. In one particular embodiment, trenches 22 and 23 are formed using a timed anisotropic etch to produce substantially vertical walls. In one embodiment, trenches 22 and 23 have substantially uniform depths.
  • Insulating layer 32 is formed along the exposed surfaces of trenches 22 and 23, as illustrated in FIG. 3. Insulating layer 32 may or may not be substantially conformal. In one embodiment, insulating layer 32 may include an oxide, a nitride, an oxynitride, or a combination thereof. In one embodiment, insulating layer 32 can be used as an implant screen. In one particular embodiment, insulating layer 32 is formed by thermally oxidizing the exposed portions of substrate 12 within trenches 22 and 23. Thermal oxidation can be beneficial in removing defects, such as those induced by etching, help to round corners of trenches 22 and 23, or a combination thereof. In another embodiment (not illustrated), insulating layer 32 can be deposited. A deposited insulating layer 32 would cover substantially all exposed surfaces of the workpiece.
  • a dopant is introduced into portions of substrate 12 at the bottom of trenches 22 and 23 to form doped regions 52 and 53, as illustrated in top and cross-.sectional views, in FIGs. 4 and 5, respectively.
  • doped regions 52 and 53 are not illustrated to simplify understanding of positional relationships between features within NVM array 14.
  • Doped region 52 lies within substrate 12 and below trench 22, and doped region 53 lies within substrate 12 and below trench 23.
  • doped regions 52 and 53 can be source/drain ("S/D") regions and act as buried bit lines.
  • the dopant may be a p-type dopant (e.g., boron) or an n-type dopant (e.g., phosphorus or arsenic).
  • the dopant can be introduced using ion implantation.
  • An optional thermal cycle can be performed to activate the dopant.
  • subsequent processing may have one or more thermal cycles capable of activating the dopant.
  • the doping concentration of doped regions 52 and 53 is at least approximately 1E19 atoms/cm 3 .
  • Charge storage stack 68 including dielectric layer 62, discontinuous storage elements 64, and dielectric layer 66 can then formed, as illustrated in FIG. 6.
  • insulating layer 32 can be removed prior to formation of dielectric layer 62 over the exposed surface of trenches 22 and 23, including the walls and bottoms of trenches 22 and 23.
  • insulating layer 32 is used in place of or in conjunction with dielectric layer 62.
  • Charge storage stack 68 can be formed following an embodiment previously described for charge storage stack 16. Portions of charge storage stack 68 maybe formed of the same or different materials as charge storage stack 16 and be formed by the same or different techniques as charge storage stack 16.
  • the set of discontinuous storage elements 110 may have the same or different composition as compared to the set of discontinuous storage elements 64.
  • Conductive layer 72 is then formed overlying the workpiece, as illustrated in FIG. 7.
  • Conductive layer 72 can include one or more semiconductor-containing or metal-containing films.
  • conductive layer 72 includes polysilicon or amorphous silicon deposited by a chemical vapor deposition process.
  • conductive layer 72 may include one or more other materials or may be deposited by another process.
  • conductive layer 72 is doped when deposited, and in another particular embodiment, is doped after it is deposited. The thickness of conductive layer 72 is sufficient to at least substantially fill in the trenches within NVM array 14.
  • the thickness of conductive layer 72 is in a range of approximately 50 to approximately 500 nm, and in a finished device, remaining portions of conductive layer 72 have a dopant concentration of at least approximately IE 19 atoms/cm 3 when conductive layer 72 includes polysilicon or amorphous silicon.
  • Portions of conducting layer 72 lying outside trenches 22 and 23 can be removed, as illustrated in FIGs. 8 and 9. Additional portions of conductive layer 72 are removed such that the remaining portions of conductive layer 72 are recessed below primary surface 13 and contained within trenches 22 and 23 to form gate electrodes 92 and 93, each of which has an upper surface that lies below primary surface 13.
  • Gate electrode 92 overlies one portion of discontinuous storage elements 64 within trench 22, and gate electrode 93 overlies another portion of discontinuous storage elements 64 within trench 23.
  • Each of gate electrodes 92 and 93 lies adjacent to a wall portion of discontinuous storage elements 64 within trenches 22 and 23 respectively.
  • each of gate electrodes 92 and 93 has a substantially rectangular shape, as seen from a cross-sectional view.
  • conductive layer 72 is undoped polysilicon, as initially deposited.
  • Gate electrodes 92 and 93 are then doped by conventional techniques such that in a finished device, gate electrodes 92 and 93 have a concentration of at least approximatelylE19 atoms/cm 3 .
  • a material capable of reacting with silicon to form a suicide and can include Ti, Ta, Co, W, Mo, Zr, Pt, other suitable material, or any combination thereof is formed on gate electrodes 92 and 93 and reacted to form a metal suicide.
  • removal of a portion of conductive layer 72 is accomplished by polishing with a conventional technique to expose oxidation-resistant layer 118, followed by a timed etch. In another embodiment (not illustrated), the removal is accomplished by an etch process without polishing. In another embodiment, portions of charge storage stack 68 may remain overlying protective layer 116. In another embodiment the recess, which is the elevational difference between the primary surface 13 and the upper surfaces of the gate electrodes 92 and 93, is between 20% and 80% of the depth of trenches 22 and 23.
  • Exposed portions of dielectric layer 66 are removed, exposing discontinuous storage elements 64, as illustrated in FIG. 10. Exposed discontinuous storage elements 64 are then removed, as illustrated in FIG. 11, or rendered incapable of storing charge (not illustrated). In one embodiment, a wet etch of exposed portions of dielectric layer 62 undercuts discontinuous storage elements 64, allowing them to be rinsed away. In one particular embodiment (not illustrated), discontinuous storage elements 64 are silicon crystals that are oxidized to form silicon dioxide. In one embodiment, at this point in the process, substantially no discontinuous storage elements 64 overlie primary surface 13 or along walls of trenches 22 and 23 that lie above the upper surfaces of gate electrodes 92 and 93 within NVM array 14.
  • An intergate dielectric layer including dielectric portions 122 and 123 is then formed over NVM array 14, as illustrated in FIG 12.
  • Dielectric portion 122 can overlie gate electrode 92 and dielectric portion 123 can overlie gate electrode 93.
  • the intergate dielectric layer can include one or more dielectric films, any of which may be thermally grown or deposited.
  • the intergate dielectric layer can include any one or more materials or be formed using any of the embodiments as described with respect to dielectric layer 18.
  • the intergate dielectric layer can have the same or different composition compared to dielectric layer 18 and may be formed using the same or different formation technique compared to dielectric layer 18.
  • the thickness of dielectric portions 122 and 123 can affect the electrical fields within the channel regions of the memory cells.
  • the electrical field is designed to provide the highest change in electrical field within the channel region for each memory cell to allow for source-side injection.
  • the thickness of dielectric portions 122 and 123 is in a range of approximately 10 to approximately 30 nm.
  • dielectric portions 122 and 123 may contain oxidized portions of discontinuous storage elements 64.
  • charge storage stack 68 includes a set of discontinuous storage elements 64, a portion of which lies within trench 22 and another portion of which lies within trench 23, and charge storage stack 16 includes another set of discontinuous storage elements 110 that overlie primary surface 13 of substrate 12.
  • the set of discontinuous storage elements 110 are spaced apart from the set of discontinuous storage elements 64 that lie within trenches 22 and 23.
  • the set of discontinuous storage elements 110 are not contiguous with the set of discontinuous storage elements 64, and the sets are spaced apart from each other by dielectric portion 122 or 123.
  • Conductive layer 132 is formed over NVM array 14, as illustrated in FIG. 13.
  • Conductive layer 132 can be formed of one or more materials, following an embodiment previously described with respect to conducting layer 72. The material or technique used could be the same or different than the one used to form conducting layer 72.
  • the thickness of conductive layer 132 is in a range of approximately 20 to approximately 300 nm.
  • conductive layer 132 has a dopant concentration of at least approximately IEl 9 atoms/cm 3 when conductive layer 132 includes polysilicon or amorphous silicon.
  • Conductive layer 132 is patterned by etching using a conventional technique to form conductive lines 142 and 143, which include gate electrodes, illustrated in FIG 14.
  • Conductive lines 142 and 143 can lie at least partly within trench 22, trench 23, one or more other trenches (not illustrated) within NVM array 14, or any combination thereof. In one embodiment, the lengths of conductive lines 142 and 143 are substantially perpendicular to the lengths of trenches 22 and 23 within NVM array 14.
  • a material capable of reacting with silicon to form a suicide e.g., Ti, Ta, Co, W, Mo, Zr, Pt, other suitable material, or any combination thereof
  • conductive lines 142 and 143 can be used as word lines for NVM array 14, with portions thereof acting as gate electrodes for plurality of bit cells.
  • charge storage stack 16 In another embodiment (not illustrated), exposed portions of charge storage stack 16 are removed. In a further embodiment, an insulating layer (not illustrated) may be formed overlying areas previously covered by portions of charge storage stack 16. Optionally, sidewall spacers may be formed adjacent to conductive lines 142 and 143.
  • NVM array 14 is substantially complete.
  • peripheral electrical connections (not illustrated) are made to access conductive portions of NVM array 14.
  • Protective layer 114 overlying the peripheral areas of substrate 12 can be removed, and another protective layer (not illustrated) can be formed over NVM array 14, which may protect NVM array 14 during component fabrication within the peripheral areas. Processing can be continued to form a substantially completed electronic device.
  • One or more insulating layers, one or more conductive layers, and one or more encapsulating layers are formed using one or more conventional techniques.
  • NVM array 14 layout and interconnect scheme may be used.
  • the process through formation of conductive layer 132 over all of NVM array 14 (FIGs. 1 through 13) can be performed using any embodiment as previously described.
  • Conductive layer 132 can be patterned and etched to form conductive lines 152 through 155, as illustrated in FIG 15.
  • the conductive lines 152 through 155 can act as word lines in the NVM array 14.
  • the lengths of conductive lines 152 through 155 are substantially parallel to the lengths of trenches 22 and 23.
  • portions of conductive lines 152 through 155 can lie within the recesses of trenches 22 and 23.
  • the composition and method of formation of conductive lines 152 through 155 maybe any of those described with respect to formation of conductive lines 142 and 143.
  • exposed portions of charge storage stack 16 can be removed.
  • an insulating layer may be formed over exposed portions of primary surface 13 of substrate 12 and along exposed surfaces of conductive lines 142 and 143.
  • sidewall spacers 154 may be formed adjacent to conductive lines 152 through 155.
  • Patterned resist layer 162 is formed over the workpiece.
  • openings in patterned resist layer 162 substantially correspond to locations over which bit lines will subsequently be formed.
  • one or more features overlying substrate 12 may or may not be removed between conductive lines 152 through 155.
  • a dopant is introduced into portions of substrate 12 to form doped regions 164.
  • Doped regions 164 may be formed by an embodiment previously described for formation of doped regions 52 and 53. Doped regions 164 can be the same or different material as doped regions 52 and 53 and can be formed by the same or different technique.
  • Patterned resist layer 162 is then removed by a conventional technique.
  • each of doped regions 164 has a dopant concentration of at least approximately IEl 9 atoms/cm 3 .
  • portions of doped regions 164 serve as S/D regions.
  • NVM array 14 is now substantially complete other than electrical connections. Remaining portions of protective layer 114 (not illustrated in FIG. 16) that overlie the peripheral areas of substrate 12 are removed, and another protective layer (not illustrated) can be formed over NVM array 14 which may protect NVM array 14 during component fabrication within the peripheral areas. Component fabrication within the peripheral areas can be performed using one or more conventional techniques. After the component fabrication within the peripheral areas is substantially completed, the protective layer overlying NVM array 14 can be removed.
  • Interlevel dielectric layer 182 is formed over the workpiece by a conventional technique. Interlevel dielectric layer 182 is patterned to form contact openings that extend to doped regions 164 and to other portions of NVM array 14 that are not illustrated in FIGs. 17 and 18. Interlevel dielectric layer 182 can include an insulating material, such as an oxide, a nitride, an oxynitride, or a combination thereof. In a specific embodiment, an anisotropic etch can be used to form contact openings.
  • Conductive plugs 172 and conductive lines 174 and 175 are then formed, as illustrated in FIG. 17.
  • the lengths of conductive lines 174 and 175 are substantially perpendicular to the lengths of conductive lines 152 and 153.
  • conductive lines 174 and 175 are bit lines for NVM array 14, and conductive plugs 172 are bit line contacts.
  • doped regions 164 underlie conductive lines 174 and 175 between portions of substrate 12 not covered by conductive lines 174 and 175.
  • conductive plugs 172 are formed prior to conductive lines 174 and 175.
  • a conductive layer (not illustrated) is formed over interlevel dielectric layer 182 and substantially fills contact openings therein. Portions of the conductive layer that lie outside the contact openings are removed to form conductive plugs 172.
  • a conventional chemical-mechanical polishing operation can be performed, and in another embodiment, a conventional etching process can be performed.
  • Another insulating layer (not illustrated) is then deposited and patterned to form trenches where conductive lines 174 and 175 will subsequently be formed. Other trenches can be formed at locations within NVM array 14, outside NVM array 14, or a combination thereof.
  • another conductive layer is formed over interlevel dielectric layer 182 and substantially fills the trenches in the insulating layer. Portions of the conductive layer that lie outside the trenches within the insulating layer are removed to form conductive lines 174 and 175.
  • a conventional chemical-mechanical polishing operation can be performed, and in another embodiment, a conventional etching process can be performed.
  • the insulating layer can lie at substantially the same elevation between conductive lines 174 and 175.
  • conductive plugs 172 and conductive lines 174 and 175 are formed concurrently using a conventional dual-inlaid process.
  • Conductive plugs 172 and conductive lines 174 and 175 can include the same or different conducting materials. Each of conductive plugs 172 and conductive lines 174 and 175 can include doped silicon, tungsten, titanium, tantalum, titanium nitride, tantalum nitride, aluminum, copper, another suitable conductive material, or any combination thereof. In one particular embodiment, conductive plugs 172 include tungsten, and conductive lines 174 and 175 include copper. An optional barrier layer, adhesion layer, or a combination thereof may be formed before the corresponding conductive layers (e.g., tungsten for conductive plugs 172 and copper for conductive lines 174 and 175). An optional capping layer (e.g., a metal- containing nitride) may be used to encapsulate copper within conductive lines 174 and 175.
  • An optional capping layer e.g., a metal- containing nitride
  • additional insulating and conductive layers can be formed and patterned to form one or more additional levels of interconnects.
  • passivation layer 184 is formed over substrate 12, including NVM array 14 and peripheral areas.
  • Passivation layer 184 can include one or more insulating film, such as an oxide, a nitride, an oxynitride, or a combination thereof.
  • yet another NVM array 14 layout and interconnect scheme may be used.
  • the process through formation of conductive lines 142 and 143 (FIG. 14) can be performed using any embodiment as previously described with respect to FIGs. 1 to 14.
  • remaining portions (not illustrated) of protective layer 114 that overlie the peripheral areas of substrate 12 are removed, and another protective layer (not illustrated) can be formed over NVM array 14 which may protect NVM array 14 during component fabrication within the peripheral areas.
  • Component fabrication within the peripheral areas can be performed using one or more conventional techniques. After the component fabrication within the peripheral areas is substantially completed, the protective layer overlying NVM array 14 can be removed.
  • the remainder of processing for the peripheral areas and NVM array 14 can occur substantially simultaneously.
  • exposed portions of charge storage stack 16 may be removed.
  • An insulating layer (not illustrated) may be formed overlying primary surface 13 of substrate 12 and along exposed surfaces of conductive lines 142 and 143.
  • a dopant is introduced into substrate 12 to form doped regions 192 at locations between conductive lines 142 and 143 and outside and adjacent to trenches 22 and 23, as illustrated in FIG. 19.
  • Doped regions 192 can include any one or more materials or be formed using any of the embodiments as described with respect to doped regions 52 and 53.
  • the insulating layer can have the same or different composition compared to doped regions 52 and 53 and may be formed using the same or different formation technique compared to doped regions 52 and 53.
  • spacers may be formed adjacent to conductive lines 142 and 143 before, after, or between individual actions used in forming doped regions 192.
  • the optional sidewall spacers can be formed as previously described regarding other embodiments.
  • doped regions 192 can serve as S/D regions in the finished device.
  • each of doped regions 192 has a dopant concentration of at least approximatelylE19 atoms/cm 3 .
  • a metal suicide can be formed from portions of conductive lines 142 and 143, doped regions 192, or any combination thereof using a conventional technique.
  • Interlevel dielectric layer 182 is then formed with contact openings using any of the embodiments as previously described. Referring to FIGs. 20 and 21, conductive plugs 202 are then formed using any embodiment as previously described for conductive plugs 172. The locations of the contact openings are changed as compared to a prior embodiment in that contact openings extend to doped region 192.
  • Insulating layer 203 can be formed by depositing an insulating material and patterned to define interconnect trenches. Conductive lines 204 through 206 are then formed within the interconnect trenches using any embodiment as previously described for conductive lines 174 and 175.
  • Conductive lines 204 through 206 can serve as bit lines within NVM array 14.
  • the orientation of conductive lines 204 through 206 is different from the orientation of conductive lines 174 and 175.
  • the lengths of conductive lines 204 through 206 are substantially perpendicular to the lengths of conductive lines 142 and 143, as illustrated in FIG. 20.
  • additional insulating and conductive layers can be formed and patterned to form additional levels of interconnects.
  • passivation layer 184 is formed over substrate 12, including NVM array 14 and peripheral areas.
  • Passivation layer 184 can include one or more insulating film, such as an oxide, a nitride, an oxynitride, or a combination thereof.
  • NVM array 14 layout and interconnect scheme may be used.
  • the layout and interconnect scheme is similar to an embodiment as illustrated in FIGs. 1 through 13 and 18 through 20 except that a virtual ground array architecture is used, rather than conductive lines 194 through 196.
  • the layout and organization will become more apparent after reading the description below with respect to FIGs. 22 to 25.
  • openings 220 are formed within the protective layer 110, and doped regions 224, 225, and 226 are formed along primary substrate 13 of substrate 12 outside trenches 22 and 23, as illustrated in FIGs. 22 and 23, which are similar to FIGs 4 and 5, respectively.
  • Openings 220 and doped regions 224, 225, and 226 can be formed using one or more conventional techniques. Openings 220 can be formed before or after forming trenches 22 and 23. For example, all openings within protective layer 110 may be formed at substantially simultaneously.
  • a mask (not illustrated) can be formed over opening 220 to substantially prevent forming a trench below openings 220. The mask can be removed after forming trenches 22 and 23.
  • a different mask may be formed over openings 220 after trenches 22 and 23 have been formed, and the different mask can be removed after forming openings 220.
  • Insulating layer 32 can be formed along the bottoms of openings 220 in a manner similar to the embodiment described with respect to FIG. 3.
  • Doped regions 224, 225, and 226 can be formed using any one or more of the embodiments as described with respect to doped regions 52 and 53.
  • the dopant species, concentration, and profile and formation of doped regions 224, 225, and 226 may be the same or different as compared to doped regions 52 and 53.
  • doped regions 224, 225, and 226 can be formed substantially simultaneously with doped regions 52 and 53.
  • Each of doped regions 52, 53, 224, 225, and 226 have lengths that are substantially parallel to one another and can act as buried bit lines.
  • Doped regions 52 and 53 lie at elevations deeper within substrate 12, as compared to doped regions 224, 225, and 226.
  • openings 220 are not formed. Instead, after forming trenches 22 and 23, remaining portions of protective layer 110 within NVM array 14 are removed before forming insulating layer 32. Doped regions 224, 225, and 226 can be formed when doped regions 52 and 53 are formed. Doped regions 224, 225, and 226 can extend to walls of trenches 22 and 23.
  • FIGs. 24 and 25 include illustrations of a portion of NVM array 14 are formation of the NVM array is substantially completed. As compared to the conductive lines 194 through 196 in FIGs. 19 and 20, doped regions 224 through 226 can be used in place of conductive lines 194 to 196.
  • peripheral electrical connections are made to access conductive portions of NVM array 14.
  • Protective layer 110 overlying the peripheral areas of substrate 12 can be removed, and another protective layer (not illustrated) can be formed over NVM array 14, which may protect NVM array 14 during component fabrication within the peripheral areas. Processing can be continued to form a substantially completed electronic device.
  • One or more insulating layers, one or more conductive layers, and one or more encapsulating layers are formed using one or more conventional techniques.
  • still another NVM array 14 layout and interconnect scheme may be used. The layout and interconnect scheme is similar to an embodiment as illustrated in FIGs.
  • bit lines lie between trenches 22 and 23, and electrical connections are made between the bit lines and only some of the doped regions underlying the bit lines.
  • the layout and organization will become more apparent after reading the description below with respect to FIGs. 26 to 29.
  • the process through formation of conductive lines 142 and 143 can be performed using any embodiment as previously described with respect to FIGs. 1 to 14.
  • the space between trenches 22 and 23 may be increased to allow for the proper formation of bit lines and contacts consistent with the design rules, as illustrated in FIG. 26.
  • remaining portions (not illustrated) of protective layer 114 that overlie the peripheral areas of substrate 12 are removed, and another protective layer (not illustrated) can be formed over NVM array 14 which may protect NVM array 14 during component fabrication within the peripheral areas.
  • Component fabrication within the peripheral areas can be performed using one or more conventional techniques. After the component fabrication within the peripheral areas is substantially completed, the protective layer overlying NVM array 14 can be removed.
  • Doped regions 192 and conductive lines 142 and 143 are formed by a previously described embodiment, as illustrated in FIG. 27.
  • Conductive plugs 242, conductive lines 244 through 247, as illustrated in FIGs. 27 and 28, are formed using an embodiment previously described with respect to formation and patterning of conductive plugs 202 and conductive lines 204 through 206.
  • Conductive lines 244 through 247 can serve as bit lines within NVM array 14.
  • the locations of conductive plugs 242 and conductive lines 244 through 247 are different from those illustrated for conductive plugs 202 and conductive lines 204 through 206, respectively.
  • the orientation of conductive lines 244 through 247 is substantially the same as the orientation of conductive lines 204 through 206.
  • each of conductive lines 244 through 247 has electrical connections via conductive plugs 242 to only some of the underlying doped regions 192.
  • the electrical connections to underlying doped regions 192 are alternated between conductive lines 245 and 246.
  • conductive line 245 is electrically connected to the middle row of doped regions 192
  • a conductive line 246 is electrically connected to the top and bottom rows of doped regions 192.
  • additional insulating and conductive layers can be formed and patterned to form additional levels of interconnects.
  • passivation layer 184 is formed over substrate 12, including NVM array 14 and peripheral areas.
  • Passivation layer 184 can include one or more insulating film, such as an oxide, a nitride, an oxynitride, or a combination thereof.
  • the gate electrodes within trenches 22 and 23 can have a shape similar to a sidewall spacer.
  • the process may start with the workpiece as illustrated in FIG. 6.
  • Conductive layer 262 can be deposited as illustrated in FIG. 30.
  • conductive layer 262 is a relatively thinner, substantially conformal layer.
  • Conductive layer 262 can be formed using any one or more embodiments as described with respect to conductive layer 72.
  • the thickness of conductive layer 262 is insufficient to fill in trenches 22 and 23 within NVM array 14. In one embodiment, the thickness of conductive layer 262 is in a range of approximately 10 nm to approximately 100 run.
  • gate electrodes 272 and 273 illustrated in FIG. 31.
  • gate electrodes 272 and 273 can have substantially sidewall spacer shapes within trenches 22 and 23.
  • gate electrodes 272 and 273 are annular when initially formed, in that each of gate electrodes 272 and 273 lies along the perimeter of trenches 22 and 23.
  • the spaced-apart left and right portions with facing curved surfaces for each of gate electrodes 272 and 273 within each of trenches 22 and 23 are connected to each other.
  • the processing of NVM array 14 can then be completed as previously described for other embodiments.
  • an additional isotropic etch portion may be used to reduce the likelihood of forming an unintended electrical connection or leakage path between subsequently-formed conductive lines 142 and 143.
  • doped regions that are at least part of source/drain regions for the memory cells within NVM array 18 have an opposite conductivity type as compared to substrate 12.
  • the portion of substrate 12 as illustrated in the figures may or may not lie within one or more well regions. Such well region(s) may be different from one or more other well regions within peripheral areas (outside NVM array 18).
  • Other doping can be performed that may affect breakdown voltages, resistivity, threshold voltage, hot carrier generation, one or more other electrical characteristics, or any combination thereof. Skilled artisans will be able to form electronic devices having doping characteristics that meet their needs or desires.
  • NVM array 14 can include memory cells using any of the layouts as previously described. Circuit schematics and cross references to physical embodiments are described to illustrate better how memory cells within NVM array 14 can be electrically configured and programmed.
  • FIG. 32 includes a circuit schematic for an embodiment as described with respect to the embodiment as illustrated in FIG. 33.
  • Memory cells 2811, 2812, 2821, and 2822 are oriented within NVM array 14, as illustrated in FIG. 32.
  • BL refers to a bit line
  • GL refers to a gate line.
  • a GL can be a control gate line or a select gate line, depending on the biasing conditions.
  • BLl 2862 is electrically connected to a S/D region of memory cell 2811 and a S/D region of memory cell 2821.
  • BL2 2864 is electrically connected to the other S/D regions of memory cells 2811 and 2821 and to a S/D region of memory cell 2812 and a S/D region of memory cell 2822.
  • BL3 2866 is electrically connected to the other S/D regions of memory cells 2812 and 2822.
  • GLl 2842 is electrically connected to a gate electrode of memory cell 2811 and a gate electrode of memory cell 2821.
  • GL2 2844 is electrically connected to gate electrodes of memory cells 2811 and 2812.
  • GL3 2846 is electrically connected to other gate electrodes of memory cells 2811 and 2821 and to a gate electrode of memory cell 2812 and a gate electrode of memory cell 2822.
  • GL42848 is electrically connected to gate electrodes of memory cells 2812 and 2822.
  • GL5 2805 is electrically connected to other gate electrodes of memory cells 2821 and 2822.
  • Each of GL2 2844 and GL5 2849 are electrically connected to gate electrodes that each include a control gate portion and a select gate portion. In one particular embodiment, such gate electrodes each include a control gate portion between two select gate portions.
  • FIG. 33 illustrates a physical embodiment of a portion of NVM array 14 corresponding to the row that includes memory cells 2811 and 2812.
  • FIG 33 is a cross- sectional illustration of the workpiece of FIG. 12 labeled with the same reference numbers those used in the circuit schematics in FIG. 33.
  • Charge storage regions for memory cells 2811 and 2812 are illustrated in FIGs. 32 and 33.
  • Memory cell 2811 includes charge storage regions 28111 to 28114, and memory cell 2812 includes charge storage region 28121 to 28124.
  • Memory cells 2821 and 2822 include similar charge storage regions, but such charge storage regions are not specifically identified in FIG. 32.
  • FIG. 34 includes a table that has some of the operating voltages for memory cells, as illustrated in FIG. 32.
  • "Pgm" means program.
  • References to charge storage regions 28111, 28112 28113, 28114, 28115, and 28116 refer to memory cell 2811 5 and more particularly to programming or reading discontinuous storage elements under gate electrodes of memory cell 2811. While many voltages are given in the table in FIG. 34 and other tables within this specification, other voltages may be used. The relative values and ratios between the voltages, rather than their absolute values are more relevant, as the absolute values of voltages change with changes in physical parameters.
  • All memory cells, as illustrated in FIG. 32 can be erased by creating a potential difference in a range of about 12 to 16 volts between substrate 12 (or well region therein) and the gate electrodes of the memory cells.
  • erasing can be performed by placing substrate 12 (or well region therein) to approximately +7 volts, placing the gate lines to -7 volts and allowing the bit lines to electrically float.
  • erasing can be performed by placing substrate 12 (or well region therein) to approximately -7 volts, placing the gate lines to +7 volts and allowing the bit lines to electrically float.
  • the voltages used for substrate 12 and the gate line do not need to be symmetric with respect to 0 volts. For example, a combination of +5 volts and -9 volts can be used.
  • FIG. 35 includes a circuit schematic for an embodiment as described with respect to the embodiment as illustrated in FIG. 36.
  • Memory cells 3111 , 3112, 3113 , 3114, 3121 , 3122, 3123, and 3124 are oriented within NVM array 14, as illustrated in FIG. 35.
  • BLl 3162 is electrically connected to a S/D region of memory cells 3111, 3112, 3113, and 3114.
  • BL2 3164 is electrically connected to a S/D region of memory cells 3121, 3122, 3123, and 3124.
  • BL3 3166 is electrically connected to the other S/D regions of memory cells 3111, 3112, 3121, and 3122.
  • BL4 3168 is electrically connected to the other S/D regions of memory cells 3113, 3114, 3123, and 3124.
  • GLl 3142 is electrically connected to select gate electrodes of memory cells 3111 and 3121.
  • GL2 3144 is electrically connected to control gate electrodes of memory cell 3111, 3112, 3121, and
  • GL3 3146 is electrically connected to select gate electrodes of memory cells 3112 and 3122.
  • GL43148 is electrically connected to select gate electrodes of memory cells 3113 and
  • GL5 3150 is electrically connected to control gate electrodes of memory cells 3113, 3114, 3123, and 3124.
  • GL6 3152 is electrically connected to select gate electrodes of memory cells 3114 and 3124.
  • Each of GLl 3142, GL3 3146, GL4 3148, and GL6 3152 are electrically connected to gate electrodes that each include a control gate portion and a select gate portion.
  • FIG. 36 illustrates a physical embodiment of a portion of NVM array 14 corresponding to the row that includes memory cells 3111, 3112, 3113, and 3114.
  • FIG 36 is substantially the same as FIG. 17 except that reference numbers as used in the circuit schematics are used in FIG. 36.
  • Memory cell 3111 includes charge storage regions 31111 to 31114
  • memory cell 3112 includes charge storage region 31121 to 31124
  • memory cell 3113 includes charge storage region 31131 to 31134
  • memory cell 3114 includes charge storage region 31141 to 31144.
  • Memory cells 3121 through 3124 include similar charge storage regions, but such charge storage regions are not specifically identified in FIG. 36.
  • FIG. 37 includes a table that has some of the operating voltages for memory cells, as illustrated in FIG. 35.
  • All memory cells, as illustrated in FIG. 35 can be erased by creating a potential difference in a range of about 12 to 16 volts between substrate 12 (or well region therein) and the gate electrodes of the memory cells.
  • erasing can be performed by placing substrate 12 (or well region therein) to approximately +7 volts, placing the gate lines to -7 volts and allowing the bit lines to electrically float.
  • erasing can be performed by placing substrate 12 (or well region therein) to approximately -7 volts, placing the gate lines to +7 volts and allowing the bit lines to electrically float.
  • the voltages used for substrate 12 and the gate line do not need to be symmetric with respect to 0 volts. For example, a combination of +5 volts and -9 volts can be used.
  • FIG. 38 includes a circuit schematic for an embodiment as described with respect to the embodiment as illustrated in FIG. 39.
  • Memory cells 3411, 3412, 3413, 3414, 3421, 3422, 3423, and 3424 are oriented within NVM array 14, as illustrated in FIG. 38.
  • BLl 3462 is electrically connected to a S/D region of memory cell 3411 and a S/D region of memory cell 3421.
  • BL2 3464 is electrically connected to the other S/D regions of memory cells 3411 and 3421 and to S/D regions of memory cell 3412 and 3422.
  • BL3 3466 is electrically connected to the other S/D regions of memory cell 3412 and 3422 and to S/D regions of memory cell 3413 and 3423.
  • BL4 3468 is electrically connected to the other S/D regions of memory cell 3413 and 3423 and to S/D regions of memory cell 3414 and 3424.
  • BL5 3469 is electrically connected to the other S/D regions of memory cell 3414 and 3424.
  • GLl 3442 is electrically connected to select gate electrodes of memory cell 3411, 3412, 3413, and 3414.
  • GL2 3444 is electrically connected to control gate electrodes of memory cell 3411, 3412, 3421 and 3422.
  • GL3 3446 is electrically connected to control gate electrodes of memory cell 3413, 3414, 3423 and 3424.
  • GL4 3448 is electrically connected to select gate electrodes of memory cell 3421, 3422, 3423, and 3424.
  • Each of GLl 3442 and GL4 3448 is electrically connected to gate electrodes that each include a control gate portion and a select gate portion.
  • FIG. 39 illustrates a physical embodiment of a portion of NVM array 14 corresponding to the row that includes memory cells 3411, 3412, 3413, and 3414.
  • FIG. 39 is substantially the same as an embodiment of FIG. 20 except that reference numbers as used in the circuit schematics are used in FIG. 39.
  • Memory cell 3411 includes charge storage regions 34111 to 34114
  • memory cell 3412 includes charge storage region 34121 to 34124
  • memory cell 3413 includes charge storage region 34131 to 34134
  • memory cell 3414 includes charge storage region 34141 to 34144. Note that charge storage regions 34111, 34124, 34131, and 34144 are not illustrated in FIG. 39, because those charge storage regions are offset from the plane as illustrated in the cross-sectional view of FIG. 39.
  • Memory cells 3421 through 3424 include similar charge storage regions, but such charge storage regions are not specifically identified in FIG. 38.
  • FIG. 40 includes a table that has some of the operating voltages for memory cells, as illustrated in FIG. 38.
  • All memory cells, as illustrated in FIG. 38 can be erased by creating a potential difference in a range of about 12 to 16 volts between substrate 12 (or well region therein) and the gate electrodes of the memory cells.
  • erasing can be performed by placing substrate 12 (or well region therein) to approximately +7 volts, placing the gate lines to -7 volts and allowing the bit lines to electrically float.
  • erasing can be performed by placing substrate 12 (or well region therein) to approximately -7 volts, placing the gate lines to +7 volts and allowing the bit lines to electrically float.
  • the voltages used for substrate 12 and the gate line do not need to be symmetric with respect to 0 volts. For example, a combination of +5 volts and -9 volts can be used.
  • FIGs. 22 through 25 can be represented by the circuit schematic as illustrated in FIG. 38 and can be operated using the voltages as listed in FIG. 40.
  • FIG. 41 includes a circuit schematic for an embodiment as described with respect to the embodiment as illustrated in FIG. 42.
  • Memory cells 3711, 3712, 3713, 3714, 3721, 3722, 3723, and 3724 are oriented within NVM array 14, as illustrated in FIG. 41.
  • BLl 3762 is electrically connected to a S/D region of memory cell 3711 and a S/D region of memory cell 3721.
  • BL2 3764 is electrically connected to the other S/D regions of memory cell 3711 and 3721 and to S/D regions of memory cells 3712 and 3722.
  • BL3 3766 is electrically connected to the other S/D regions of memory cells 3712 and 3722.
  • BL4 3768 is electrically connected to S/D regions of memory cells 3713 and 3723.
  • BL5 3770 is electrically connected to the other S/D regions of memory cells 3713 and 3723, and S/D regions of memory cells 3714 and 3724.
  • BL6 3772 is electrically connected to the other S/D regions of memory cells 3714 and 3724.
  • GLl 3742 is electrically connected to select gate electrodes of memory cell 3711, 3712, 3713, and 3714.
  • GL2 3744 is electrically connected to control gate electrodes of memory cell 3711, 3712, 3721, and 3722.
  • GL3 3746 is electrically connected to control gate electrodes of memory cell 3713, 3714, 3723, and 3724.
  • GL4 3748 is electrically connected to select gate electrodes of memory cell 3721, 3722, 3723, and 3724.
  • Each of GLl 3742 and GL4 3748 is electrically connected to gate electrodes that each include a control gate portion and a select gate portion.
  • FIG. 42 illustrates a physical embodiment of a portion of NVM array 14 corresponding to the row that includes memory cells 3711, 3712, 3713, and 3714.
  • FIG. 42 is substantially the same as FIG. 28 except that reference numbers as used in the circuit schematics are used in FIG. 42.
  • Memory cell 3711 includes charge storage regions 37111 to 37114
  • memory cell 3712 includes charge storage region 37121 to 37124
  • memory cell 3713 includes charge storage region 37131 to 37134
  • memory cell 3714 includes charge storage region 37141 to 37144. Note that charge storage regions 37111, 37124, 37131, and 37144 are not illustrated in FIG. 42, because those charge storage regions are offset from the plane as illustrated in the cross-sectional view of FIG. 42.
  • Memory cells 3721 through 3724 include similar charge storage regions, but such charge storage regions are not specifically identified in FIG. 41.
  • FIG. 43 includes a table that has some of the operating voltages for memory cells, as illustrated in FIG. 41.
  • All memory cells, as illustrated in FIG. 41 can be erased by creating a potential difference in a range of about 12 to 16 volts between substrate 12 (or well region therein) and the gate electrodes of the memory cells.
  • erasing can be performed by placing substrate 12 (or well region therein) to approximately +7 volts, placing the gate lines to -7 volts and allowing the bit lines to electrically float.
  • erasing can be performed by placing substrate 12 (or well region therein) to approximately -7 volts, placing the gate lines to +7 volts and allowing the bit lines to electrically float. Note that the voltages used for substrate 12 and the gate line do not need to be symmetric with respect to 0 volts.
  • NVM array 14 its memory cells, bit lines, and gate lines. After reading this specification, skilled artisans will appreciate that the row and column orientations can be reversed. Electrically connections between memory cells and their associated bit lines, gate lines, or any combination thereof along one or more rows can be changed to one or more columns. Similarly, electrically connections between memory cells and their associated bit lines, gate lines, or any combination thereof along one or more columns can be changed to one or more rows.
  • Embodiments as described herein are useful in forming NMV arrays or a portion thereof.
  • the use of discontinuous storage elements within a trench in the substrate allows smaller memory cells to be formed and increase memory density.
  • the discontinuous storage elements can also allow more bits to be stored within a memory cell as opposed to a conventional floating gate structure.
  • portions of the discontinuous storage elements lie between all of the gate electrodes and the substrate.
  • the portions of the discontinuous storage elements lie between all of the gate electrodes and the substrate at substantially all locations where gate electrodes overlie the substrate.
  • the portions of discontinuous storage elements can allow up to six bits of data to be stored per memory cell.
  • the fabrication of the NVM array can be implemented using existing materials and equipment. Therefore, process integration would not require developing new processes for new equipment or having to address materials incompatibility issues.
  • the memory cells can be formed such that select gate lines are formed, such that they are at least partly recessed within the trenches.
  • Source-side injection can be used to program some of the charge storage regions of memory cells.
  • the thickness of the intergate dielectric portions 114 and 115 and programming voltages can be selected to allow a relatively larger electrical field to be generated near the intergate dielectric portions 114 and 115 as compared to near the S/D regions that are electrically connected to the bit lines.
  • the source-side injection allows programming times similar to conventional hot-electron injection and has a higher electron efficiency compared to conventional hot-electron injection.
  • an electronic device can include a substrate including a first trench that includes a wall and a bottom and extends from a primary surface of the substrate.
  • the electronic device can also include a first set of discontinuous storage elements, wherein the first set of discontinuous storage elements overlies the primary surface of the substrate.
  • the electronic device can further include a second set of the discontinuous storage elements including a first portion. The first portion of the second set of discontinuous storage elements can lie within the first trench, and the first portion of the second set of discontinuous storage elements is spaced apart from the first set of discontinuous storage elements.
  • the electronic can still further include a first gate electrode within the first trench, wherein at least a part of the first portion of the second set of discontinuous storage elements lies between the first gate electrode and the wall of the first trench.
  • the electronic device can also include a second gate electrode overlying the first gate electrode and the primary surface of the substrate.
  • the first gate electrode has an upper surface that lies below the primary surface of the substrate.
  • the second gate electrode extends at least partly within the first trench.
  • the electronic device further includes a third gate electrode within a second trench.
  • the substrate further includes the second trench that is spaced apart from the first trench, wherein the second trench includes a wall and a bottom and extends from the primary surface of the substrate.
  • the second set of the discontinuous storage elements includes a second portion that lies within the second trench.
  • the third gate electrode has an upper surface that lies below the primary surface of the substrate, wherein the second portion of the second set of discontinuous storage elements lies between the third gate electrode and the wall of the second trench.
  • the electronic device further includes a first doped region lying within the substrate below the first trench, and a second doped region lying within the substrate below the second trench.
  • the electronic device further includes a third doped region lying along the primary surface of the substrate between the first and second trenches.
  • the third doped region extends to the walls of the first and second trenches.
  • the third doped region is spaced apart from the walls of the first and second trenches.
  • a first charge storage region includes a first discontinuous storage element within the first portion of the second set of discontinuous storage elements, wherein the first discontinuous storage element lies closer to the upper surface of the first gate electrode than the first doped region.
  • a second charge storage region includes a second discontinuous storage element within the first portion of the second set of discontinuous storage elements, wherein the second discontinuous storage element lies closer to the first doped region than the upper surface of the first gate electrode, and wherein the second charge storage region is spaced apart from the first charge storage region.
  • a third charge storage region includes a third discontinuous storage element within the second portion of the second set of discontinuous storage elements, wherein the third discontinuous storage element lies closer to the upper surface of the third gate electrode than the second doped region.
  • a fourth charge storage region includes a fourth discontinuous storage element within the second portion of the second set of discontinuous storage elements, wherein the fourth discontinuous storage element lies closer to the second doped region than the upper surface of the third gate electrode, and wherein the fourth charge storage region is spaced apart from the third charge storage region.
  • the second gate electrode overlies the first gate electrode, the third gate electrode, and a portion of the substrate between the first and second trenches.
  • the electronic device further includes a fourth gate electrode spaced apart from the third gate electrode. The second gate electrode overlies the first gate electrode and a first portion of the substrate between the first and second trenches, and the fourth gate electrode overlies the third gate electrode and a second portion of the substrate between the first and second trenches.
  • the electronic device further includes a first dielectric layer lying along the wall and bottom of the first trench, and a second dielectric layer lying between the first portion of the second set of the discontinuous storage elements and the first gate electrode.
  • each of first and second sets of discontinuous storage elements includes silicon nanocrystals or metal nanoclusters.
  • the first gate electrode includes portions, and the portions of the first gate electrode include curved outer surfaces that face each other.
  • an electronic device can include a substrate including a first trench and a second trench that are spaced apart from each other, wherein each of the first and second trenches includes a wall and a bottom and extends from a primary surface of the substrate.
  • the electronic device can also include a first doped region lying within the substrate along the bottom of the first trench, and a second doped region lying within the substrate along the bottom of the second trench.
  • the electronic device can further include a first dielectric layer lying along the walls and bottoms of the first and second trenches, and discontinuous storage elements. A first set of the discontinuous storage elements can overlie the primary surface between the first and second trenches and a second set of the discontinuous storage elements.
  • a first portion of the second set of the discontinuous storage elements can lie within the first trench, and a second portion of the second set of the discontinuous storage elements can lie within the second trench.
  • Each of the first and second portions of the second set of the discontinuous storage elements can be spaced apart from the primary surface of the substrate and the first set of discontinuous storage elements.
  • the electronic device can still further include a second dielectric layer adjacent to the first and second portions of the discontinuous storage elements, and a first gate electrode lying within the first trench and having an upper surface that lies below the primary surface of the substrate, wherein at least a part of the first portion of the second set of discontinuous storage elements lies between the first gate electrode and the wall of the first trench.
  • the electronic device can yet further include a second gate electrode lying within the second trench and having an upper surface that lies below the primary surface of the substrate, wherein at least a part of the second portion of second set of discontinuous storage elements lies between the second gate electrode and the wall of the second trench.
  • the electronic device can also include a third dielectric layer including a first portio overlying the first gate electrode within the first trench and a second portion overlying the second gate electrode within the second trench.
  • the electronic device can further include a third gate electrode overlying (1) at least one of the first portion or the second portion of third dielectric layer, and (2) at least one of the first portion or the second portion of the second set of the discontinuous storage elements.
  • an electronic device can include a first set of memory cells oriented substantially along a first direction, wherein each memory cell within the first set of memory cells includes a first gate electrode that includes a control gate portion and a select gate portion.
  • the electronic device can also include a second set of memory cells oriented substantially along the first direction, wherein each memory cell within the second set of memory cells includes a first gate electrode that includes a control gate portion and a select gate portion.
  • the electronic device can further include a first conductive line electrically connected to the first set of memory cells, wherein the first conductive line is of a type including a gate line or a bit line, and a second conductive line electrically connected to the second set of memory cells.
  • the second conductive line can be of a same type as the first conductive line, and when compared to the first conductive line, the second conductive line can be electrically connected to more sets of memory cells that lie along the first direction.
  • each memory cell within the first and second sets of memory cells includes a nonvolatile memory cell that includes the first gate electrode and a second gate electrode.
  • the first gate electrode includes a control gate portion and a select gate portion
  • the second gate electrode is a control gate electrode
  • the select gate portion of the first gate electrode lies between the second gate electrode and the control gate portion of the first electrode.
  • a discontinuous storage element lies between a channel region and the control gate portion of first gate electrode
  • another discontinuous storage element lies between the channel region and the second gate electrode
  • substantially none of the discontinuous storage elements lies between the channel region and the select gate portion of first gate electrode.
  • the electronic device further includes a third set of memory cells oriented substantially along the first direction, wherein the first, second, and third sets of memory cells lie within different rows or different columns as compared to one another.
  • Each memory cell within the third set of memory cells includes a nonvolatile memory cell that includes the first gate electrode and a second gate electrode.
  • the first gate electrode includes a control gate portion and a select gate portion
  • the second gate electrode is a control gate electrode
  • the select gate portion of the first gate electrode lies between the second gate electrode and the control gate portion of the first electrode.
  • the first conductive line is a first gate line that is electrically connected to the first gate electrodes of the first set of memory cells
  • the second conductive line is a second gate line that is electrically connected to the second gate electrodes of the second and third sets of memory cells.
  • the electronic device further includes a third set of memory cells oriented substantially along the first direction, wherein the first, second, and third sets of memory cells lie within different rows or different columns as compared to one another.
  • the first conductive line is a first bit line
  • the second conductive line is a second bit line electrically connected to the second and third sets of memory cells.
  • the first direction is associated with a row or a column.
  • a process for forming an electronic device can include forming a first set of discontinuous storage elements over a primary surface of a substrate.
  • the process can also include forming a first trench within the substrate, wherein the first trench includes a wall and a bottom and extends from the primary surface of the substrate and forming a second set of discontinuous storage elements, wherein a first portion of the second set of discontinuous storage elements lie within the first trench.
  • the process can further include forming a first gate electrode within the first trench after forming the second set of discontinuous storage elements, wherein the first gate electrode has an upper surface that lies below the primary surface of the substrate, and at least a part of the first portion of the second set of discontinuous storage elements lies between the first gate electrode and the wall of the first trench.
  • the process can still further include removing a part of the first portion of the second set of discontinuous storage elements that overlies the primary surface of the substrate.
  • the process can yet further include forming a second gate electrode that overlies the first gate electrode and the primary surface of the substrate, wherein after forming the second gate electrode, substantially none of the first portion of the second set of discontinuous storage elements lies along the wall of the first trench at an elevation between an upper surface of the first gate electrode and the primary surface of the substrate.
  • forming the second gate electrode includes forming the second gate electrode, such that at least a portion of the second gate electrode extends at least partly into the first trench.
  • the process further includes forming a third gate electrode within the second trench.
  • Forming the first trench further includes forming a second trench that is spaced apart from the first trench, wherein the second trench includes a wall and a bottom and extends from a primary surface of the substrate.
  • Forming the second set of discontinuous storage elements further includes forming a second portion of the second set of discontinuous storage elements within the second trench.
  • Forming the third gate electrode includes forming the third gate electrode, such that the third gate electrode has an upper surface that lies below the primary surface of the substrate, and at least a part of the second portion of the second set of discontinuous storage elements lies between the third gate electrode and the wall of the second trench. After forming the second gate electrode, substantially none of the second portion of the second set of discontinuous storage elements lies along the wall of the second trench at an elevation between an upper surface of the third gate electrode and the primary surface of the substrate.
  • the process further includes forming a first doped region and a second doped region along the bottoms of the first and second trenches, respectively. In a more particular embodiment, the process further includes forming a third doped region lying along the primary surface of the substrate between the first and second trenches. In a still more particular embodiment, forming the third doped region is performed before forming the second gate electrode. In another still more particular embodiment, forming the third doped region is performed after forming the second gate electrode.
  • a first charge storage region includes the first discontinuous storage element, wherein the first discontinuous storage element lies closer to the upper surface of the first gate electrode than the first doped region.
  • a second charge storage region includes a second discontinuous storage element within the first portion of the discontinuous storage elements, wherein the second discontinuous storage element lies closer to the first doped region than the upper surface of the first gate electrode, and wherein the second charge storage region is spaced apart from the first charge storage region.
  • a third charge storage region includes a third discontinuous storage element, wherein the third discontinuous storage element lies closer to the upper surface of the third gate electrode than the second doped region.
  • a fourth charge storage region includes a fourth discontinuous storage element within the second portion of the discontinuous storage elements, wherein the fourth discontinuous storage element lies closer to the second doped region than the upper surface of the third gate electrode, and wherein the fourth charge storage region is spaced apart from the third charge storage region.
  • forming the second gate electrode includes forming the second gate electrode such that the second gate electrode overlies the first and third gate electrodes, and from a top view, lengths of the first and second trenches are substantially perpendicular to a length of the second gate electrode.
  • the process further includes forming a fourth gate electrode.
  • Forming the second gate electrode includes forming the second gate electrode, such that the second gate electrode that overlies the first gate electrode, and forming the fourth gate electrode includes forming the fourth gate electrode, such that the fourth gate electrode that overlies the third gate electrode. From a top view, a length of the first trench is substantially parallel to a length of the second gate electrode, and a length of the second trench is substantially parallel to a length of the fourth gate electrode.
  • the process further includes forming a first dielectric layer lying along the wall and bottom of the first trench, forming a second dielectric layer after forming the second set of discontinuous storage elements, and forming a third dielectric layer after forming the first gate electrode.
  • forming the third dielectric layer and removing the part of the first portion of the second set of discontinuous storage elements include oxidizing an exposed portion of the first gate electrode, and a part of the first portion of the second set of discontinuous storage elements that do not lie between the first gate electrode and the wall of the first trench.
  • forming the first gate electrode includes forming a conductive layer after forming the second set of discontinuous storage elements, polishing the conductive layer to a remove portion of the conductive layer that overlies the primary surface of the substrate, and recessing the conductive layer within the first trench to form the first gate electrode, such that the upper surface of the first gate electrode lies below the primary surface.
  • forming the first gate electrode includes forming a conductive layer after forming the second set of discontinuous storage elements, and anisotropically etching the conductive layer to form the first gate electrode, which from a cross-sectional view, has a sidewall spacer shape.
  • forming the first set of discontinuous storage elements or forming the first set of discontinuous storage elements includes forming silicon nanocrystals or forming metal nanoclusters.
  • the process further includes removing a part of the first set of discontinuous storage elements that overlie a region of the substrate where the first trench is to be formed.
  • a process for forming an electronic device can include forming a first set of discontinuous storage elements over a primary surface of a substrate and removing parts of the first set of discontinuous storage elements that overlie regions of the substrate where a first trench and a second trench are to be formed.
  • the process also can include forming the first and second trenches within the substrate, wherein the first trench is spaced apart from the second trench, and each of the first and second trenches includes a wall and a bottom and extends from a primary surface of the substrate.
  • the process can further include forming a second set of discontinuous storage elements, wherein a first portion of the second set of discontinuous storage elements lie within the first trench, and a second portion of the second set of discontinuous storage elements lie within the second trench.
  • the process can still further include forming a first conductive layer after forming the first and second sets of discontinuous storage elements, and removing a portion of the first conductive layer that overlies the primary surface of the substrate to form a first gate electrode within the first trench and a second gate electrode within the second trench.
  • the first gate electrode has an upper surface that lies below the primary surface of the substrate, a first discontinuous storage element within the first portion of the discontinuous storage elements lies between the first gate electrode and the wall of the first trench, the second gate electrode has an upper surface that lies below the primary surface of the substrate, and a second discontinuous storage element within the second portion of the discontinuous storage elements lies between the second gate electrode and the wall of the first trench.
  • the process can yet further include removing parts of the second set of discontinuous storage elements that overlie the primary surface of the substrate, lie along the wall of the first trench at an elevation between the upper surface of the first gate electrode and the primary surface of the substrate, and lie along the wall of the second trench at an elevation between the upper surface of the second gate electrode and the primary surface of the substrate.
  • the process can also include forming a first dielectric layer over the first gate electrode, wherein the first dielectric layer has an upper surface within the first trench and a second portion with an upper surface within the second trench, and forming a second dielectric layer over the second gate electrode, wherein the second dielectric layer has a first portion with an upper surface within the second trench.
  • the process can further include forming a second conductive layer after forming the first and second dielectric layers, and patterning the second conductive layer to form a third gate electrode that overlies the first gate electrode and the primary surface of the substrate.
  • substantially none of the first portion of the second set of discontinuous storage elements lies along the wall of the first trench at an elevation between an upper surface of the first gate electrode and the primary surface of the substrate, and substantially none of the second portion of the second set of discontinuous storage elements lies along the wall of the second trench at an elevation between an upper surface of the second gate electrode and the primary surface of the substrate.
  • the process further includes forming a first doped region and a second doped region along the bottoms of the first and second trenches, respectively, and forming a third doped region along the primary surface of the substrate between the first and second trenches.
  • a first charge storage region includes the first discontinuous storage element, wherein the first discontinuous storage element lies closer to the upper surface of the first gate electrode than the first doped region.
  • a second charge storage region includes a third discontinuous storage element within the first portion of the discontinuous storage elements, wherein the third discontinuous storage element lies closer to the first doped region than the upper surface of the first gate electrode, and wherein the second charge storage region is spaced apart from the first charge storage region.
  • a third charge storage region includes the second discontinuous storage element, wherein the second discontinuous storage element lies closer to the upper surface of the third gate electrode than the second doped region.
  • a fourth charge storage region includes a fourth discontinuous storage element within the second portion of the discontinuous storage elements, wherein the fourth discontinuous storage element lies closer to the second doped region than the upper surface of the third gate electrode, and wherein the fourth charge storage region is spaced apart from the third charge storage region.
  • forming the first set of discontinuous storage elements or forming the first set of discontinuous storage elements includes forming silicon nanocrystals or forming metal nanoclusters.

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Abstract

La présente invention a trait à un dispositif électronique comportant un substrat comprenant une tranchée (22, 23) incluant une paroi et un fond. Le dispositif électronique peut également comporter un premier ensemble d'éléments de stockage discontinus (110) sus-jacents à une face principale du substrat et un deuxième ensemble d'éléments de stockage discontinus (64) logés dans la tranchée. Le dispositif électronique peut également comporter une première électrode de grille (92), dans laquelle sensiblement aucun des éléments discontinus n'est logé le long de la paroi de la tranchée à une élévation entre une surface supérieure de la première électrode de grille et la face principale du substrat. Le dispositif électronique peut également comporter une deuxième électrode de grille sus-jacente à la première électrode de grille et à la face principale. Dans un autre mode de réalisation, une ligne conductrice peut être en liaison électrique avec une ou des rangées ou colonnes de cellules de mémoire, et une autre ligne conductrice peut constituer plusieurs rangées ou plusieurs colonnes des cellules de mémoire.
PCT/US2006/028575 2005-07-25 2006-07-24 Dispositif electronique comportant des elements de stockage discontinus Ceased WO2007014115A1 (fr)

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US20050148173A1 (en) * 2004-01-05 2005-07-07 Fuja Shone Non-volatile memory array having vertical transistors and manufacturing method thereof

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