WO2007008173A1

WO2007008173A1 - Semiconductor structure for transistors with enhanced subthreshold swing and methods of manufacture thereof

Info

Publication number: WO2007008173A1
Application number: PCT/SG2006/000093
Authority: WO
Inventors: Eng Huat Toh; Yee Chia Yeo; S. Samudra Ganesh
Original assignee: National University Of Singapore
Priority date: 2005-07-07
Filing date: 2006-04-11
Publication date: 2007-01-18
Also published as: TW200707730A

Abstract

The semiconductor device (100) comprises a substrate structure (104); a gate stack (102) formed on said substrate structure (104); a drain region (122) of a first dopant type formed in the substrate structure (104) adjacent said gate stack (102); a source structure (126) formed on said substrate structure (104) adjacent said gate stack (102), the source structure (126) comprising a source region (132) of a second dopant type and a first region of a dopant concentration below 1018 cm-3 disposed between the source region (132) and the substrate structure (104). The impact ionization metal-oxide semiconductor (IMOS) device has application as an inverter or integration into integrated circuit chips.

Description

Semiconductor Structure For Transistors With Enhanced Subthreshold Swing and Methods of Manufacture Thereof

FIELD OFThE INVENTION

The present invention relates to the field of semiconductor devices and circuits, and more particularly, to semiconductor devices, inverters, integrated ciruit chips, and methods of manufacturing such devices, and the use of such devices in integrated circuits.

BACKGROUND

Miniaturization or scaling of the Complementary Metal Oxide Semiconductor (CMOS) transistor to improve its speed performance results in rapid increase in the power consumption of CMOS transistors and integrated circuits employing these transistors.

Reducing the supply voltage V_DD helps to contain or reduce the power consumption, but if the transistor threshold voltage V₇- is not correspondingly reduced, the gate overdrive V_G - V₇-, where V₆ is the maximum gate voltage and is equal to Vbo. becomes smaller. A smaller gate overdrive leads to reduced speed performance.

To maintain the speed performance of transistors, V₇ reduction usually accompanies transistor scaling and supply voltage reduction. However, the reduction of V₇- results in an increase in the transistor off-state leakage current, which leads to an increase in power consumption.

Currently, further reduction of V_τ together with device scaling is limited by the non- scalability of the subthreshold swing S. The subthreshold swing S for a. conventional CMOS field-effect transistor (FET) is above 60 mV per decade at room temperature, and this is related to the Ferrhi-Dirac distribution of the carrier energy.

It is known in the art that a planar impact ionization metal-oxide-semjconductor (I- MOS) structure that modulates the breakdown voltage and the current of a gated p-i-n structure can realize a subthreshold swing S of less than 60 mV/dscade at room temperature. However, it has been found that the planar I-MOS structure suffers from 006/000093

serious hot carrier degradation. This has adverse effects on the reliability of the device.

Besides hot carrier degradation, the planar I-MOS device structure also suffers from a number of other deficiencies.

Firstly, the planar I-MOS structure requires a laterally-positioned impact ionization region (l-region) for carrier multiplication effect, and the l-region occupies an additional area. The use of additional silicon area leads to a trade-off in layout efficiency and renders the device design unattractive.

Secondly, the prior art planar I-MOS structure employs lithography techniques to define the l-region. A misalignment error in lithography directly translates to an error in the length of the l-region, which affects the electrical performance of the device. Lithographic errors could therefore affect the operational uniformity of I-MOS transistors in a integrated chip.

Thirdly, the operating current and voltage requirements of such a device are too high for normal conventional CMOS operation. This is due to the high breakdown voltage needed for impact ionization.

The present invention thus seeks to address the above deficiencies through novel impaction ionization metal-oxide-semiconductor (I-MOS) device structure designs and methods of manufacture.

SUMMARY OF THE INVENTION

According to a first aspect of the invention, there is provided a semiconductor structure comprising a substrate structure; a gate stack formed on said substrate structure^ drain region of a first dopant type formed in the substrate structure adjacent said gate stack; a source structure formed on said substrate structure adjacent said gate stack, the source structure comprising a source region of a second dopant type and a first region of a dopant concentration below it)¹⁸ crrf³ disposed between the source region and the substrate structure. 6 000093

The substrate structure may be a bulk semiconductor or a semiconductor-on-insulator substrate.

The bulk semiconductor may comprise elemental or compound semiconductors selected from a group comprising silicon, germanium, carbon, gallium arsenide, indium phosphide, and indium antimonide.

The semiconductor-on-insulator substrate may comprise at least one semiconductor layer formed on an insulator layer, said semiconductor layer comprising any one or more of a group consisting of silicon, germanium, carbon, or compound semiconductors.

The semiconductor-on-insulator may comprise a plurality of semiconductor layers.

The semiconductor layers may comprise a silicon-germanium layer formed on a silicon layer and said silicon layer formed on a silicon oxide layer.

The gate stack may comprise a gate electrode formed on a gate dielectric layer.

The gate electrode may comprise any one or more of a group consisting of polycrystalline silicon, an elemental metal, a metal alloy, a metal nitride, a metal suicide or a metal oxide.

The gate dielectric layer may comprise any one or more of a group consisting of silicon dioxide, nitraded silicon dioxide (SiON), hafnium oxide (HfO₂), hafnium oxynitride (HfON), hafnium silicate (HfSiO₄), hafnium silicon oxynitride (HfSiON), lanthanum oxide (La₂O₃) or any dielectric with a permittivity (k) value larger than 6.

The source structure may comprise elemental, compound semiconductors, IH-V semiconductors, binary compound semiconductors, ternary compound semiconductors or alloy semiconductors selected from a group comprising silicon, germanium, gallium arsenide, indium arsenide, indium antimonide, indium phosphide, gallium indium arsenide, gallium indium antimonide, silicon-germanium, silcon-germanium-carbon, silicon-carbon, and germanium-carbon. The first region may comprise elemental, compound semiconductors, IH-V semiconductors, binary compound semiconductors, ternary compound semiconductors or alloy semiconductors selected from a group comprising silicon, germanium, gallium arsenide, indium arsenide, indium antimonide, indium phosphide, gallium indium arsenide, gallium indium antimonide, silicon-germanium, silcon-germanium-carbon, silicon-carbon, and germanium-carbon.

The semiconductor structure may further comprise spacers oppositely adjacent said gate electrode.

The first dopant type may be n-type dopant and the second dopant type may be p-type dopant.

The first dopant type may be p-type and the second dopant type may be n-type dopant.

The source region may be formed by a combined deposition and in-situ doping.

The semiconductor structure may further comprise a second region of said first dopant type formed on said drain region.

The semiconductor structure may further comprise a conductive metal suicide material formed on said source region and said drain region.

The first region may be doped with a second dopant type.

The first region may have a thickness in the range of approximately 1 nm to approximately 100 nm.

The substrate structure may comprise a recessed portion, with respect to a surface of the drain region, at an interface between the first region and the substrate structure.

The substrate structure may comprise silicon and said first region may comprise silicon, germanium, or both. According to a second aspect of the invention, there is provided a method of forming a semiconductor structure comprising the steps of providing a substrate structure; forming a gate stack on the substrate structure; forming a drain region of a first dopant type in said substrate structure adjacent said gate stack; forming a source structure on said substrate structure adjacent said gate stack, the source structure comprising a source region of a second dopant type and a first region of a dopant concentration below 10¹⁸cm^"3 disposed between the source region and the substrate structure.

The method may further comprise the step of forming spacers adjacent said gate stack.

The step of forming said gate stack may further comprise the steps of forming a gate dielectric layer; and forming a gate electrode.

A hardmask may be formed on the gate electrode, the hardmask comprising a dielectric material.

The step of forming said source structure may comprise a selective epitaxy step.

The selective epitaxy step may further comprise in-situ doping.

The selective epitaxy step may comprise utilising any one or more of a group consisting of silane, disilane, methyl-silane, germane, and chlorine.

The method may further comprise the step of etching said substrate structure prior to forming said source structure.

The substrate structure arid the source structure may comprise any one or more of a group consisting of silicon, germanium, Garbon of compound semiconductors.

The method may further comprise the steps of forming a conductive material over said source region and said drain region; depositing an insulating layer above said conductive material; and forming contacts to said source region, said drain region, and said gate stack. The steps of forming said drain region and said source structure may comprise an ion implantation step.

The first dopant type may be n-type and said second dopant type may be p-type.

The first dopant type may be p-typ^~e and said second dopant type may be n-type.

According to a third aspect of the invention, there is provided an inverter comprising a first transistor comprising a gate electrode; a drain region of a first dopant type; and a source region of a first dopant type, said first transistor source region connected to a first power supply and said first transistor drain region connected to an output terminal; a second transistor comprising a substrate structure; a gate stack formed on said second transistor substrate structure; said second transistor gate stack further comprising a gate electrode; a drain region of a second dopant type formed in said second transistor substrate structure adjacent sajd second transistor gate stack; and a source structure formed on said second transistor substrate structure adjacent said second transistor gate stack, said second transistor source structure comprising a source region of a first dopant type and a first region of a dopant concentration below 10¹⁸ cm^"3 disposed between said second transistor source region and said second transistor substrate structure, said second transistor source region connected to a second power supply and said second transistor drain region connected to said output terminal; and an input terminal connected to the gate electrodes of said first and second transistors.

The first dopant type may be p-type dopant, and said second dopant type may be n- type dopant.

The first dopant type may be n-type dopant, and said second dopant type may be p- type dopant.

According to a fourth aspect of the invention, there is provided an inverter comprising a first transistor comprising a substrate structure; a gate stack formed on said first transistor substrate structure; said first transistor gate stack further comprising a gate electrode; a drain region of a first dopant type formed in said first transistor substrate structure adjacent said first transistor gate stack; and a source structure formed on said first transistor substrate structure adjacent said first transistor gate stack, said first transistor source structure comprising a source region of a second dopant type and a first region of a dopant concentration below 10¹⁸ cm^"3 disposed between said first transistor source region and said first transistor substrate structure, said first transistor source region connected to a first power supply and said first transistor drain region connected to an output terminal; a second transistor comprising a substrate structure; a gate stack formed on said second transistor substrate structure; said second transistor gate stack further comprising a gate electrode; a drain region of a second dopant type formed in said second transistor substrate structure adjacent said second transistor gate stack; and a source structure formed on said second transistor substrate structure adjacent said second transistor gate stack, said second transistor source structure comprising a source region of a first dopant type and a first region of a dopant concentration below 10¹⁸cm^"3 disposed between said second transistor source region and said second transistor substrate structure, said second transistor source region connected to a second power supply and said second transistor drain region connected to said output terminal; and an input terminal connected to the gate electrodes of said first and second transistors.

According to a fifth aspect of the invention, there is provided an integrated circuit chip comprising a plurality of first transistors, each first transistor comprising a first gate electrode; a first drain of a first dopant type, and a first source of a first dopant type; and a plurality of second transistors, each second transistor comprising a substrate structure; a gate stack formed on said second transistor substrate structure; said second transistor gate stack further comprising a gate electrode; a drain region of a second dopant type formed in said second transistor substrate structure adjacent said second transistor gate stack; and a source structure formed on said second transistor substrate structure adjacent said second transistor gate stack, said second transistor source structure comprising a source region of a first dopant type and a first region of a dopant concentration below 10¹⁸ cnrf³ disposed between said second transistor source region and said second transistor substrate structure.

According to a sixth aspect of the invention, there is provided an integrated circuit chip comprising a plurality of first transistors, each first transistor comprising a substrate structure; a gate stack formed on said first transistor substrate structure; said first transistor gate stack further comprising a gate electrode; a drain region of a second dopant type formed in said first transistor substrate structure adjacent said first transistor gate stack; and a source structure formed on said first transistor substrate structure adjacent said first transistor gate stack, said first transistor source structure comprising a source region of a first dopant type and a first region of a dopant concentration below 10¹⁸crτf³ disposed between said first transistor source region and said first transistor substrate structure; and a plurality of second transistors, each second transistor comprising a substrate structure; a gate stack formed on said second transistor substrate structure; said second transistor gate stack further comprising a gate electrode; a drain region of a first dopant type formed in said second transistor substrate structure adjacent said second transistor gate stack; and a source structure formed on said second transistor substrate structure adjacent said second transistor gate stack, said second transistor source structure comprising a source region of a second dopant type and a first region of a dopant concentration below 10¹⁸ cm^'3 disposed between said second transistor source region and said second transistor substrate structure.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention is now described by way of non-limiting examples, with reference to the accompanying drawings, in which: Figure 1 shows a cross sectional view of an L-shaped Impact Ionization Metal-Oxide- Semiconductor (LI-MOS) transistor device built in accordance with one embodiment of the present invention.

Figure 2 shows a schematic of band-to-band carrier generation rate contour plots occurring at the impact ionization region of an n-channel device of Figure 1 at source voltage V_s= -5.25 V and a gate voltage V_G ?= 1 V.

Figure 3 shows a schematic .of holes concentration contour plots generated by impact ionization from hot electrons occurring at the impact ionization region of an n-channel device of Figure 1 at source voltage V₅= -5.25 V and a gate voltage V₆= 1 V.

Figure 4 shows a plot of the simulated drain current I₀ (A/μm) against gate voltage V_G (V). The source voltage V_s of Si LI-MOS and Ge LI-MOS is at -5.25 V and -1.8 V, respectively.

Figure 5 shows a plot of the simulated gate current 1_G (A/μm) against gate voltage V_G (V). the source voltage V_s of Si LI-MOS and Ge LI-MOS is at -5.25 V and -1.8 V, respectively.

Figures 6 to 11 illustrate fabrication of embodiments of L|-MOS transistor devices built in accordance with the present invention.

Figure 12 shows a cross sectional view of an L-shaped Impact Ionization Metal-Oxide- Semiconductor (LI-MOS) transistor device built in accordance with one embodiment of the present invention.

Figures 13 to 14 illustrate fabrication of embodiments of Ll-MOS transistor devices built in accordance with the present invention.

Figure 15 shows a cross sectional view of an L-shaped Impact Ionization Metal-Oxide- Semiconductor (LI-MOS) transistor device built in accordance With one embodiment of the present invention. Figure 16 shows a cross sectional view of an L-shaped Impact Ionization Metal-Oxide- Semiconduetor (U-MOS) transistor device built in accordance with one embodiment of the present invention.

Figure 17 shows a cross sectional view of an L-shaped Impact Ionization Metal-Oxide- Semiconductor transistor device 15 built in accordance with one embodiment of the present invention.

Figure 18 shows the electrical circuit symbols for a LI-MOS device built in accordance with an embodiment of the present invention.

Figures 19A to 19C shows basic electrical circuits comprising a LI-MOS device built in accordance with an embodiment of the present invention.

Figures 2OA and 2OB show inverter circuits comprising a MOS device and a LI-MOS device built in accordance with an embodiment of the present invention.

Figure 21 A to 21 C shows NAND logic gate circuits comprising a MOS device and a Ll- MOS device built in accordance with an embodiment of the present invention.

DETAILED DESCRIPTION

The embodiments described provide semiconductor devices and circuits, and more particularly, semiconductor devices with improved subthreshold swing, methods of manufacturing such devices, and the use of such devices in integrated circuits.

Figure 1 shows a cro^'όs sectional view of an. L-shaped Impact Ionization Metal-Oxide- SemiGonductor (LI-MOS) transistor device 10O fabricated in accordance with one embodiment of the present invention, which can provide a semiconductor device with improved subthreshold swing. In the embodiment depicted in Fig. 1 , a semiconductor on insulator structure is shown.

The device 100 comprises a gate stack 102 formed on a substrate structure 104. The substrate structure 104 comprises a first semiconductor layer 106 formed above an insulation layer 108 on a wafer substrate 110. The first semiconductor layer 106 and the second semiconductor layer 126 may have a crystalline or amorphous structure and may comprise of an elemental semiconductor or compound semiconductor. Elemental semiconductors include silicon, and germanium. Compound semiconductors or Hl-V semiconductors include binary compound semiconductors such as gallium arsenide, indium arsenide, indium antimonide, indium phosphide, and ternary compound semiconductors such as gallium Indium arsenide and gallium indium antimonide. In addition, the first semiconductor layer and the second semiconductor layer each may comprise alloy semiconductors, such as silicon-germanium (SiGe), silcon-germanium-carbon (SiGeC), silicon-carbon (SiC), and germanium-carbon (GeC).

The gate stack 102 comprises a gate insulator or gate dielectric layer 112 formed on the first semiconductor layer 106, and a gate or gate electrode 114 formed above the gate dielectric layer 112. Spacers 116a and 116b are formed on opposite sides of the gate electrode 114. A second semiconductor layer 126 is formed above the substrate Structure 104 adjacent to the spacer 116a.

A source structure comprising a heavy doped source region 132 is formed within the second semiconductor layer 126, the second semiconductor layer 126 itself having a dopant concentration below 10¹⁸cm^"3. The heavy doped source region 132 is disposed nearer to the surface of the second layer 126. For an n^channel device 100, the source region 132 will be p+ doped, while for a p-channel device 100, the source region 132 will be n+ doped. A drain region 122 will also be formed within the first semiconductor layer 106 extending, below the spacer 116b so that the drain region 122 is formed within the substrate structure 104. For an n-channel device 100, the drain region 122 will be n+ doped, while for a p-channe| device 100, the drain region 122 will be p+ doped.

A conducting channel (not shown), spanning from the source region 132 to the drain region 122 will be formed when the device 100. is suitably biased.

When the device 100 is operated,^' an L-shaped impact ionization region 136 extends vertically below the source region 132, and horizontally below the spacer 116a. Jn contrast, prior art planar I-MOS structures have the impact ionization region occurring in the region 113 directly beneath the gate dielectric layer 112 as well as the intrinsic semiconductor region 106, Thus for the device 100, the impact ionization region 136 has been significantly shifted away from most of the region 113. While there is still carrier activity in the region 113, the carrier activity is not of the hot carrier activity type due to the low electric field in the region 113. The formation of the L-shaped impact ionization region 136 in the present embodiment arises due to the strong electric field present in the impact ionization region 136.

The L-shaped impact ionization region 136 thus reduces the damaging effects impact ionization has on the gate dielectric layer 112 and further greatly reduces hot carrier degradation effects that are more present in current i-MOS structures. The impact ionization region 136 can also be scaled vertically instead of horizontally thus allowing a compact design without sacrificing silicon (substrate) area. Vertical scaling of the impact ionization region will be detailed (ater with respect to Figures 7 to 12.

In the example embodiment, the first semiconductor layer 106 and the second semiconductor layer 126 comprises silicon. The wafer substrate 110 comprises bulk silicon, while the insulation layer 108 comprises silicon dioxide. The gate electrode 114 comprises polysilicon. The gate dielectric layer 112 comprises silicon dioxide. The spacers 116a and 116b comprises silicon nitride (SiN).

In other embodiments, the gate electrode 114 comprises any other conductive gate materials like elemental metals (e.g. Ta, Ti, Hf, Ru, Mo, W, Pt, Ni, etc.), metal alloys (e.g. TaPt, TaHf, NiHf, etc.), metal nitrides like TiN, HfN, WN, MoN, and TaN, metal suicides (e.g. NiSi, CoSi, RSi, HfSi, etc.), metal oxides {e.g. RuO₂, IrO₂, etc.), or combinations thereof. The first semiconductor layer 106 and the second semiconductor layer 126 comprise silicon germanium, silicon or germanium, carbon or compound semiconductors. The gate dielectric layer 112 comprises any dielectric insulator such as hafnium oxide (HfO₂), hafnium oxynitride (HfON), hafnium silicate (HfSiO₄), hafnium silicon oxynitride (HfSiON), lanthanum oxide (La₂O₃) or any dielectric with a permittivity (k) value larger than 6. The spacers 116a and 116b comprise silicon oxynitride (SiON), silicon dioxide (SiO₂), Si^N₄, high-k materials or combinations thereof. Different combination of materials can also be used to enhance the operation of the device. The source region 132 and the drain region 122 may additionally be strapped with a conductive material such as metal suicides to reduce the electrical resistance. An example of a metal suicide commonly used to reduce the resistance in source and drain regions is nickel suicide (NiSi).

In another embodiment, the gate electrode 114 comprises polysilicort with a nitride hard mask on top. The nitride hard mask comprises a material selected from a group comprising silicon oxide, silicon oxynitride and any dielectric material.

In another embodiment, the first semiconductor layer 106 can comprise a plurality of sub-layers, the sub-layers comprising silicon, germanium, carbon, or combination thereof, or compound semiconductors. For example, the first semiconductor layer 106 may comprise two sub-layers such as a silicon-germanium sub-layer formed on a silicon sub-layer. Having two sub-layers can give the advantage of strain control and bandgap engineering at the impact ionization region 136 below the spacer 116a. In addition, the second semiconductor layer 126 may also be comprised of a plurality of sub-layers comprising elemental semiconductors, compound semiconductors, or alloy semiconductors. For example, the second semiconductor layer may comprise a germanium layer formed on a silicon-germanium layer.

in other embodiments, the substrate structure 104 is a bulk semiconductor or a semiconductor-on-insulator substrate. Bulk semiconductor substrates comprise elemental semiconductors such as silicon, germanium, carbon, or compound semiconductors such as gallium arsenide, indium phosphide, indium antimonide, or combinations thereof.

In the example embodiment of the device 100, approximate thicknesses for the insulation layer 112, the first semiconductor layer 106, the second semiconductor layer 126 and the gate electrode 114 are 2θA, 6OθA, 500A and 1000 A respectively. The gate electrode 114 has a width W₁₁₄ of approximately 60nm. The L-shaped length L₁₃₆ of the L-shaped impact ionization region 136 is approximately 60 nm. The widths W_116a and W_116b of the spacers 116a and 116b are respectively approximately 40nm each.

Dimensions of the device 100 are not only limited to the above parameters. The spacer widths W₁₁₆₃ and W_116b are preferably chosen to be thick enough to keep hot carriers occurring within the impact ionization region 136 from reaching the gate dielectric layer 112. On the other hand, the spacer widths W₁₁₆₃ and Wii_6b are preferably chosen to be not too thick as this will increase the resistance of the impact ionization region 136 and thereby induce a greater voltage drop across the impact ionization region 136. The dimensions of the spacer widths W₁₁₆₃ and W_116b depend on the technology application. Spacer widths W₁₁₆₃ and W_116b are preferably between approximately 2 nm and approximately 200nm, and more preferably between about 2 nm and 100 nm, and even more preferably between about 2 nm and 50 nm. It should be noted that the spacer width generally scales with technology generations. The thickness of the gate dielectric or insulation layer 112 can range from about 0.4 nm to about 20 nm, more preferably from about 0.4 nm to about 5 nm, and even more preferably from about 0.4 nm to about 1.5 nm. The thickness of the gate electrode may be about 10 nm to about 200 nm, and more preferably about 10 nm to 100 nm.

In the embodiment where the first semiconductor layer 106 comprises two sub-layers, the thicknesses of the first sub-layer and the second sub-layer are each preferably between about 1 nm to about 50 nm. In another embodiment the first sub-layer and the second sub-layer are each between about 1 nm to about 100 nm.

Operation of an n-channel device 100 of Figure 1 using device materials and dimensions summarized respectively in tables 1 and 2 below was simulated using Synopsys Technology Computer-Aided-Design (TCAD) tools. The second layer 126 was p+ doped. Hydrodynamic equations using the non-local field approach were solved.

Table 1: Device materials and parameters used for first simulation set

Table 2: Device materials and parameters used for second simulation set

The simulation results are now discussed with reference to Figures 2, 3, 4 and 5.

Figure 2 shows a schematic of band-to-band carrier generation rate contour plots 201 occurring at the impact ionization region 136 of an n-channel device 100 of Figure 1. The device materials and parameters of the n-channei device 100 used are those summarized in table 1. As mentioned earlier, Figure 2 has been simulated using Synopsys (TCAD) tools. The lowest band-to-band generation rate is 1ύ^1ocm³/s, while the highest band-to-band generation rate is 10²⁸cm³/s.

In Figure 2, a thin layer of liner 212 between the gate eleGtrode 114 and the spacers 116a and 116b is formed. The liner 212 comprises silicon dioxide.

It can be observed from Figure 2 that while a portion of the band-to-band generation rate contour plots 201 may extend beyond the impact ionization region (compare impact ionization region 136 of Figure 1) the highest band-to-band generation region, referred to as the hot carrier activity region 203, occurs at the edge of the spacer 116a. Thus, current density is highest at the corner of the liner 212 corresponding to the area below the spacer 116a. As the hot carrier activity region 203 does not occur in the region below the gate dielectric layer 112, little hot carriers will be injected into the gate electrode 114 and the gate dielectric layer 112, therefore reducing the effect of hot carrier degradation on the gate dielectric layer 112 and the gate electrode 114. It can also be observed that most of the hot carrier activity region 203 occurs in the vertical area adjacent to the spacer 116a and away from the gate dielectric 112.

Figure 3 shows a schematic of holes concentration contour plots 301 generated by^' impact ionization from hot electrons occurring at the impact ionization region 136 of an n-bhaηnel device 100 of Figure 1. The device materials and parameters of the n- channel device 100 used are those summarized in table 1. As mentioned earlier, Figure 3 has been simulated using Synopsys (TCAD) tools. The lowest holes concentration is 10¹⁶cm^"3, while the highest holes concentration is 10¹⁹cm^"3.

From Figure 3, it can be seen that most of the holes concentration contour plots 301 are confined within the impact ionization region 136. It can thus be appreciated that carrier multiplication is also confined within the impact ionization region 136. The highest hole concentration contour plot 303 occurs near the surface of the second semiconductor layer 126. This allows for the impact ionization region 136 to be scaled vertically by changing the thickness of the second semiconductor layer 126 or changing the depth of the p+ doping profile through, for example, implantation or in- situ doping of the source region 132. Vertical scaling has the advantage of saving silicon (substrate) area.

Figure 4 shows a plot of the simulated drain current I₀ (A/μm) against gate voltage V_G (V). The curve 401 represents the semiconductor device 100 of Figure 1 using device materials and dimensions tabulated in table 1. The curve 402 represents the semiconductor device 100 of Figure 1 using device materials and dimensions tabulated in table 2. The operating conditions for both curves are as follows: source voltages V₅ biased at -5.25V and -1.8V, respectively, for silicon (Table 1 ) and germanium (Table 2) LI-MOS devices; and both. drain voltages V_D being grounded.

Both curves show that a subthreshold slope of less than 5mV/dec with a low Wl_όπ ratio and a threshold voltage V_r of 0.10V can be achieved. The silicon based and the germanium based devices 100 have a subthreshold swing of 4.5 mV/decade and 0.2 mV/decade, respectively.

Figure 5 shows a plot of the simulated gate current I_G (A/μm) against gate voltage V_G (V). The gate current I_G reflects the hot electrons flow as a function of gate voltage V_G. The curve 501 represents. the device 100 of Figure 1 using device materials and dimensions tabulated in table 1. The curve 502 represents the semiconductor device 100 of Figure 1 using device materials and dimensions tabulated in table 2. The operating conditions for both curves are as follows: source voltages V₅ biased at - 5.25V and -1.8V, respectively, for silicon and germanium LI-MOS devices; and both drain voltages V_D being grounded.

Comparing curves 501 and 502 it can be seen that the germanium based device 100 has a lower carrier injection current to the gate electrode 114 even though the germanium based device 100 has a higher impact ionization rate than the silicon based device 100. However, the gate currents in the silicon based device 100 and the germanium based device 100 can be considered negligible as they are in the order of below 1 Q^"15 A/μm. The hot carrier reliability of the device 100 can thus be appreciated.

Figure 6 shows a cross sectional view of an L-shaped Impact Ionization Metal-Oxide- Semiconductor (LI-MOS) transistor device 600 built in accordance with one embodiment of the present invention.

Fabrication of embodiments of Ll-MOS transistor devices built in accordance with the present invention will now be described with reference to Figures 6 to 11.

In Figure 6A, the device structure 600 comprising a gate stack 602 formed on a substrate structure 604 is provided. The substrate structure 604 is a semiconductor- on-insulator substrate comprising a first semiconductor layer 606 formed on an insulation layer 608 on a wafer substrate 610. The gate stack 602 comprises a gate insulator or gate dielectric layer 612 formed on the first semiconductor layer 606, and the gate or gate electrode 614 formed above the. gate dielectric layer 612. The gate electrode 614 may comprise of a hard mask at the top surface that could be retained during subsequent selective epitaxy step and ion implantation step. The hardmask may comprise one or more layers of silicon dioxide, silicon oxynitride, or any dielectric material. Spacers 616a and 616b are formed on opposite sides of the gate electrode 614. It will be appreciated by the person skilled in the. art that the device structure 600 can be formed using known fabrication processes to fabricate a gate stack with adjacent spacers, e.g. employing lithographic processes, etching processes, and deposition processes such as sputtering, chemical vapour deposition (CVD)₁ and epitaxial growth.

In the example embodiment, the first semiconductor layer 606 comprises silicon. The wafer substrate 610 comprises bulk silicon, while the insulation layer 608 comprises silicon dioxide. The gate electrode 614 comprises polysilicon with a nitride hard mask on top. The gate dielectric layer 612 comprises silicon dioxide. The spacers 616a and 616b comprise silicon nitride. The nitride hard mask comprises a material selected from a group comprising silicon oxide, silicon oxynitride and any dielectric material. However, it will be appreciated that different materials may be used in different embodiments.

Jri another embodiment, the substrate structure 604 comprises a bulk semiconductor substrate. The spacers 616a and 616b can comprise materials such as SiON₁ Si₃N₄, SiO₂, or a high-k material.

Next, as shown in Figure 6B₁ an optional oxide layer 618 is deposited over the device structure 600, in the example embodiment using low-pressure chemical vapor deposition (LPCVD) or plasma-enhanced chemical vapor deposition (PECVD). The oxide layer 618 can be used to prevent ion channeling during a subsequent ion implantation step. A photo resist 620 is then deposited and patterned using lithography techniques known in the art so that it is above the first semiconductor layer 606 on one side of the gate stack 602 and extending above one of the spacers 616a and above a portion of the gate electrode 614.

Next, a doping step by ion implantation, plasma immersion ion implantation or diffusion source is performed to form a drain region 622 in the first semiconductor layer 606 in areas not covered by the photo resist 620, and extending below the spacer 616b. To obtain an n-channel device, n+ dopants will be used while to obtain a p-channel device, p+ dopants will be used.

After removal of the photo resist 620 by chemical resist stripping (CRS) or plasma resist stripping (PRS) and the oxide layer 618 by hydrogen fluoric acide (HF) dip (if the optional oxide layer 618 in Figure 6B was used), a mask 624 is formed. The mask 624, which preferably comprises silicon oxide, covers the drain region 622, and exposes the substrate region on the opposing side of the gate stack, as shown in Figure 6C. The silicon oxide mask 624 may be formed by depositing silicon oxide over the device structure, patterning a photo resist (not shown) to cover the silicon oxide over the drain region 622, etching the uncovered silicon oxide, and removing the photo resist. A second semiconductor layer 626 is then epitaxially grown above the exposed surface portion of the first semiconductor layer 606. The. epitaxial growth of the second semiconductor layer 626 employs a selective epitaxy process which uses any one or more of a group of gases consisting of silane, disilane, methyl-silane, germane, and chlorine, depending on the material of the second semiconductor layer 626. The gases silane, disilane, methyl-silane, or germane may be mixed with a carrier gas such as hydrogen or argon. In the example embodiment, the second semiconductor layer 626 comprises silicon and germanium, however it will be appreciated that other semiconductor materials may be used in different embodiments.

Next, the mask 624 is removed by a suitable etch. Jn the preferred embodiment, the etch employs HF. An optional oxide layer 628 is formed using LPCVD or PECVD. Photo resist 630 is then formed one side of the gate stack 602 extending above the drain region 622, the spacer 616b and above a portion of the gate electrode 614, as shown in Figure 6D.

Next, a doping step by ion implantation* plasma ion implantation or diffusion source is performed to form a heavy-doped source region 632 in the second semiconductor layer 626. To obtain an n-channel device, p+ dopants will be used while to obtain a p- channel device, n+ dopants will be used.

Figure 6E shows the resulting structure 634 after removal by chemical resist stripping (CRS) or plasma resist stripping (PRS) of the photo resist 630 and the oxide layer 628. The device structure 634 has an L-shaped impact ionization region 636 extending vertically below the source region 632, and horizontally below the spacer 616a. As described earlier with reference to the simulation results illustrated in Figures 2 and 3, the device structure 634 can be designed such that the hot carrier concentration in the impact ionization region 636 does not extend below the gate dielectric layer 612, thus avoiding damage to the gate dielectric that may be caused by the hot carriers. Furthermore, the overall length or dimension of the impact ionization region 636 between the source region 632 and the drain region 622 can be readily controlled or varied during the fabrication of the device structure 634. This is because the vertical portion of the impact ionization region 636 can be very accurately controlled through the epitaxial growth of the second semiconductor layer 626 (see figure 6C) on the one hand, and control of the doping process to form the source region 632 (see Figure 6D), Also, the L-shaped impact ionization region 636 allows for a compact design without sacrificing silicon (substrate) area.

It should be noted that the fabrication process described thus far may be slightly modified while still achieving the structure 634 of Figure 6E. For example, the formation of the second semiconductor layer 626 by selective epitaxy and the doping of the source region 632 may preceed the formation of the drain region 622.

The device structure 634 is then subjected to annealing and a suitable Back-End-Of- Line process (BEOL) to form the finished LI-MOS transistor device. The BEOL process includes first, a partial or full silicidatioh of the source region 632, drain region 622, and gate electrode 614. Next, a silicon nitride contact etch-stop layer is deposited, and an interlayer dielectric comprising silicon dioxide is deposited. This is followed by contact etching, and a metal such as tungsten is deposited to form the via. A damascene process is then employed to form metal lines to connect various devices. Damascene processes Known in the art, such as dual damascene or single damascene processes, may be employed.

Turning now to Figure 7A, a fabrication process according to another example embodiment will be described. The starting device structure 700 is the same as the starting device structure 600 shown in Figure 6A. The same numerals have been used to indicate the same layers.

Next, as shown in Figure 7B, an optional oxide layer 713 is deposited over the device structure 700, in the example embodiment using LPCVD or PECVD. A photo resist 720 is then deposited and patterned using lithography techniques known in the art so that it is above the first semiconductor layer 606 on one side of the gate stack 602 and extending above one of the spacers 616a and above a portion of the gate electrode 614. Next, a doping step by ion implantation, plasma ion implantation or diffusion source is performed to form a drain region 722 in the first semiconductor layer 606 in areas not covered by the photoresist 720, and extending below the spacer 616b. To obtain an n- channel device, n+ dopants will be used while to obtain a p-channel device, p+ dopants will be used.

After removal of the photo resist 720 by chemical resist stripping (CRS) or plasma resist stripping (PRS) and the oxide layer 713 by HF dip, a mask 724 is formed. The mask 724, which preferably comprises silicon oxide, covers the drain region 722, and exposes the substrate region on the opposing side of the gate stack, as shown in Figure 7C. A second semiconductor layer 726 is then epitaxially grown above the exposed surface portion of the first semiconductor layer 606. In the example embodiment, the second semiconductor layer 726 comprises silicon and germanium, however it will be appreciated that other semiconductor materials may be used in different embodiments. In this embodiment, the second semiconductor layer 726 is initially grown to a height which will later form part of the L-shaped impact ionization region underneath a source region.

In Figure /D, a combined deposition and iή-situ doping step during selective epitaxy is performed to form a heavy-doped source region 732. The selective epitaxy employs any one or more of a group consisting of silane, disilane, methyl-silane, germane, and chlorine, depending on the material of the second semiconductor layer 726. The gases silane, disilane, methyl-silane, or germane may be mixed with a carrier gas such as hydrogen or argon. During this step, the second semiconductor layer 726 continues to be grown epitaxially with in-situ doping to form the source region 732. To obtain an n- chahnel device, p+ dopants will be used while to obtain a p-channel device, n+ dopants will be used in the in-situ doped source region 732.

Figure 7E shows the resulting. structure 734 after the mask 724 is removed by a suitable etch. In the preferred embodiment, the etch employs. HF. Again, the device structure 734 has an L-shaped impact ionization region 736 extending vertically below the source region 732, and horizontally below the spacer 616a. The overall length or dimension of the impact ionization region 736 between the source region 732 and the drain region 722 can be readily controlled or varied during the fabrication of the device structure 734. This is because the vertical portion of the impact ionization region 736 can be very accurately controlled through the epitaxial growth of the second semiconductor layer 726 (see figure 7C).

It should be noted that in the fabrication process just described, modifications to the order of the process steps may be made while still achieving the device structure 734 of Figure 7E. For example, the steps of forming of the second semiconductor layer 726 by selective epitaxy and forming the in-situ doped source region 732 may be performed prior to the step of doping the drain region 722.

The device structure 734 is then subjected to annealing and a suitable Back-End-Of- Line process (BEOL) to form the finished LI-MOS transistor device. The BEOL process includes first; a partial or full silicidation of the source region 732, drain region 722, and gate electrode 614. Next a silicon nitride contact etch-stop layer is deposited, and an interlayer dielectric comprising silicon dioxide is deposited. This is followed by contact etching, and metal like tungsten is deposited to form the via. A damascene process is then employed to form metal lines to connect various devices.

Turning now to Figure 8A, a fabrication process according to another example embodiment will be described. The starting device structure 800 is the same as the starting device structure 600 shown in Figure 6A, while the same numerals have been used to indicate the same layers.

Next, as shown in Figure 8B, an optional oxide layer 813 is deposited over the device structure 800, in the example embodiment using LPCVD or PECVD. A photo resist 820 is then deposited and patterned using lithography techniques known in the art so that it is above the first semiconductor layer 606 on one side of the gate stack 602 and extending above one of the spacers 616a and above a portion of the gate electrode 614.

Next, a doping step by ion implantation, plasma ion implantation or diffusion source is performed to form a drain region 822 in the first semiconductor layer 606 in areas not covered by the photo resist 820, and extending below the spacer 616b. To obtain an n-channel device, n+ dopants will be used while to. obtain a p-channei device, p+ dopants will be used. After removal of the photo resist 820 by chemical resist stripping (CRS) or plasma resist stripping (PRS), and the oxide layer 813 by HF dip, a mask 824 is formed. The mask 824, which preferably comprises silicon oxide, covers the drain region 822, and exposes the substrate region on the opposing side of the gate stack, as shown in Figure 8C. A second semiconductor layer 816 comprising material is epitaxially grown above the exposed surface portion of the first semiconductor layer 606. The second semiconductor layer 816 will later form part of the L-shaped impact ionization region underneath a source region. Next, a third semiconductor layer 826 is epitaxially grown above the second semiconductor layer 606a.

In the example embodiment, the second semiconductor layer 816 and third semiconductor layer 826 comprise silicon, however it will be appreciated that other semiconductor materials may be used in different embodiments.

Next, the mask 824 is removed by a suitable etch. In the preferred embodiment, the etch employs HF. An oxide layer 828 is deposited by PECVD. Photo resist 830 is then formed on one side of the gate stack 602 extending above the drain region 822, the spacer 616b and above a portion of the gate electrode 614, as shown in Figure 8D.

Next, a doping step by ion implantation, plasma ion implantation or diffusion source is performed to form a heavy-doped source region 832 in the second semiconductor layer 826. To obtain an n-channel device, p+ dopants will be used while to obtain a p- channel device, n+ dopants will be used.

Figure 8E shows the resulting structure 834 after removal of the photo resist 830 by chemical resist stripping (CRS) or plasma resist stripping (PRS), and the oxide layer 828 by HF dip. The device structure 834 has an L-shaped impact ionization region 836 extending vertically below the source region 832, and horizontally below the spacer 616a. The overall length or dimension of the impact ionisation region 836 between the source region 832 and the drain region 822 can be readily controlled or varied during the fabrication of the device structure 834. This is because the vertical portion of the impact ionisation region 836 can be very accurately controlled through the epitaxial growth of the second semiconductor layer 816 (see figure 8G) on the one hand, and control of the doping process to form the source region 832 (see Figure 8D). The device structure 834 is then subjected to annealing and a suitable Back-End-Of- i_ine process (BEOL) to form the finished LI-MOS transistor device. The BEOL process includes first, a partial or full silicidation of the source region 832, drain region 822, and gate electrode 614. Next, a silicon nitride contact etch-stop layer is deposited, and an interlayer dielectric comprising silicon dioxide is deposited. This is followed by contact etching, and metal like tungsten is deposited to form the via. A damascene process is then employed to form metal lines to connect various devices.

Turning now to Figure 9A, a fabrication process according to another example embodiment will be described, the starting device structure 900 is the same as the starting device structure 600 shown in Figure 6A, while the same numerals have been used to indicate the same layers.

Next, as shown in Figure 9B, an oxide layer 913 is deposited over the device structure 900, in the example embodiment using LPGVD or PECVD. A photo resist 920 is then deposited and patterned using lithography techniques known in the art so that it is above the first semiconductor layer 606 on one side of the gate stack 602 and extending above one of the spacers 616a and above a portion of the gate electrode 614.

A doping step by ion implantation, plasma ion implantation or diffusion source is then performed to form a drain region 922 in the first semiconductor layer 606 in areas not covered by the photoresist 920, and extending below the spacer 616b. To obtain an n- channel device, n+ dopants will be used while to obtain a p-channel device, p+ dopants will be used.

After removal of the photo resist 920 by chemical resist stripping (CRS) or plasma resist stripping (PRS).and the oxide layer 913 by HF dip, a mask 924 is formed. The mask 924, which preferably comprises silicon oxide, covers the drain region 922, and exposes the substrate region on the opposing side of the gate stack, as shown in Figure 9C. A second semiconductor layer 916 is epϊtaxially grown above the exposed surface portion of the first semiconductor layer 606. The second semiconductor layer 916 will later form part of the L-shaped impact ionization region underneath a source region. In Figure 9D, a combined deposition and in-situ doping step during selective epitaxy is performed to form a heavy-doped source region 932. The selective epitaxy employs any one or more of a group consisting of silane, disilane, methyl-silane, germane, and chlorine, depending on the material of the second semiconductor layer 926. The gases silane, disilane, methyl-silane, or germane may be mixed with a carrier gas such as hydrogen or argon. During this step, a third semiconductor layer 926 is epitaxially grown with in-situ doping to form the source region 932 above the exposed second semiconductor layer 916. To obtain an n-channel device, p+ dopants will be used while to obtain a p-Ghannel device, n+ dopants will be used. In the example embodiment, the second semiconductor 916 and third semiconductor layer 926 comprise silicon, however it will be appreciated that other semiconductor materials may be used in different embodiments.

Figure 9E shows the resulting structure 934 after removal of the mask 924 by a suitable etch. In the preferred embodiment, the etch employs HF. Again, the device structure 934 has aη L-shaped impact ionization region 936 extending vertically below the source region 932, and horizontally below the spacer 616a. The overall length or dimension of the impact ionization region 936 between the source region 932 and the drain region 922 can be readily controlled or varied during the fabrication of the device structure 934. This is because the vertical portion of the impact ionization region 936 can be very accurately controlled through the epitaxial growth of the second semiconductor layer 916 (see figure 9C).

The device structure 934 is then subjected to annealing and a suitable Back-End-Of- Line process (BEOL) to form the finished LI-MOS transistor device. The BEOL process includes first, a partial or full silicidation of the source region 932, drain region 922, and gate electrode 614. Next, a silicon nitride contact etch-stop layer is deposited, and an ϊnterlayer dielectric which comprises silicon dioxide is deposited. This is followed by contact etching, and metat like tungsten is deposited to form the via. A damascene process is then employed to form metal lines to connect various devices.

Turning now to Figure 1OA, a fabrication process according to another example embodiment will be described. The starting device structure 1000 is the same as the starting device structure 600 shown in Figure 6A. The same numerals have been used to indicate the same layers.

Next, as shown in Figure 1OB, an optional oxide layer 1013 is deposited over the device structure 1000, in the example embodiment using LPCVD or PECVD. A photo resist 1020 is then deposited and patterned using photolithogaphy techniques known in the art so that it is above the first semiconductor layer 606 on one side of the gate stack 602 and extending above one of the spacers 616a and above a portion of the gate electrode 614.

Next, a doping step by ion implantation, plasma ion implantation or diffusion source is performed to form a drain region 1022 in the first semiconductor layer 606 in areas not covered by the photoresist 1020, and extending below the spacer 616b. To obtain an n-channel device, n+ dopants will be used while to obtain a p-channel device, p+ dopants will be used.

After removal of the photo resist 1020 by chemical resist stripping (CRS) or plasma resist stripping (PRS) and the oxide layer 1013 by HF dip, a mask 1024 is formed. The mask 1024, which preferably comprises silicon oxide, covers the drain region 1022, and exposes the substrate region on the opposing side of the gate stack, as shown in Figure 10C. The exposed portion of the first semiconductor layer 606 is etched to form a recess 1006 extending below the spacer 616a as shown in Figure IOC: The etch can be performed, for example, with a dry plasma etch process or a wet etch process or a physical sputtering process. An optional surface repair step, such as an annealing step, may be performed to repair any etch damage on the surface of the etched recess 1006. The annealing step may employ a temperature of above 350 degrees Celsius and may be performed in a hydrogen ambient, for example.

In Figure 10D, a second semiconductor layer 1016 comprising material is epitaxially grown on the recess 1006 of the first semiconductor layer 1006. The second semiconductor layer 1016 will later form part of the L-shaped impact ionization region underneath a source region. A combined deposition and in-situ doping step during selective epitaxy is performed to form a heavy-doped source region 1032. The selective epitaxy employs any one or more of a group consisting of silane, disilane, methyl-silane or germane, depending on the material of the second semiconductor layer 1026. The gases silane,. disilane, methyl-silane, or germane may be mixed with a carrier gas such as hydrogen or argon. During this step, a third semiconductor layer 1026 is epitaxially grown with in-situ doping to form the source region 1032 above the exposed second semiconductor layer 1016. To obtain an n-channel device, p+ dopants will be used while to obtain a p-channel device, n+ dopants will be used. In the example embodiment, the second semiconductor layer 1016 and third semiconductor layer 1026 comprise silicon, however it will be appreciated that other semiconductor materials may be used in different embodiments.

Figure 10E shows the resulting structure 1034 after removal of the mask 1024 by a suitable etch. In the preferred embodiment, the etch employs HF. Again, the device structure 1034 has an L-shaped impact ionization region 1036 extending vertically below the source region 1032, and horizontally below the spacer 616a. The overall length or dimension of the impact ionization region 1036 between the source region 1032 and the drain region 1022 can be readily controlled or varied during the fabrication of the device structure 1034. This is because the vertical portion of the impact ionization region 1036 can be very accurately controlled through the epitaxial growth of the second semiconductor layer 1016 (see figure 10D).

The device structure 1034 is then subjected to annealing and a suitable Back-End-Of- Line process (BEOL) to form the finished LI-MOS transistor device. The BEOL process includes first, a partial or full silicidation of the source region 1032, drain region 1022, and gate electrode 614. Next, a silicon nitride contact etch-stop layer is deposited, and an iriterlayer dielectric comprising silicon dioxide is deposited. This is followed by contact etching, and metal like tungsten is deposited to form the via. A damascene process is then employed to form metal lines to connect various devices.

Turning now to Figure 11A₁ a fabrication process according to another example embodiment will be described. The starting device structure 1100 is the same as the starting device structure 600 shown in Figure 6A, while the same numerals have been used to indicate the same layers.

Next, as shown in Figure 11 B, an optional oxide layer 1113 is deposited over the device structure 1100, in the example embodiment using LPCVD or PECVD. A photo resist 1120 is then deposited and patterned using photolithography techniques known in the art so that it is above the first semiconductor layer 606 on one side of the gate stack 602 and extending above one of the spacers 616a and above a portion of the gate electrode 614.

A doping step by ion implantation , plasma ion implantation or diffusion source is then performed to form a drain region 1122 in the first semiconductor layer 606 in areas not covered by the photoresist 1120, and extending below the spacer 616b. To obtain an n-channel device, n+ dopants will be used while to obtain a p-÷channel device, p+ dopants will be used.

After removal of the photo resist 1120 by chemical resist stripping (CRS) or plasma resist stripping (PRS),and the oxide layer 1113 by HF dip, a mask 1124 is formed. The mask 1124, which preferably comprises silicon oxide, covers the drain region 1122, and exposes the substrate region on the opposing side of the gate stack, as shown in Figure 11 C. A second semiconductor layer 1114 is epitaxially grown above the exposed surface portion of the first semiconductor layer 606. This is followed by a condensation step to form a compound region 1118 within the first semiconductor layer 606 so that a portion of the compound region 1118 extends below a portion of the spacer 616a as shown in Figure .11 D.

In Figure 11E₃ a third semiconductor layer 11,16 is epitaxially grown above the compound region 1118 of the first semiconductor layer 606. The third semiconductor layer 1116 will later form part of the L-shaped impact ionization region underneath a source region. A combined deposition and in-situ doping step during selective epitaxy is performed to form a heavy-doped source region 1132. The selective epitaxy employs anyone or more of a group consisting of silane, disilane, methyl-silane, germane, and chlorine, depending on the material of the second semiconductor layer 1126. The gases silahβj disilane, methyl-silane, or germane may be mixed with a carrier gas such as hydrogen or argori. During this step, a fourth semiconductor layer 1126 is epitaxially grown with in-situ doping to form the source region 1132 above the exposed third semiconductor layer 1116. To obtain an n-channel device, p+ dopants will be used while to obtain a p-channel device, n+ dopants will be used. In the example embodiment, the second semiconductor layer 1114, the third semiconductor layer 1116 and the fourth semiconductor layer 1126 comprise silicon germanium. However it will be appreciated that other semiconductor materials may be used in different embodiments.

Figure 11 F shows the resulting structure 1134 after removal of the mask 1124 by a suitable etch. In the preferred embodiment, the etch employs HF. Again, the device structure 1134 has an L-shaped impact ionization region 1136 extending vertically below the source region 1132, and horizontally below the spacer 616a. The overall length or dimension of the impact ionization region 1136 between the source region 1132 and the drain region 1122 can be readily controlled or varied during the fabrication of the device structure 1134. This is because the vertical portion of the impact ionization region 1136 can be very accurately controlled through the epitaxial growth of the fourth semiconductor layer 1126 (see figure 11 E).

The device structure 1134 is then subjected to annealing and a suitable Back-End-Of- Line process (BEOL) to form the finished LI-MOS transistor device. The BEOL process includes first, a partial or full silicldation of the source region 1132, drain region 1122, and gate electrode 614. Next, a silicon nitride contact etch-stop layer is deposited, and an interiayer dielectric which could be silicon dioxide is deposited. Thjs is followed by contact etching, and metal like tungsten is deposited to form the via. A damascene process is then employed to form metal lines to connect various devices.

Figure 12 shows a cross sectional View of an L-shaped Impact Ionization Metal-Oxide- Semiconductor (LI-MOS) transistor device 1200 built in accordance with one embodiment of the present invention.

The device 1200 comprises a gate stack 1202 formed on a substrate structure 1204. The substrate structure 1204 comprises a first semiconductor layer 1206 formed above an insulation layer 1208 on a wafer substrate 1210. The gate stack 1202 comprises a gate dielectric layer 1212 formed on the first semiconductor layer 1206, a gate electrode 1214 formed above the gate dielectric layer 1212. Spacers 1216a and 1216b are formed on opposite sides of the gate electrode 1214. A second semiconductor layer 1226 is formed above the substrate structure 1204.

A source structure comprising a heavy doped source region 1232 is formed within the second semiconductor layer 1226, the second semiconductor layer 1226 itself having a dopant concentration below 10¹⁸Cm^"3, adjacent to the spacer 1216a while a drain region 1222 is formed within the second semiconductor layer 1226 adjacent to the spacer 1216b extending below the spacer 1216b so that a portion of the drain region 1222 is formed within the substrate structure 1204. For an n-channel device 1200, the source region 1232 will be p+ doped while the drain region 1222 will be n+ doped. For a p-channel device 1200, the source region 1232 will be n+ doped while the drain region 1522 will be p+ doped.

A conducting channel (not shown), spanning from the source region 1232 to the drain region 1222 will be formed when the device 1200 is suitably biased.

For the device 1200, an L-shaped impact ionization region 1236 extends vertically below the source region 1226, and horizontally below the spacer 1216a.

In the example embodiment, the first semiconductor layer 1206 and the second semiconductor layer 1226 comprises silicon. The wafer substrate 1210 comprises bulk silicon, while the insulation layer 1208 comprises silicon dioxide. The gate electrode 1214 comprises polysilicon. The gate dielectric layer comprises silicon dioxide. The spacers 1216a and 1216b comprise silicon nitride.

in other embodiments, the substrate structure 1204 is a bulk semiconductor substrate which may comprise elemental semiconductors such as silicon, germanium, carbon, or compound semiconductors such as gallium arsenide, indium phosphide, indium antimonide, or combinations thereof.

Figure 13 shows a cross sectional view of an L-shaped Impact Ionization Metal-Oxide- Semiconductor (LI-MOS) transistor device 1300 built in accordance with one embodiment of the present invention.

Fabrication of embodiments of LI-MOS transistor devices built in accordance with the present invention will now be described with reference to Figures 13 to 14.

Turning now to Figure 13A, a fabrication process according to another example embodiment will be described. The starting device structure 1300 is the same as the starting device structure 600 shown in Figure 6A. The same numerals have been used to indicate the same layers.

Next, as shown in Figure 13B, a second semiconductor layer 1326 is epitaxially grown above the first semiconductor layer 606 on both sides of the gate stack 602. In the example embodiment, the second semiconductor layer 1326 comprises silicon, however it will be appreciated that other semiconductor materials, such as silicon- germanium and germanium, may be used in different embodiments.

In Figure 13C, a photo resist 1320 is deposited and patterned using stepper track so that it is above the second semiconductor layer 606 on one side of. the gate stack 602 and extending above one of the spacers 616a and above a portion of the gate electrode 614.

Next, a doping step by ion implantation, plasma ion implantation or diffusion source is performed to form a drain region 1322 extending from the second semiconductor layer 1326 and the first semiconductor layer 606 in areas not covered by the photo resist 1320 to below the spacer 616b. To obtain an n-channel device, n+ dopants will be used while to obtain a p-channel device, p+ dopants will be used.

After removal of the photo resist 1320 by chemical resist stripping (CRS) or plasma resist stripping (PRS), a photo resist 1330 is then formed on the other side of the gate stack 602 extending above the drain region 1322* the spacer 616b and above a portion of the gate electrode 614* as shown in Figure 13D.

Next, a doping step by ion implantation, plasma ion implantation or diffusion source is performed to form a heavy-doped source region 1332 in the exposed portion of the second semiconductor layer 1326. To obtain an n-cbaήnel device, p+ dopants will be used while to obtain a p-channel device, n+.dopants will be used.

Figure 13E shows the resulting structure 1334 after removal of the photo resist 1330 by chemical resist stripping (GRS) or plasma resist stripping (PRS). The device structure 1334 has an L-shaped impact ionization region 1336 extending vertically below the source region 1332, and horizontally below the spacer 616a. The overall length or dimension of the impact ionization region 1336 between the source region 1332 and the drain region 1322 can be readily controlled or varied during the fabrication of the device structure 1334. This is because the vertical portion of the impact ionization region 1336 can be very accurately controlled through the epitaxial growth of the second semiconductor layer 1326 (see figure 13B) on the one hand, and control of the doping process to from the source region 1332 (see Figure 13D). Also, the L-shaped impact ionization region 1036 allows for a compact design without sacrificing silicon (substrate) area.

It will be appreciated by the person skilled in the art that the fabrication process described with reference to Figures 13A to 13E are readily compatible with current CMOS fabrication steps.

The device structure 1334 is then subjected to annealing and a suitable Back-End-Of- Line process (BEOL) to form the finished LI-MOS transistor deyiGe. The BEOL process includes first, a partial or full silicidation of the source region 1332, drain region 1322, and gate electrode 614. Next, a silicon nitride contact etch-stop layer is deposited, and an interlayer dielectric comprising silicon dioxide is deposited. This is followed by contact etching, and metal like tungsten is deposited to form the via. A damascene process is then employed to forrri metal lines to connect various devices. . Having a raised source region 1332 and a raised drain region 1322 in the finished Ll- MOS transistor device may facilitate subsequent circuit interconnection between other peripheral devices.

Turning now to Figure 14A, a fabrication process according to another example embodiment will be described. The starting device structure 1400 is the same as the starting device structure 600 shown in Figure.6A, while the same numerals have been used to indicate the same layers.

Next, as shown in Figure 14B, a second semiconductor layer 1416 is epitaxially grown above the exposed surface portion of the first semiconductor layer 606. The second semiconductor layer 1416 will later form part of the L-shaped impact ionization region underneath a source region. A third semiconductor layer 1426 is then epitaxially grown above the second semiconductor layer 1416. In the example embodiment, the second semiconductor layer 1416 and the third semiconductor layer 1426 comprise silicon, however it will be appreciated that other semiconductor materials may be used in different embodiments.

In Figure 14C, a photo resist 1420 is deposited and patterned using, stepper track so that it is above the third semiconductor layer 1426 on one side of the gate stack 602 and extending above one of the spacers 616a and above a portion of the gate electrode 614.

Next, a doping step by ion implantation, plasma ion implantation or diffusion source is performed to form a drain region 1422 extending from the third semiconductor layer 1426, the second semiconductor layer 1416 and the first semiconductor layer 606 in areas not covered by the photo resist 1420 to below the spacer 616b. To obtain an n- channel device, n+ dopants will be used while to obtain a p-channel device, p+ dopants will be used.

After removal of the photo resist 1420 by chemical resist stripping (CRS) or plasma resist stripping (PRS), a photo resist 1430 is then formed on one side of the gate stack 602 extending above the drain region 1422, the spacer 616b and above a portion of the gate electrode 614, as shown in Figure 14D.

Next, a doping step by ion implantation, plasma ion implantation or diffusion source is performed to form a heavy-doped source region 1432 in the exposed portion of the second semiconductor layer 1416. To obtain an n-channel device, p+ dopants will be used while to obtain a p-channel device, n+ dopants will be used.

Figure 14E shows the resulting structure 1434 after removal of the photo resist 1430 by chemical resist stripping (CRS) or plasma resist stripping (PRS). The device structure 1434 has an L-shaped impact ionization region 1436 extending vertically below the source region 1432, and horizontally below the spacer 616a. The overall length or dimension of the impact ionization region 1436 between the source region 1432 and the drain region 1422 can be readily controlled or varied during the fabrication of the device structure 1434. This is because the vertical portion of the impact ionization region 1436 can be very accurately controlled through the epitaxial growth of the second semiconductor layer 606a (see figure 14B) on the one hand, and control of the doping process to form the source region 1432 (see Figure 14D). Also* the L-shaped impact ionization region 1436 allows for a compact design without sacrificing silicon (substrate) area.

It will be appreciated by the person skilled in the art that the fabrication process described with reference to Figures 14A to 14E are readily compatible with current CMOS fabrication steps.

The device structure 1434 is then subjected to annealing and a suitable Back-End-Of- Line process (BEOL) to form the finished LI-MOS transistor device. The BEOL process includes first, a partial or full silicidatiόn of the source region 1432, drain region 1422, and gate electrode 614. Next, a silicon nitride contact etch-stop layer is deposited, and an interlayer dielectric comprising silicon dioxide is deposited. This is followed by contact etching, and metal like tungsten is deposited to form the via. A damascene process is then employed to form metal lines to connect various devices. Having a raised source region 1432 and a raised drain region 1412 in the finished Ll- MOS transistor device may facilitate subsequent circuit interconnection between other peripheral devices.

Figure 15 shows a cross sectional view of an L-shaped Impact Ionization Metal-Oxide- Semioonductor (LI-MOS) transistor device 1500 built in accordance with one embodiment of the present invention.

The device 1500 comprises a gate stack 1502 formed on a substrate structure 1504. The substrate structure 1504 comprises a semiconductor layer 1506, and a bulk substrate 1510. The gate stack 1502 comprises a gate dielectric layer 1512 formed on the first semiconductor layer 1506, a gate electrode 1514 formed above the gate dielectric layer 1512. Spacers 1516a and 1516b are formed on opposite sides of the gate electrode 1514. A second semiconductor layer 1526 is formed above the substrate structure 1504.

A source structure comprising a heavy doped source region 1532 is formed within the second semiconductor layer 1526, the second semiconductor layer 1526 itself having a dopant concentration below 10¹⁸Cm^"3, adjacent to the spacer 1516a while a drain region 1522 is formed within the first semiconductor layer 1506 adjacent to the spacer 1516b extending below the spacer 1516b so that the drain region 122 is formed within the substrate structure 1504. For an n-channel device 150Q, the source region 1532 will be p+ doped while the drain region 1522 will be n+ doped. For a p-channel device 1500, the source region 1532 will be n+ doped while the drain region 1522 will be p+ doped.

A conducting channel (not shown), spanning from the source region 1532 to the drain region 1522 will be formed when the device 1500 is suitably biased.

For the device 1500, an L-shaped impact ionization region 1536 extends vertically below the source region 1532, and horizontally below the spacer 1516a.

In the example embodiment, the first semiconductor layer 1506 and the second semiconductor layer 1526 comprises silicon. The wafer substrate 1510 comprises bulk silicon. The gate electrode 1-5.14 comprises polystlicon. The gate dielectric layer 1512 comprises silicon dioxide. The spacers 1516a and 1516b comprise silicon nitride.

ItWiII be appreciated by the person skilled in the art that the fabrication process described with reference to Figures 6 to 1.1 are readily compatible to fabricate device 1500.

Figure 16 shows a cross sectional View of an L-shaped Impact Ionization Metal-Oxide- Semiconductor (LI-MOS) transistor device 1600 built in accordance with one embodiment of the present invention.

The device 1600 comprises a gate stack 1602 formed on a substrate structure 1604. The substrate structure 1604 comprises a first semiconductor layer 1606 formed on a wafer substrate 1610. The gate stack 1602 comprises a gate dielectric layer 1612 formed on the first semiconductor layer 1606, a gate electrode 1614 formed above the gate dielectric layer 1612. Spacers 1616a arid 1616b are formed on opposite sides of the gate electrode 1614. A second semiconductor layer 1626 is formed above the substrate structure 1604.

A source structure comprising a heavy doped source region 1632 is formed within the second semiconductor layer 1626, the second semiconductor layer 1626 itself having a dopant concentration below 10¹⁸Cm^"3, adjacent to the spacer 1616a while a drain region 1622 is formed within the second semiconductor layer 1626 adjacent to the spacer 1616b extending below the spacer 1616b so that a portion of the drain region 1622 is formed within the substrate structure 1604. For an n-channel device 1600, the source region 1.632 will be p+ doped while the drain region 1622 will be n+ doped. For a p-channel device 1600, the source region 1632 will be n+ doped while the drain region 1622 will be p+ doped.

A conducting channel (not shown), spanning from the source region 1632 to the drain region 1622 will be formed when the device 1600 is suitably biased.

For the device 1600, an L-shaped impact ionization region 1636 extends vertically below the source region 1632, and horizontally below the spacer 1616a.

In the example embodiment the first semiconductor layer 1604 and the second semiconductor layer 1626 comprises silicon. The wafer substrate 1610 comprises bulk silicon. The gate electrode 1614 comprises polysilicon. The gate dielectric layer 1612 comprises silicon dioxide. The spacers 1616a and 1616b comprise silicon nitride.

It will be appreciated by the person skilled in the art that the fabrication process described with reference to Figures 13 to 14 are readily compatible to fabricate device 1600.

Figure 17 shows a cross sectional view of an L-shaped Impact Ionization Metal-Oxide- Semiconductor (LI-MOS) transistor device 1700 built in accordance with one embodiment of the present invention.

The device 1700 comprises a gate stack 1702 formed on a substrate structure 1704. The substrate structure 1704 comprises a first semiconductor layer 1706 formed above an insujation layer 1708 on a wafer substrate 1710. The gate stack 1702 comprises a first gate insulator or a first gate dielectric layer 1712 formed on the first semiconductor layer 1706, a charge storage layer 1710 formed above the first gate dielectric layer 1712, a second gate dielectric layer 1713 formed above the charge storage layer 1710 and a gate or gate electrode 1714 formed above the second gate dielectric layer 1713. Spacers 1716a and 1716b are formed on opposite sides of the gate electrode 1714. A second semiconductor layer 1726 is formed above the substrate structure 1704.

A source structure comprising a heavy doped source region 1732 is formed within the second. semiconductor layer 1726, the second semiconductor layer 1726 itself having a dopant concentration below Iu¹⁸CnT³, adjacent to the spacer 1716a while a drain region 1722 is formed within the second semiconductor layer 1726 adjacent to the spacer 116b extending below the spacer 1716b so that a portion of the drain region 1722 is formed within the substrate structure 1704. For an n-channel device 1700, the source region 1732 will be p+ doped while the drain region 1722 will be n+ doped. For a p-channel device 1700, the source region 1732 will be n+ doped while the drain region 1722 will be p+ doped.

A conducting channel (not shown), spanning from the source region 1732 to the drain region 1722 will be formed when the device 1700 is suitably biased.

As the charge storage layer 1710 retains a charge after removal of the biasing voltage applied to the device 1700, it will be Appreciated by the person skilled in the art that the device 1700 can be used in memory devices.

For the device 1700, an L-shaped impact ionization region 1736 extends vertically below the source region 1726, and horizontally below the spacer 1716a.

In the example embodiment, the first semiconductor layer 1706 and the second semiconductor layer 1726 comprises silicon. The wafer substrate 1710 comprises bulk silicon, while the insulation layer 1708 comprises silicon dioxide. The gate electrode 1714 comprises polysilicon. The first gate dielectric layer 1712 and the second gate dielectric layer 1713 comprise silicon dioxide. The charge storage layer 1710 comprises a floating gate made of polysilicon or silicon nitride. The spacers 1716a and 1716b comprise silicon nitride.

In another embodiment, the charge storage layer 1710 is a layer of discrete dots or quantum dots comprising metal, semiconductor or a dielectric material. In other embodiments, the charge storage layer 1710 comprises metal dots embedded in a dielectric matrix, semiconductor dots embedded in a dielectric matrix or a first dielectric with a smaller band gap embedded in a second dielectric matrix with a larger band gap.

Figure 18 shows the electrical circuit symbols for a LI-MOS device built in accordance with an embodiment of the present invention. Electrical circuit symbol 1802 is used to represent an n-channel LI-MOS while electrical circuit symbol 1804 is used to represent a p-channel LI-MOS.

Figures 19A to 19C shows basic electrical circuits 1900 comprising a LI-MOS device built in accordance with an embodiment of the present invention.

To form a first inverter electrical circuit 1902, an n-channel LI-MOS device 1802 is connected as shown to a resistor R while to form a second inverter electrical circuit 1904, a p-channel LI-MQS device 1804 is connected as shown to a resistor R. A third inverter electrical circuit 1906 is formed by connecting the n-channel LI-MOS device 1802 with the p-channel LI-MOS device 1804 as shown.

Two distinct power supply voltages V_DD and Vss are respectively used for each of the inverter circuits 1902, 1904 and 1906 while each of the outputs V_όut can be connected to a load (not shown). It will be appreciated by the person skilled in the art that the inverter circuits 1902, 1904 and 1906 can be appropriately arranged to form digital logic gates such as NλND, NOR arid XOR.

Figures 2OA and 2OB show inverter circuits comprising conventional CMOS devices and LI-MOS devices built in accordance with embodiments of the present invention.

To form a first inverter electrical circuit 2002, ah n-channel LI-MOS device 1802 is connected as shown to a conventional p-channel CMOS device 2006 while to form a second inverter electrical circuit 2004, a p-channel LI-MOS device 1804 is connected as shown to a conventional n-channel CMOS device 2008. Two distinct power supply voltages V_DD and V_ss are respectively used for each of the inverter circuits 2002 and 2004 while each of the outputs V_oyA can be connected to a load (not shown).

Figures 21 A to 21 C shows NAND logic gate circuits 2100 comprising conventional CMOS devices and LMMOS devices built in accordance with embodiments of the present invention.

A first NAND logic gate circuit 2102 is formed by connecting two n-channel LI-MOS devices 1802 that are in series with two parallel connected p-channel Ll-MOS devices 1804 as shown in Figure 21 A.

A second NAND logic gate circuit 2104 is formed by connecting one n-chaήnel LI-MOS device 1802 and one conventional n-channel CMOS device 2108 that are in series with two parallel connected p<;hannel Ll-MOS devices 1804 as shown in Figure 21 B.

A third NAND logic gate circuit 2106 is formed by connecting one n-channel LI-MOS device 1802 and one conventional n-channel CMOS device 2108 that are in series with two parallel connected conventional p-channel CMOS devices 2110 as shown in Figure 21 C.

Two distinct power supply voltages V_DD and V_ss are respectively used for each of the NAND logic gate circuits 2102, 2104 and 2106 while each of the outputs V_out can be connected to a load (not shown).

Jt will be appreciated by the person skilled in the art that a NOR logic circuit gate can also be similarly formed.

Accordingly, it will be. apparent that various other modifications and adaptations of the invention will be apparent to the person skilled in the art after reading the foregoing disclosure without departing from the spirit and scope of the invention and it is intended that all such modifications and adaptations come within the scope of the appended claims.

Claims

CLAIMS:

1. A semiconductor structure comprising a substrate structure; a gate stack formed on said substrate structure; a drain region of a first dopant type formed in the substrate structure adjacent said gate stack; a source structure formed on said substrate structure adjacent said gate stack, the source structure comprising a source region of a second dopant type and a first region of a dopant concentration below 10¹⁸ cm^"3 disposed between the source region and the substrate structure.

2. The semiconductor structure of claim 1 , wherein said substrate structure is a bulk semiconductor or a semiconductor-on-insulator substrate.

3. The semiconductor structure of claim 2, wherein said bulk semiconductor comprises elemental or compound semiconductors selected from a group comprising silicon, germanium, carbon, gallium arsenide, indium phosphide, and indium antimonide.

4. The semiconductor structure of claim 2, wherein said semiconductor-on- insulatbr substrate comprises at least one semiconductor layer formed on an insulator layer, said semiconductor layer comprising any one or more of a group consisting of silicon, germanium, carbon, or compound semiconductors.

5. The semiconductor structure of claim 2, wherein said semiconductor-on- insulator comprises a plurality of semiconductor layers.

§. The semiconductor structure of claim 5, said plurality of semiconductor layers comprising a silicon-germanium layer formed on a silicon layer and said silicon layer formed on a silicon oxide layer.

7. The semiconductor structure of claim 1 , wherein said gate stack comprises a gate electrode formed on a gate dielectric layer.

8. The semiconductor structure of claim 7, wherein said gate electrode comprises any one or more of a group consisting of polycrystalline silicon, an elemental metal, a metal alloy, a metal nitride, a metal suicide or a metal oxide.

9. The semiconductor structure of claim 7, wherein said gate dielectric layer comprises any one or more of a group consisting of silicon dioxide, hafnium oxide (HfO₂), hafnium oxynitride (HfON), hafnium silicate (HfSiO₄), hafnium silicon oxynitride (HfSiON), lanthanum oxide (La₂O₃) or any dielectric with a permittivity (k) value larger than 6.

10. The semiconductor structure of claim 1 , wherein said source structure comprises elemental, compound semiconductors, Hl-V semiconductors, binary compound semiconductors, ternary compound semiconductors or alloy semiconductors selected from a group comprising silicon, germanium gallium arsenide, indium arsenide, indium aritimoriide, indium phosphide, gallium indium arsenide, gallium indium antimoήide, silicon-germanium, silcon-germanium-earbon, silicon-carbon, and germanium-carbon.

11. The semiconductor structure of claim 1 , wherein said first region comprises elemental, compound semiconductors, Hl-V semiconductors, binary compound semiconductors, ternary compound semiconductors or alloy semiconductors selected from a group comprising silicon, germanium gallium arsenide, indium arsenide, indium antimonide, indium phosphide, gallium indium arsenide, gallium indium antimonide, silicon-germanium, silcon-germaniurri-carbqn, silicon-carbon, and germanium-carbon.,

12. The semiconductor structure of claim 7, further comprising spacers oppositely adjacent said gate electrode.

13. The semiconductor structure of claim 1, wherein said first dopant type is ή-type dopant and said second dopant type is p-type dopant.

14. The semiconductor structure of claim 1, wherein said first dopant type is p-type and said second dopant type is n-type dopant.

15. The semiconductor structure of claim 1, wherein said source region is formed by a combined deposition and in-situ doping.

16. The semiconductor structure of claim 1 , further comprising a second region of said first dopant type formed on said drain region.

17. The semiconductor structure of claim 16, further comprising a conductive metal suicide material formed on said source region and said drain region.

18. The semiconductor structure of claim 1 , wherein said first region is doped with a second, dopant type.

19. The semiconductor structure of claim 18, wherein said first region has a thickness in the range of approximately 1 nm to approximately 100 nm.

20. The semiconductor structure of claim i , wherein said substrate structure comprises a recessed portion, with respect to a surface of the drain region, at an interface between the first region and the substrate structure.

21. The semiconductor structure of claim 20, wherein said substrate structure comprises silicon and said first region comprises silicon, germanium, or both.

22. A method of forming a semiconductor structure comprising the steps of providing a substrate structure; forming a gate stack on the substrate structure; forming a drain region of a first dopant type in said substrate structure adjacent said gate stack; forming a source structure on said substrate structure adjacent said gate stack, the source structure comprising a source region of a second dopant type and a first region of a dopant concentration below 10¹⁸ cm^"3 disposed between the source region and the substrate structure.

23. The method of claim 22, further comprising the step of forming spacers adjacent said gate stack.

24. The method of claim 22, wherein the step of forming said gate stack further comprises the steps of forming a gate dielectric layer; and forming a gate electrode.

25. The method of claim 24, further comprising the step of forming a hardmask on the gate electrode, the hardmask comprising a dielectric material.

26. The method of claim 22, wherein the step of forming said source structure comprises a selective epitaxy step.

27. The method of claim 26, wherein said selective epitaxy step further comprises in-situ doping.

28. The method of claim 26, wherein said selective epitaxy step comprises utilising any one or more of a group consisting of silane, disilane, methyl-silane, germane, and chlorine.

29. The method of claim 22, further comprising the step of etching said substrate structure prior to forming said source structure.

30. The method of claim 22, wherein said substrate structure and the source structure comprise any one or more of a group consisting of silicon, germanium, carbon or compound semiconductors.

31. The method of claim 22, further comprising the steps of forming a conductive material over said source region and said drain region; depositing an insulating layer above said conductive material; and forming contacts to said source region, said drain region, and. said gate stack.

32. The method of claim 22, wherein the steps of forming said drain region and said source structure comprise an ion implantation step.

33. The method of claim 22, wherein said first dopant type is n-type and said second dopant type is p-type.

34. The method of claim 22, wherein said first dopant type is p-type and said second dopant type is n-type.

35. An inverter comprising a first transistor comprising a gate electrode; a drain region of a first dopant type; and a source region of a first dopant type, said first transistor source region connected to a first power supply and said first transistor drain region connected to an output terminal; a second transistor comprising a substrate structure; a gate stack formed on said second transistor substrate structure; said second transistor gate stack further comprising a gate electrode; a drain region of a second dopant type formed in said second transistor substrate structure adjacent said second transistor gate stack; and a source structure formed on said second transistor substrate structure adjacent said. second transistor gate stack, said second transistor source structure comprising a source region, of a first dopant type and a first region of a dopant concentration below 10¹⁸Cm^"3 disposed between said second transistor source region and said second transistor substrate structure, said second transistor source region connected to a second power supply and said second transistor drain region connected to said output terminal; and an input terminal connected to the gate electrodes of said first and second transistors.

36. The inverter of claim 35, wherein said first dopant type is p-type dopant, and said second dopant type is n-type dopant.

37. The inverter of claim 35, wherein said first dopant type is π-type dopant, and said second dopant type is p-type dopant. -

38. An inverter comprising a first transistor comprising a substrate structure; a gate stack formed on said first transistor substrate, structure; said first transistor gate stack further comprising a gate electrode; a drain region of a first dopant type formed in said first transistor substrate structure adjacent said first transistor gate stack; and a source structure formed on said first transistor substrate structure adjacent said first transistor gate stack, said first transistor source structure comprising a source region of a second dopant type and a first region of a dopant concentration below 10¹⁸Cm^"3 disposed between said first transistor source region and said first transistor substrate structure, said first transistor source region connected to a first power supply and said first transistor drain region connected to an output terminal; a second transistor comprising a substrate structure; a gate stack formed on said second transistor substrate structure; said second transistor gate stack further comprising a gate electrode; a drain region of a second dopant type formed in said second transistor substrate structure adjacent said second transistor gate stack; and a source structure formed on said second transistor substrate structure adjacent said second transistor gate stack, said second transistor source structure comprising a source region of a first dopant type and a first region of a dopant concentration below IO^crrf³ disposed between said second transistor source region and said second transistor substrate structure, said second transistor source region connected to a second power supply and said second transistor drain region connected to said output terminal; and an input terminal connected to the gate electrodes of said first and second transistors.

39. The inverter of claim 38, wherein said first dopant type is p-type dopant, and said second dopant type is n-type dopant.

40. The inverter of claim 39, wherein said first dopant type is n-type dopant, and said second dopant type is p-type dopant.

41. An integrated circuit chip comprising a plurality of first transistors, each first transistor comprising a first gate electrode; a first drain of a first dopant type, and a first source of a first dopant type; and a plurality of second transistors, each second transistor comprising a substrate structure; a gate stack formed on said second transistor substrate structure; said second transistor gate stack further comprising a gate electrode; a drain region of a second dopant type formed in said second transistor substrate structure adjacent said second transistor gate stack; and a source structure formed on said second transistor substrate structure adjacent said second transistor gate stack, said second transistor source structure comprising a source region of a first dopant type and a first region of a dopant concentration below 10^t8 cm^"3 disposed between said second transistor source region and said second transistor substrate structure.

42. The integrated circuit chip of claim 41 , wherein the first dopant type is p-type dopant, and said second dopant type is n-type dopant.

43. The integrated circuit chip of claim 41, wherein the first dopant type is n-type dopant, and said second dopant type is p-type dopant.

44. An integrated circuit chip comprising a plurality of first transistors, each first transistor comprising a substrate structure; a gate stack formed on said first transistor substrate structure; said first transistor gate stack further comprising a gate electrode; a drain region of a second dopant type formed in said first transistor substrate structure adjacent said first transistor gate stack; and a source structure formed on said first transistor substrate structure adjacent said first transistor gate stack, said first transistor source structure comprising a source region of a first dopant type and a first region of a dopant concentration below 10¹⁸ cm^"3 disposed between said first, transistor source region and said first transistor substrate structure; and a plurality of second transistors, each second transistor comprising a substrate structure; a gate stack formed on said second transistor substrate structure; said second transistor gate stack further comprising a gate electrode; a drain region of a first dopant type formed in said second transistor substrate structure adjacent said second transistor gate stack; and a source structure formed on said second transistor substrate structure adjacent said second transistor gate stack, said second transistor source structure comprising a source region of a second dopant type and a first region of a dopant concentration below 10¹⁸ cm^"3 disposed between said second transistor source region and said second transistor substrate structure.