WO2007093172A2 - Integrated circuit arrangement and method for determining the parasitic non-reactive resistance of at least the lead of at least one memory cell of an integrated circuit arrangement - Google Patents

Abstract

An integrated circuit arrangement (300) has at least one electronic component (302), and also at least one resistance determining circuit that is coupled to the electronic component and is monolithically integrated with the latter and serves for determining the parasitic non-reactive resistance (303) of at least the lead to the at least one electronic component.

Description

Integrated circuit arrangement and method for determining the parasitic ohmic resistance of at least the supply line of at least one memory cell of an integrated circuit arrangement.

The invention relates to an integrated circuit arrangement and a method for determining the parasitic ohmic resistance of at least the supply line of at least one

Memory cell of an integrated circuit arrangement.

In the manufacture of semiconductor chips, for example of semiconductor memory chips, for example dynamic random access memory (DRAM) chips, technology-related variations of device properties occur, as well as variations in the values of parasitic elements such as lead resistance, in other words the resistance of leads to the Memory cells, in a DRAM, for example, the

Capacitance to the capacitor of a respective memory cell, the stray capacitance, etc. The variations of the device characteristics are completely specified for a given manufacturing process and may be taken into account in the circuit design.

For the parasitic elements there is usually no comprehensive electrical characterization. Although, for example, sheet resistances are characterized by metallization levels, also referred to as metal levels, certain parasitic lead resistances are not. If the functional behavior of integrated circuits is critically determined by such parasitic lead resistances, an electrical characterization of the latter for process control is very helpful or even indispensable. The electrical characterization of parasitic lead resistances is generally not trivial because often the leads are not separately electrically accessible and can only be measured together with other elements. Such a situation is given for example with a parasitic ohmic resistance as access to a capacitor. This case occurs, for example, at the gate of a MOS field effect transistor (MOS) or in the DRAM memory cell.

A generalized representation of the above-mentioned topic is shown in Fig.l.

Fig.l shows in an arrangement 100, a chip-external

Measuring device 101 and an integrated circuit _arrangement, integrated circuit (IC) 102. The measuring device 101 is connected by a cable 103 with a bonding connection pad 104 of the integrated circuit arrangement 102nd

For reasons of simpler representation, only one memory cell 105 of a memory cell array having a multiplicity of memory cells arranged in rows and columns is shown in FIG.

The dynamic memory cell 105, in other words the memory cell of a dynamic random access memory (DRAM) has a storage capacitor 106 and a parasitic resistor Rparasitic 107 of the supply line to the

Storage capacitor 106 on. The supply line contains the ohmic resistance of the leading to the storage capacitor 106 supply line and optionally, if in the memory cell 105 for reasons of simplification not shown here selection transistor is provided, for example, the channel resistance of the respective selection transistor. Furthermore, symbolized in FIG. 1 are the terminal pad capacitance 108, the capacitance of the feeding track 109 and the ohmic resistance 110 of the feeding track.

In other words, integrated in the integrated circuit arrangement 102 is a component to be tested (in other words the "Device Under Test", DUT), which consists of a capacitor 106 with a parasitic lead resistance 107 which is to be determined Supply lines to the memory cell 105 as well as the interface via the bonding pad 104 cause further capacitances and ohmic resistances.

The external measuring device 101 shown symbolically in FIG. 1 serves to determine the parasitic ohmic supply resistance Rparasitic

The measurement of such an RC arrangement can generally take place in the time domain or in the frequency domain. The metrological problem scales in this case with the inverse size of the RC constant of the DUT 105.

In the case of the measurement with an off-chip measuring device 101 shown in FIG. 1, the extraction of the parasitic resistive lead resistance rparasitic of interest is very critically dependent on the exact knowledge of all other components and thus often only very imprecisely possible.

For a very small RC constant of the DUT 105, the behavior of the integrated circuit device 102 is dominated by the remaining elements and the influence of the DUT 105 can no longer be resolved, ie, detected. In special cases, so-called impedance analyzers can be used to determine the parasitic resistive lead resistance of the DUT 105. However, in this case too, the effects or restrictions described above arise.

For example, it has not been possible with impedance analyzers to determine the parasitic ohmic lead resistances in a DRAM memory cell.

According to an embodiment of the invention, an integrated circuit arrangement is provided which ^■ at least one electronic component, such as a memory cell has. Furthermore, the integrated

Circuit arrangement at least one coupled to the electronic component and with this monolithically integrated resistance-determining circuit for determining the parasitic resistance of at least the supply line to the at least one electronic component.

According to another exemplary embodiment of the invention, in a method for determining the parasitic ohmic resistance of at least the supply line to at least one electronic component of an integrated circuit arrangement, electrical quantities which characterize the at least one electronic component are detected on-chip. Using the detected electrical quantities, the parasitic resistance is determined on-chip.

Thus, illustratively according to an embodiment of the invention, an on-chip integrated measuring circuit is provided for measuring and determining the parasitic ohmic resistance of at least the supply line to at least one electronic component, for example one

Memory cell, in an integrated circuit arrangement. Due to the physical proximity of the circuit, in other words the monolithically integrated resistance detection circuit, to the Device Under Test, in other words the electronic component, for example the memory cell, the additional resistances and capacitances shown in FIG. 1 and described above are avoided ,

Exemplary embodiments of the invention will become apparent from the dependent claims.

In the circuit arrangement may be provided in this monolithically integrated detection circuit for detecting electrical quantities which characterize the at least one electronic component.

In the circuit arrangement may further be provided in this monolithically integrated drive unit for driving the at least one electronic component during the detection of the parasitic ohmic resistance of at least the supply line to the at least one electronic component.

The at least one electronic component can be set up as a memory cell. Furthermore, according to an exemplary embodiment of the invention, the at least one electronic component may have at least one capacitor. In other embodiments of the invention, the electronic component may additionally comprise further components, for example a capacitor selection transistor, in the case of the configuration of the electronic component as memory cell, for example as dynamic random access memory cell, a selection transistor for selecting the capacitor with regard to charging or unloading the same with or from electrical charge carriers. According to the case that the electronic component still contains additional elements, such as a select transistor, it is provided, for example, that the parasitic resistance of the series connection of the supply line to the capacitor and the elements which in addition to the capacitor in the electronic components is detected, for example, the parasitic resistance of the channel region and the source region or the drain region of the select transistor when it is made in MOS technology, is determined.

The at least one electronic component can have at least one capacitor for storing electrical charge carriers and therefore optionally for storing information, for example binary information.

According to one exemplary embodiment of the invention, the at least one electronic component has a component selection unit for selecting the at least one electronic component, for example one

Memory cell selecting unit for selecting the at least one memory cell. The component selecting unit may be formed by at least one component selecting transistor, for example, a memory cell selecting transistor.

The at least one memory cell is a dynamic random access memory cell in accordance with an embodiment of the invention.

According to a further embodiment of the invention, the drive unit is set up to control the charging or discharging of the electronic component with or from electrical charge carriers, for example electrons.

The drive unit may further be configured such that the at least one capacitor in a first Actuating phase is substantially fully charged, is partially discharged in a second drive phase and finally discharged in a third drive phase substantially completely.

In this case, the driving unit may be arranged such that the three driving phases are repeated, e.g. periodically.

The drive unit may be configured as a delay locked loop (DLL) circuit, a phase locked loop (PLL) circuit or a ring oscillator circuit, alternatively as any other type of circuit providing the functionality required.

The detection circuit may be configured to detect at least one of the following electrical quantities:

The discharge current of the at least one electronic component, for example the discharge current of the at least one capacitor, and / or

• The voltage applied to the at least one electrical component voltage, for example, applied to the at least one capacitor voltage.

The resistance detection circuit may be configured to detect the parasitic resistance of at least the lead using the electrical quantities detected by the detection circuit.

Furthermore, the resistance-determining circuit may be configured to determine the parasitic ohmic resistance of at least the supply line using formed time averages of the electrical quantities detected during the charging and discharging of the at least one electronic component, for example the capacitor of a memory cell. Thus, according to an embodiment of the invention by means of a monolithically integrated measuring circuit, a time-precise control of charging operations and discharges of electric charge carriers to the electronic component, in other words on the "Device Under Test" (DUT), are made possible. From relatively simple to be measured time averages of analog electrical variables, such as the discharge current or the voltage at the electronic component, such as the

Capacitor of a memory cell, according to an embodiment of the invention, the parasitic lead resistance can be determined to a capacitance, in other words to the capacitor.

The resistance-determining circuit may be arranged such that the parasitic resistance is determined according to the following rule:

being with

R is the parasitic resistance of the supply line inside the DUT to the capacitor, N is the number of time slots of the charge carried out and discharging of the capacitor,

Ii is the time average of the charging current during the first activation phase,

I3 the time average of the discharge current during the third drive phase,

• V] _ a voltage provided for charging the capacitor, is called. According to one exemplary embodiment of the invention, an output amplifier is additionally provided which is coupled on the input side to the at least one electronic component, for example the capacitor, and which provides an amplifier output voltage on the output side.

According to this embodiment of the invention, the resistance-determining circuit may be arranged such that the parasitic resistance is determined according to the following rule:

R - ^{X λ Vl} l ^Δv ouτJ

where, with R, the parasitic resistance of the supply line within the DUT to the capacitor,

N is the number of time slots of charging and discharging the capacitor,

Ii is the time average of the charging current during the first activation phase,

Vi a voltage provided for charging the capacitor,

• ΔVouT is the amplifier output voltage.

According to another embodiment of the invention array circuit is additionally provided a monolithically integrated in the circuit arrangement unit for compensating for temporal disparities different time slots in the integrated, hereinafter also referred to as ^■ dynamic element matching unit.

According to another embodiment of the invention, it is provided that the drive unit is set up such that the at least one capacitor in a charging Activation phase is charged and discharged in a discharge Ansteuerphase.

According to this embodiment of the invention, the drive unit may comprise an oscillation measurement circuit, wherein the oscillation measurement circuit is arranged such that

In the charge-drive phase, the capacitor is charged until a charging threshold is reached,

Upon the charge threshold being reached, the drive unit is switched to the discharge drive phase, so that the capacitor is discharged; in the discharge drive phase, the capacitor is discharged until a discharge threshold is reached;

• When the discharge threshold is reached, the drive unit is switched to the charge drive phase so that the capacitor is charged.

According to this embodiment of the invention, an integrated circuit is therefore clearly ^{Oszillationsmess'} is provided. From the relatively simple and robust to be measured oscillator frequency of Oszillationsmess circuit according to this embodiment of the invention, the parasitic ohmic supply resistance is determined to a capacitor.

In other words, in one embodiment of the

Invention provided that as a measuring circuit in the circuit arrangement, a monolithically integrated free-running oscillator is provided, the frequency of which is dependent on the parasitic ohmic supply resistance to be determined. The resulting oscillator frequency together with predetermined analog electrical quantities, such as corresponding currents or voltages, enables and forms the basis for the determination of the parasitic resistive supply resistance.

For the measurement of the oscillator frequency different possibilities are given. The oscillator frequency can be direct, in or on the chip, i. previously divided in the integrated circuit arrangement, determined with an external measuring device. Furthermore, the oscillator frequency can be used to drive an on-chip counter circuit. When specifying a chip-internal or chip-external time base results in the oscillator frequency by simply reading a digital information (bit sequence).

This solution has, for example, the following effects: The on-chip integrated measuring circuit avoids unwanted parasitic electrical elements.

• With regard to the characterization of the DUT with a certain RC constant, this procedure is limited only by internal time constants of the integrated measuring circuit and is therefore suitable, for example, for small values of the RC constant.

• The measurement effort is low and the process is very robust, since it is only necessary, for example, to read out digital information.

The oscillation measurement circuit according to an embodiment of the invention comprises a Schmitt trigger whose first threshold is the charge threshold and whose second threshold is the discharge threshold.

Furthermore, the drive unit can have:

A first current source for providing a charging current for charging the capacitor, wherein the first current source can be realized, for example, by means of a current source transistor,

A second current source for providing a discharge current for discharging the capacitor, wherein the second current source can be realized for example by means of a second current source transistor,

At least one switch for selectively coupling the first power source or the second power source to the capacitor,

Wherein the at least one switch is coupled to the output of the Schmitt trigger such that it couples the first current source or the second current source to the capacitor depending on the output signal of the Schmitt trigger.

The charging threshold may be a first reference voltage and the discharging threshold may be a second reference voltage.

Furthermore, the resistance detecting circuit may be configured such that the parasitic resistance is detected by using the oscillation frequency of the oscillation measuring circuit.

Furthermore, the resistance-determining circuit may be arranged such that the parasitic resistance is determined according to the following rule:

R = ^{ΛU 2} f • C _τ

being with

R is the parasitic resistance of the supply line within the DUT to the capacitor, Δu is the difference between the first reference voltage and the second reference voltage,

I the charging current for charging the capacitor,

• f is the oscillation frequency of the oscillation measurement circuit, • Cf is the capacitance of the capacitor. Furthermore, in the integrated circuit arrangement according to an exemplary embodiment of the invention, at least one reference component, for example at least one reference capacitor, may be provided, wherein the

Drive unit may be configured such that the at least one electronic component and, for example, the capacitor and the at least one reference component, for example, the at least one reference capacitor, are charged with the same voltage or with two voltages clearly correlated with each other.

In this context, the expression "two voltages which are clearly correlated with one another" means that the ratio of the two voltages used is known to one another, so that due to the respectively known ratio, the respective different charging processes or discharging processes can be clearly concluded.

The integrated circuit arrangement further has, according to an embodiment of the invention, at least one latch capacitor coupled to the capacitor and at least one reference latch capacitor coupled to the reference capacitor.

According to this embodiment, the drive unit further comprises:

A first switch connected between a first voltage source and the capacitor, a second switch connected between the first

Voltage source and the capacitor is connected or which is connected between a second voltage source and the capacitor,

A third switch connected between the capacitor and the latch capacitor, • a fourth switch connected between the reference capacitor and the reference buffer capacitor.

The drive unit is configured according to this embodiment of the invention such that

In a first phase the first switch and the second switch are closed and the third switch and the fourth switch are opened, and in a second phase the first switch and the second switch are opened and the third switch and the fourth switch are closed ,

According to another embodiment of the invention ^', the integrated circuit arrangement further comprises a fifth

Switch on, which is connected between the reference capacitor and a reference potential and a sixth switch, which is connected between the reference intermediate switch capacitor and the reference potential.

The fifth switch and the sixth switch thus clearly each form a unit by means of which it is possible, the reference capacitor to a unique potential, the reference potential, for example, the ground potential to discharge or charge before the potential of the

Condenser and the reference capacitor are transferred to the latch capacitor or the reference latch capacitor.

Thus, it can be provided that the drive unit is set up in such a way that the fifth switch and the sixth switch are closed in a first phase (in this phase the latch capacitor and reference latch capacitor are discharged or charged to the reference potential, for example ), and in the second phase the fifth switch and the sixth switch are open (in this phase, for example, the potential which is applied to the capacitor or to the reference capacitor, at least partially transferred to the latch capacitor or to the reference latch capacitor.

According to an embodiment of the invention, it is provided that the resistance-determining circuit is adapted to determine the parasitic resistance of at least the supply line by using the time difference of a charging process of electrical charges of the at least one electronic component, for example the capacitor, and a reloading of electrical charges at least one reference component, for example the at least one reference capacitor.

Thus, according to an exemplary embodiment of the invention, the measurement of the time difference of transhipment processes between a component to be tested, the electronic component (Device Under Test, DUT), for example a DRAM memory cell, and a known reference structure can be measured.

According to another embodiment of the invention, the integrated circuit arrangement further comprises a comparator whose first input is coupled to the electronic component and whose second input is coupled to a third voltage source. Furthermore, a reference comparator is provided, whose first input is coupled to the reference component and whose second input is coupled to the third voltage source or to a fourth voltage source. The resistance detection circuit according to this embodiment is arranged to detect the parasitic ohmic resistance of the lead using the temporal

Difference of the switching of the comparator and the reference comparator. Furthermore, a first signal propagation path can be provided in the integrated circuit arrangement, for example downstream of the comparator, with at least one first signal propagation delay element. Furthermore, a second signal propagation path, for example downstream of the reference comparator, may be provided with at least one second signal propagation delay element. The at least one second signal propagation delay element can be set up such that its signal propagation delay is greater than that of the at least one first signal propagation delay element.

Furthermore, according to one embodiment of the invention, the first signal propagation path has a plurality of series-connected first signal propagation delay elements, wherein one or more first signal propagation delay elements are grouped into a first signal propagation delay stage. The second

Signal propagation path may include a plurality of serially connected second signal propagation delay elements, wherein one or more second signal propagation delay elements are grouped into second signal propagation delay stages.

Between the output of the comparator and the output of the reference comparator, a bistable flip-flop, such as a flip-flop, be connected.

Furthermore, between the output of at least a part of the first signal propagation delay stages and a corresponding second signal propagation delay stage, in each case a bistable multivibrator can be connected. The at least one first signal propagation delay element may be formed by at least one first inverter, and the at least one second signal propagation delay element may be formed by at least one second inverter.

Furthermore, the resistance-determining circuit may be arranged to determine the parasitic resistance of the lead using the outputs of the bistable flip-flops.

According to an embodiment of the invention, the integrated circuit arrangement may comprise a first reference structure having signal propagation delays whose signal propagation delay is equal to that of the first signal propagation delay elements. Furthermore, a second reference structure may be provided which has signal propagation delay elements whose signal propagation delay is equal to that of the second signal propagation delay elements.

According to another embodiment of the invention, the first reference structure has a first ring oscillator with the signal propagation delay elements and the second

Reference structure comprises a second ring oscillator with the second signal propagation delay elements.

Furthermore, the resistance-determining circuit may be arranged such that the parasitic resistance is determined according to the following rule:

_R = ^N f2 -% k • C _τ • In 3 Z ₁ • f ₂

being with

R the parasitic resistance of the supply line, N is the number of the signal propagation delay stage at which the state of the associated bistable multivibrator changes compared to the bistable multivibrator immediately preceding it, k the number of signal propagation delays in the first reference structure, the number of signal propagation delay elements in the first reference structure and the number of signal propagation delay elements in the second reference structure is the same,

• f] _ the frequency of the first ring oscillator,

• ± 2 & i- ^e frequency of the second ring oscillator,

• CT is the capacitance of the capacitor.

Embodiments of the invention are illustrated in the figures and are explained in more detail below.

Show it

Figure 1 is a plan view of a circuit arrangement;

Figure 2 is a plan view of a monolithic integrated

Circuit arrangement according to an embodiment of the invention;

Figure 3 is a detailed illustration of a monolithic integrated circuit arrangement according to an embodiment of the invention;

Figures 4A and 4B is an illustration of a charge and discharge cycle for the device under test of the circuit arrangement of Figure 3 (Figure 4A) and the corresponding drive signals for the switches provided in the circuit arrangement of Figure 3 (Figure 4B ); Figure 5 is a detailed illustration of a monolithic integrated circuit arrangement according to another embodiment of the invention;

Figure 6 is a detailed illustration of a monolithic integrated circuit arrangement according to another embodiment of the invention;

Figure 7 is a detailed illustration of the voltage source circuit of the circuit arrangement of Figure 6;

Figure 8 is a diagram in which the time course of

Bit line voltage is shown;

Figure 9 is a diagram in which the time course of

Output voltage of the Schmitt trigger circuit of the circuit arrangement shown in Figure 6 is shown;

Figure 10 is a diagram in which the accuracy of

Resistance determination of the circuit arrangement shown in Figure 6 as a function of the oscillation frequency f and the determination of the capacitance C _{τ of} the capacitor is shown;

Figure 11 is a diagram in which the accuracy of

Resistance determination of the circuit arrangement shown in Figure 6 as a function of the current value I and the determination of the capacitance C _{τ of} the capacitor is shown; and

Figure 12 is a detailed illustration of a monolithic integrated circuit arrangement according to another embodiment of the invention. 2 shows a plan view of a monolithic integrated circuit arrangement 200 according to the exemplary embodiments of the invention.

The basic structure of the monolithic integrated circuit arrangement 200 according to the exemplary embodiments of the invention described below is continuous, as shown in FIG.

The circuit arrangement 200 has one or a plurality of chip-external connection pads 201, wherein the connection pad 201 is connected by means of one or more electrically conductive tracks 202 to an electronic component 203 to be tested. The electrical component may be any electrical component on or in a wafer, generally in an integrated circuit.

According to the following embodiments, it is believed that the electronic component 203 to be tested has a capacitor 204, such as a capacitor of a memory cell, such as a dynamic random access memory (DRAM) memory cell, without limitation of algo- rality.

In an alternative embodiment of the invention, the electronic component 203 is a transistor, wherein, for example, the gate terminal of the transistor is connected by means of a feed line 205 with the electrically conductive conductor 202, for example made of aluminum or copper.

The electronic component 204 is coupled by means of a feed line 205, for example additionally by means of a switched in the supply selection transistor (select transistor), with the electrically conductive conductor 202, wherein the supply line is made of polysilicon, for example.

The supply line 205 has a parasitic ohmic resistance R, which is to be determined by means of the monolithic integrated circuits described below.

It should be noted in this context that in an alternative embodiment of the invention, any number of electronic components whose parasitic ohmic lead resistances, for example, the respective supply to the metallic electrically conductive tracks 202 are to be determined, may be provided in the integrated circuit arrangement 200 can, for example, a plurality of thousands or millions, for example, in a memory array, provided memory cells, each of which is formed by a respective capacitor and a capacitor upstream of the respective selection transistor, in each case, the parasitic ohmic supply resistance of the supply line between the capacitor 204 and the electrically conductive trace 202 of aluminum or copper to determine.

Also monolithically integrated in the circuit arrangement 200 is a detection circuit 206 which is coupled to the conductor track 202 and which detects electrical quantities which characterize, for example, the electronic component 204 and / or the parasitic ohmic lead resistance 205.

A likewise monolithically integrated in the circuit arrangement 200 drive unit 207 is used to drive the electronic component 204 and optionally additionally provided in the circuit arrangement provided power sources or voltage sources (not shown in Figure 2 for the sake of a simplified and comprehensible representation). 3 shows a detailed illustration of a monolithic integrated circuit arrangement 300 according to an embodiment of the invention.

In the following, it is assumed without restriction of generality that the parasitic ohmic feed line resistance is the parasitic ohmic trench resistor (trench resistor) of a DRAM memory cell as electronic component 301.

The integrated circuit assembly 300 has the following components monolithically integrated therein:

An electronic component 301, which is a capacitor

302 and a parasitic ohmic supply resistance 303, which is to be determined.

Furthermore, the capacitor 302 is coupled by means of the lead to a node 304, which is coupled to a first input 305 of a first switch SWi 306, the second terminal 307 is coupled to a first current detection circuit 308 for detecting a first current Iχ, which in The following will be explained in more detail. In series with the current detection circuit 308 is a voltage source 309 which provides an electrical voltage Vi.

Furthermore, the node 304 is coupled to a first terminal 310 of a second switch SW2 311, whose second terminal 312 is coupled to the ground potential.

Furthermore, the node 304 is coupled to a first terminal 313 of a third switch SW3 314 whose second terminal 315 is coupled to a second current detection circuit 316 for measuring a third current I3. The second Current sense circuit 316 is further coupled to the ground potential.

Furthermore, three RS flip-flops 317, 318, 319 are provided in the circuit arrangement 300, wherein the output 320 of a first RS flip-flop 317 is coupled to the control input 321 of the first switch SW] _ 306 and this controls. The second RS flip-flop 318 is coupled at its output 322 to the control input 323 of the second switch SW2 311 and controls this by means of the output signal of the second RS flip-flop 318th

The output 324 of the third RS flip-flop 319 is coupled to the control input 325 of the third switch SW3 314 and controls this, in other words opens this or

■ closes this depending on the value of the output signal of the third RS flip-flop 319.

The inputs of the RS flip-flops 317, 318, 319 are optionally coupled to an intermediate Dynamic Element Matching unit 326 with outputs of a Delay Locked Loop circuit 327, such that the reset input 329 of the first RS flip-flop 327 Flops 317 is timed after the set input 328 of the first RS flip-flop 217 from the delay locked loop circuit 327 with a high level (DLL) signal.

Furthermore, the control of the RS flip-flops 317, 318, 319 by means of the DLL circuit 327 such that • the set input 330 of the second RS flip-flop 318 is driven with a high-level signal, after the 'Reset input 329 of the first RS flip-flop 317 was driven;

• the reset input 331 of the second RS flip-flop 318 timed after the set input 330 of the second RS flip-flop 318. Further, the set input 332 of the third RS flip-flop 319 is timed to the reset input 331 of the second RS flip-flop 318 with a high-level signal, and finally, in a respective cycle, the reset input 333 of the third RS flip-flop 319 timed after the set input 332 of the third RS flip-flop 319 with a high-level signal. In this way, it is ensured that, as will be explained in more detail below, the switches 306, 311, 314 are closed successively in a non-overlapping manner, so that a defined

Charging operation of the capacitor 302 and one in two separate partial discharging operations in accordance with the control by means of the switches 306, 311, 314 is achieved.

As an alternative to the DLL circuit 327, a phase-locked loop circuit (PLL circuit) or a ring oscillator circuit, for example with a plurality of series-connected inverters, may be provided for providing the corresponding drive signals.

The electronic component, according to this embodiment of the invention, a DRAM memory cell 301 is connected to the voltage source 309 by means of the first switch SWi 306 when it is closed, and thus charged.

Substantially after the completion of the charging process, the DUT 301 is discharged in two non-overlapping partial discharge processes, such that first (in a first partial discharge phase) via the then closed second switch SW2 311, the charge carriers stored on the capacitor 302 partially drain as a second current flow I2 and in a second partial discharge phase, when the second switch SW2 311 is opened and the third switch SW3 314 is closed, by means of the third switch SW3 314 is substantially completely discharged, wherein a third current I3 flows and is detected by the second current measuring circuit 316.

The precise timing of the switch states of the switches 306, 311, 314 is enabled by means of the RS flip-flops 317, 318, 319 driven by the DLL circuit 327.

As an alternative to the holding elements shown as RS flip-flops 317, 318, 319, it is also possible to provide only logic that guarantees the corresponding time delay and time control with corresponding logic gates. To simplify the representation of the control, the charging process 401 and the two discharging processes, a first partial discharging process 402 and a second partial discharging process 403 are shown in a time diagram 400 in FIG. 4A.

By means of the DLL circuit 327, the pulse duration for the respective switches 306, 311, 314 is derived. If a ring oscillator circuit is used instead of the DLL circuit 327, for example when using a 70 nm process technology, a time delay of 1 ns can be achieved with a series connection of six inverters.

The cycle consisting of the charging process 401 and the two partial discharging processes 402, 403, which as a whole require a period of time T, is carried out repeatedly and thus repeats with a frequency f which corresponds to the period T, i. the total duration, which results from the duration of the charging process 401 and the two partial discharging operations 402, 403.

In the first half period T / 2, the first switch SWi ^{306 is} active, in other words, closed (cf.

Switch aging diagram 450 in FIG. 4B) corresponding to the first switch control signal 451 for the first switch SWi 306, which corresponds to the output signal of the first RS flip-flop 317. The first switch driving signal 451 is at the low level until the beginning of the charging operation 401 (thus, the first switch SWi 306 is opened), changing at the beginning of the

T charging process 401 (time) to high level (which the first switch SWi 306 is closed) and returns to the low level (time "0") upon completion of the charging process, with the first switch SWi 306 is opened again. During the charging process 401, according to the supplied voltage Vi, a first flows

Current Ii (shown in Figure 4A as a time course I (t), measured as average Ii) to the capacitor 302 and loads it. This is shown in Figure 4A with a capacitor charging curve 404. During the entire discharge process 402, 403, the first switch SWi ³⁰⁶ remains open.

Upon completion of the charging operation during which the capacitor 302 is substantially fully charged, the second switch SW2 311 opened during the charging process 401 is closed (time "0") (see second switch driving signal 452 in Fig. 4B) ) and remains closed for the duration of a time slot whose duration is defined according to T / N, where N is the number of time slots during the period T, whereby during the first partial discharge phase 402 via the second switch SW2 311 a first Part discharge current I2 (in Fig.4A shown as a time course I (t), measured as the average I2) flows.

During the second partial discharging process 402, the first switch SWi 306 and the third switch SW3 314 are opened.

FIG. 4A shows the partial discharge during the first partial discharge process 402 in a first partial discharge curve 405. After completion of the first partial discharging process 402 (time T / N), the second switch SW2 311 is re-opened according to the second switch driving signal 452 corresponding to the output signal of the second RS flip-flop 318.

Subsequently, the third switch SW3 314 is closed by means of the third switch drive signal 453, in that the third switch drive signal 453, which previously had a low level during the charging process 401 and the first partial discharge process 402, rises to high level and thus the third switch SW3 314 closes (time T / N). During the second partial discharging process 403, the residual charge still remaining on the capacitor 302 discharges through the third switch SW3 314 and the second measuring circuit 316 to the ground potential, whereby a third current I3 (shown in FIG. 4A as time characteristic I (t ), measured as rπ

Mean value I3) flows (until a time - at which the

2 third switches SW3 314 is reopened). The discharge is shown in FIG. 3 for the second partial discharge operation 403 in a second partial discharge curve 406.

In other words, in the first half cycle T / 2, the first switch SWi ^{306 is} active and the DUT 301 is charged, with an exponentially decaying first current Ii flowing. In the second half period, the DUT 301 is discharged. An exponential discharge current with the opposite sign, but for example the same amount, flows. The discharge current first flows in the first partial discharge phase 402 via the second switch SW2 411 and then, in the second partial discharge phase 403, via the third switch SW3 314.

In the following, the time average values of the currents Iχ (charge current), 12 (discharge current Tei 1) and I3 (discharge current part 2), which are related to the period T, are calculated. With

I = I ₀ • e RC (D

being with

• R is the parasitic resistive line resistance to be determined, and

• C is the capacitance of the capacitor,

surrendered

(2)

Vi Using I _Q = - ^ - and T »2 • RC it follows:

Il «- • V ₁ • C = f • V ₁ • C, (3)

The first part of the discharge current results to

I ₂ = f -V ₁ 1 -e RC

(4)

in which

1 1 τ = - • -. (5; f N The second part of the discharge current results from the difference of the currents in equations (3) and (4) according to the following rule:

I3 = f • V ₁ • C • e RC (6)

The combination of equations (3) and (6) provides an expression for the parasitic resistive line resistance R to be determined in the DUT 301:

According to this embodiment of the invention, the specification of the voltage Vi and the measurement of the current values Ii and I3 is thus required.

A parameter analyzer, for example the company Agilent, can be used, for example, to determine the above-mentioned current values. The accuracy of the method is then determined by the precision of the time base generated by DLL circuit 327.

It follows:

N

The accuracy of the time base and thus the determination of the parasitic ohmic supply resistance can, as is schematically indicated in FIG. 3, be improved with an optional "Dynamic Element Matching", wherein by means of the Dynamic Element Matching unit 326 any existing inequalities of the time slots, which under the Charging process and the unloading process are to be timed out.

5 shows an integrated circuit arrangement 500 according to another embodiment of the invention.

The elements identical or similar to the circuit arrangement 300 according to FIG. 3 are given the same reference numerals in FIG. 5 as in FIG.

In addition to the elements provided in the circuit arrangement according to FIG. 3, the circuit arrangement 500 according to FIG. 5 has a fourth switch SW4 501, a fifth switch SW5 502 and a sixth switch SWg 503. Furthermore, a selection logic, in other words a selection circuit 504 is provided, which is coupled to

The control terminal 505 of the fourth switch SW4 501,

• the control terminal 506 of the fifth switch SW5 502, as well

• with the control connection 507 of the sixth switch SW ₆ 503.

The select logic 504 thus controls the switching behavior of the following switches:

The fourth switch SW4 501,

The fifth switch SW5 502, and

• the sixth switch SWg 503.

A first terminal 508 of the fourth switch SW4 501 is coupled to ^'the second terminal 313 of the third switch SW3 314th The second terminal 509 of the fourth switch SW4 505 is coupled to the node 304. Clearly, the fourth switch SW4 501 is thus connected between the third switch SW3 314 and the node 304. Furthermore, the first terminal 510 of the fifth switch SW5 502 is coupled to the node 304, and the second terminal 511 of the fifth switch SW5 502 is coupled to an input 512 of a buffer amplifier 513 to the output 514 of which an output voltage ΔVOUT is provided. Furthermore, with the second terminal 511 of the fifth switch SW5 502, the second terminal 515 of the sixth switch SWg 503 is coupled, the first terminal 516 of which is connected to the ground potential.

Furthermore, a buffer capacitor 517, which is additionally coupled to the ground potential, is coupled to the second terminal 511 of the fifth switch SW5 502 and to the input 512 of the buffer amplifier 513.

The charging operations and the (partial) discharging operations controlled by the switches SWi 306, SW2 311 and SW3 314 are the same as those explained above in connection with the circuit arrangement 300 of Fig. 3 and Figs. 4A and 4B were. The switches SW4 501, SW5 502 and SWg 503 driven by the selection logic 504 together with the

Buffer amplifiers 513 enable the measurement of a voltage value, the output voltage ΔVQUT ^TO a

Time τ after the start of the charging process.

Calculations analogous to those described above in connection with the exemplary embodiment according to FIG. 3 again lead to an expression for the desired parasitic ohmic lead resistance, which results according to the following rule:

Das Ausführungsbeispiel gemäß Fig.5 erfordert somit die Vorgabe der Spannung Vi und die Messungen des Stromwertes Ii und der Spannung ΔVQUT •

The embodiment according to FIG. 5 thus requires the presetting of the voltage Vi and the measurements of the current value Ii and the voltage ΔVQUT.

The discussion of the accuracy is identical to that of the embodiment described above, which has been shown in FIG. 3, and again the following equation applies:

N

The embodiments described above are particularly suitable for a DUT 301, which has a relatively small RC constant.

According to the embodiments described above, the measurement principle of the circuit arrangements 300, 500 is based on the precise timing of charging and discharging operations of the DUT 301 by means of the drive circuit 327. The measurement of time averages of analog electrical variables, such as the discharge current or the voltage allows the determination of the resistive portion in the DUT 301.

The embodiments described above have, inter alia, the following effects:

• The on-chip integrated measuring circuit avoids unwanted parasitic electrical elements.

With regard to the characterization of the DUT 301 with a certain RC constant, the method is only due to the precision of the DLL circuit 327, generally the

Timer circuit 327, limited and is therefore suitable, for example, just for small values of the RC constant.

• The measuring effort is low and can be measured, for example, with standard measuring instruments, such as a Parameter analyzer from Agilent. • For the determination of the parasitic ohmic

Cable resistance, no information about the capacitive component of the DUT 301 is required.

Fig. 6 shows an integrated circuit assembly 600 according to another embodiment of the invention.

In this embodiment of the invention, the DUT 501 is also a dynamic random access memory cell having a trench capacitor 602 of capacitance CT and a select transistor 603 for selecting the respective memory cell 601 according to a select signal supplied via a word line 604 to the gate terminal of the select - Transistor 603 is performed.

In this case, the selection transistor 603 is shown in order to make it clear that, if necessary, an additional ohmic resistance is taken into account or additionally determined in the determination of the parasitic ohmic supply resistance RT 605 of the DUT 601, in this case the resistance .des Select transistor 603 formed by the distance of the source region, the channel region and the drain region of the select transistor 603.

The first source / drain region 606 of the select transistor 603 is coupled to the trench capacitor 602 by way of the feed line to the line resistor 605. The second source / drain region 607 of the select transistor 603 is coupled to a bit line 608 and above to the input

609 of a Schmitt trigger circuit 610 coupled. The reference voltages U _re fi and U _re f2 are used to adjust the two Sehaltschwellen the Schmitt trigger circuit 610. A possible realization of the Schmitt trigger circuit

610 has an operational amplifier 611 and a Power source circuit, which is shown in detail in Figure 7.

The output 612 of the Schmitt trigger circuit 610 is fed back to two switches, namely the control input 613 of a first switch 614 and the control input 615 of a second switch 616.

A first terminal 617 of the first switch 614 is coupled to a first current source 618, which provides a current +1 and which is realized, for example, by means of a current source transistor. The second terminal 619 of the first switch 614 is coupled in a first switch position to a second reference voltage U _re f2 620 and in a second switch position to a node 621 which is coupled to the bit line 608.

A first terminal 622 of the second switch 615 is coupled to a second current source 623, which has one to the

Current +1 equal in magnitude, but with opposite signs, i. I, wherein the second current source 623 may also be realized by means of a current source transistor. The second terminal 624 of the second switch 615 is in a first

Switch position coupled to a first reference voltage U _re fi 625 and in a second switch position with the node 621 and thus with the bit line 608th

The two switches 614 and 616 are switched in such a way that in each case only one of the two switches is coupled to the node 621 and thus either the current +1 or the current -I flows to the bit line 608. The other of the two switches 614, 616 is in each case at one of the two reference voltages and is thereby pre-charged to the voltage value (pre-charged), in which the node 621 is located when the device is switched on again. This reduces the Influence of parasitic capacitances and stabilizes the operating point of the current sources 618, 623, which are realized for example by means of current source transistors.

Clearly, the two switches 614, 616 are thus activated depending on the binary output state and thus the binary output signal of the Schmitt trigger circuit 610.

Fig. 7 shows the Schmitt trigger circuit 610 in detail.

The Schmitt trigger circuit 610 has a third switch 701 whose control input 702 is coupled to the output 612 of the operational amplifier 611 and whose first input 703 is coupled to a reference voltage input 626 of the operational amplifier 611 and whose second input 704 each is coupled to switch position either to a first voltage source 705 (first switch position of switch 701) which provides the voltage (U + ΔU) and coupled in a second switch position to a second voltage source 706 which provides the voltage (U - ΔU).

This means that, depending on the output signal state of the operational amplifier 611, either the voltage (U + ΔU) for the operational amplifier 611 is used as the first reference voltage U _re f] _ or a voltage (U - ΔU) as the second reference Voltage U _re f2-

Clearly, the measuring circuit in the circuit arrangement 600 corresponds to a free-running oscillator for determining the trench resistor RT. In the memory cell 601, a current +1 is impressed in a first phase, which from the first current source 618 via the first switch 614, which is in the Schalterpositiori such that the current +1 from the first current source 618 to the node 621 and thus to the bit line BL 608 and above into the trench capacitor 602.

The current +1 causes a time independent voltage drop I * RT on bit line 608, as in the voltage diagram

800 is shown symbolically in FIG. The voltage on the bit line BL 608 increases linearly with time (depending on the current +1 and the trench capacitance CT, in other words the capacitance of the trench capacitor 602). The voltage on the bit line BL 608 is measured by a comparator circuit with the Schmitt trigger circuit 610.

Upon reaching an upper voltage reference value U _re fi, which is provided by the first voltage source 705, the bit line BL 608 is switched to a current source of equal amplitude but inverse sign, namely the second current source 623, which provides the current -I. This is done by bringing the first switch 614 to the second switch position at this time and coupling it to the second reference voltage U _re f2 and bringing the second switch 616 into its second switch position and thus the second current source 623 to the node 621 and is coupled thereto via the bit line BL 608.

The voltage drop I * RT thus changes its direction and the voltage decreases linearly with time, as also shown in Fig.8. Upon reaching a lower voltage reference, the second reference voltage U _re f2 / which is provided by the second voltage source 706, the first current source is reconnected and the process repeats. This is done by bringing the second switch 616 from its second switch position to its first switch position and thereby coupling it to the first reference voltage U _re fi 625. The first switch 614 is again brought into its first switch position, which in turn the first current source 618 with the Node 621 and above is coupled to bit line BL 608.

ΔU = U _re fi -U _re f ₂ results in an oscillation frequency f of:

f = (H)

2 • C _τ • (Δμ - I • R _τ )

and thus the trench resistor RT according to the following rule:

_{Rτ =} ^ _ _ ^ (12)

I f • C _τ

In the following, the accuracy of the resistance determination of the parasitic ohmic resistance of the supply line RT is to be determined as a function of inaccuracies of the variables I, ΔU and CT.

For this purpose, an error calculation for the frequency according to equation (11) is carried out according to the following rule:

The quantities σj and σ ^ u are inaccuracies of the current generation and the reference voltage generation or

Comparator measurement. The uncertainty of the value of the trench capacitance CT of the trench capacitor 602 is expressed by σ ^. The evaluation of the resistance according to equation (12) with a modified frequency (f + σf) gives:

where I, ΔU, C _τ and f are nominal values.

The relative error of the resistance determination thus results from:

The output voltage UouT ', which is provided at the output 612 of the Schmitt trigger circuit 610, is shown in its time history in the voltage diagram 900 in FIG.

FIGS. 10 and 11 show the evaluation of equation (15) as a function of the oscillation frequency f (see graph 1000 in FIG. 10) or of the current corresponding thereto (compare graph 1100 in FIG. 11).

As a parameter for the family of curves, the determination of the value for the capacitance CT of the trench capacitor 602 is given.

It can be seen that the accuracy of

Resistance determination for increasing frequencies (currents) and good knowledge of the trench capacitance CT of the trench capacitor 602 increases. If the trench capacitance CT is known only with a precision of 10%, and if the determination of the parasitic resistive line resistance RT should also be carried out with 10% accuracy, then, according to the diagram 1000 in FIG. 10, a frequency f of approximately 1 GHz must be measured , Such high frequencies pose a great challenge to the comparator circuit, ie in this case for the Schmitt trigger circuit 610. In order to reduce the requirements for the comparator circuit and thus the Schmitt trigger circuit 610, according to one exemplary embodiment of the invention, a measuring process is provided in which the value of the trench capacitance 0χ of the trench capacitor 602 in a first step at low frequencies (currents) , for example, using the same circuit arrangement 600, as shown in Figure 6, is determined exactly.

In a second measurement, the parasitic ohmic supply resistance RT to be determined is subsequently measured at moderate frequencies.

For example, it can be seen from FIG. 10 that the 10%

Resistance accuracy is achieved with a measurement frequency below 100 MHz, when the uncertainty of the capacitance CT of the trench capacitor 602 is limited to 1% (see first curve 1001 in Fig. 10).

Fig. 12 shows an integrated circuit arrangement 1200 according to another embodiment of the invention.

Also in this embodiment of the invention is based on a DUT 1201, which is a trench capacitor

1202 a dynamic random access memory memory cell contains in an array a plurality, for example, thousands or millions of trench capacitors as DRAM memory cells in a corresponding memory cell array.

To determine is the parasitic resistance of the supply line to the respective trench capacitor 1202, shown in Figure 12 by means of a parasitic supply resistance R

1,203th Furthermore, a buffer capacitor 1204 as well as a reference capacitor 1205 and a reference buffer capacitor 1206 are provided in FIG.

Furthermore, the circuit arrangement 1200 has a first switch S1 1207, a second switch S2 1208, a third switch S3 1209, a fourth switch S4 1210, a fifth switch S5 1211 and a sixth switch S6 1212.

The first switch Sl 1207 is connected between the DUT 1201 and a reference voltage Vi _n 1213. The fourth switch S4 1210 is coupled between the reference voltage 1213 and the reference capacitor 1205.

The second switch S2 1208 is connected between the DUT 1201 and the latch capacitor 1204.

The third switch S3 1209 is coupled between the ground potential and thus a first terminal of the latch capacitor 1204 and the second terminal of the latch capacitor 1204 and thus short-circuits the latch capacitor 1204 when the third switch S3 1209 is closed.

The fifth switch S5 1211 is coupled on the one hand to the reference capacitor 1205 and on the other hand to the reference latch capacitor 1206.

The sixth switch S6 1212 is between a first one

Terminal of the reference latch capacitor 1206 and the second terminal of the reference latch capacitor 1206 and closes this to the ground potential for a short time when the sixth switch S6 1212 is closed. Furthermore, a first comparator 1214 and a second comparator 1215 are provided.

The first input 1216 of the first comparator 1214 is coupled to one terminal of the latch capacitor 1204, the second switch S2 1208, and the third switch S3 1209. The second input 1217 of the first comparator 1214 is coupled to a second reference potential Vi _n / 3 1218. The first input 1219 of the second comparator 1215 is coupled to the reference latch capacitor 1206 and to the fifth switch S5 1211 and the sixth switch S6 1212. The second input 1220 of the second comparator 1215 is coupled to one terminal of the reference latch capacitor 1206, the sixth switch S6 1212 and the fifth switch S5 1211 coupled.

The output 1221 of the first comparator 1214 is coupled to a first input 1222 of a first flip-flop circuit 1223 and further to a first inverter 1224 of a first delay stage 1225 having an additional series-connected second inverter 1226. In the circuit arrangement 1200, in addition to the first delay stage 1225, there are also five further delay stages 1227, 1228, 1229, 1230, 1231 connected in series, each with two series-connected inverters. Each delay stage 1227, 1228, 1229, 1230, 1231 has a delay for the signal propagation of the output signal of the first comparator 1214 of 450 ps according to this embodiment of the invention.

The output 1232 of the second comparator 1215 is coupled to a second input 1233 of the first flip-flop circuit 1223. Further, the output 1232 of the second comparator 1215 is coupled to the input of a first reference inverter 1234 of a first reference delay stage 1235 which additionally includes a second reference inverter connected in series with the first reference inverter 1234 1236 has. The first delay stage according to this embodiment of the invention, five further delay stages 1237, 1238, 1239, 1240, 1241 followed.

In this regard, it should be noted that in principle any number of delay stages in series may be connected in series to the output 1232 of the second comparator 1215 and any number of delay stages in series to the output 1221 of the first comparator 1214 for the respective time delay of the signal propagation of the first comparator 1214 Output signal of the second comparator 1215 and the first comparator 1214, respectively.

Each reference delay stage 1234, 1236, 1237, 1238, 1239, 1240, 1241 produces a time signal propagation delay of a signal applied to its input with respect to its output signal of 500 ps.

Generally, the reference inverters are according to this

Embodiment of the invention, a greater time delay than the inverters connected to the first comparator 1214 delay stages.

Thus, the signal propagation occurs along the

Series connection of the reference delay stages slower than the signal propagation along the series connection of the delay stages.

Furthermore, one of the number of the respective

Delay stages or reference delay stages corresponding flip-flop circuits 1242, 1243, 1244, 1245, 1246 provided (in the present example, six flip-flop circuits are thus provided in the circuit arrangement 1200), wherein a respective first input of the respective flip Floating circuit 1247, 1248, 1249, 1250, 1251 between a respective output of a Delay stage and the input of a downstream delay stage is connected.

A respective second input 1252, 1253, 1254, 1255, 1256 of a respective flip-flop circuit 1242, 1243, 1244, 1245, 1246 is connected between a respective output of a reference delay stage 1234, 1236, 1237, 1238, 1239, 1240, 1241 and the respective input of a respective downstream reference delay stage switched.

The respective outputs 1257, 1258, 1259, 1260, 1261, 1262 of the flip-flop circuits 1223, 1242, 1243, 1244, 1245, 1246 are coupled to an output register 1263 into which the respective output values of the flip-flop circuits Circuits 1223, 1242, 1243, 1244, 1245, 1246 are written.

Instead of the inverters or the reference inverters, any other delay elements can be provided which provide a time delay for the signal propagation of the respective output signal of the comparators 1214, 1215.

Furthermore, in the circuit arrangement, a first

Ring oscillator circuit 1264 having inverters 1265, 1266, 1267, 1268, 1269 coupled in series with one another and a binary counter 1270 coupled to the output of inverter 1269, which provides a signal having a first frequency f 1, the Inverter of the first ring oscillator circuit 1264 has the same timing and thus the same temporal

Signal delay as the inverters of the delay stages

1226, 1227, 1228, 1229, 1230 and 1231.

Furthermore, a signal having a second frequency .2 .2 providing second ring oscillator circuit 1271 is provided, which has five reference inverters 1272, 1273, 1274, 1275, 1276, wherein the inverters of the second Ring oscillator circuit 1271 have the same timing and thus the same time signal propagation delay as the reference inverters of the reference delay stages 1235, 1237, 1238, 1239, 1240 and 1241. Further, the second ring oscillator circuit 1271 has a second binary counter 1277 which is coupled to the output of inverter 1276.

An idea underlying the circuit arrangement 1200 can be clearly seen in the measurement of the time difference of recharging events between the DUT 1201 (for example, a DRAM memory cell) and a known reference structure (the reference capacitor, the reference latch capacitor , the second comparator 1215 and the reference delay stages).

In a first phase, the nodes Vl and V4 are charged to an initial potential V ^ _n by closing the first switch Sl 1207 and the fourth switch S4 1210.

At the same time, the nodes V2 and V5 are reset to zero potential according to this embodiment by also closing the third switch S3 1209 and the sixth switch S6 1212 in this phase, so that the nodes V2 and V5 are discharged to the ground potential.

In a next step, the first switch Sl 1207, the third switch S3 1209, the fourth switch S4 1210 and the sixth switch S6 1212 are opened and the second switch S2 1208 and the fifth switch S5 1211 are closed. In this way, the potentials are equalized at the nodes V1 and V2 or at the nodes V4 and V5.

The compensation between the voltages at the nodes V1 and V2 is slower than the compensation of the voltages at the

Nodes V4 and V5, since in the DUT 1201, the parasitic resistive lead resistance 1203 the charge transfer of the charge carriers from the trench capacitor 1202 to the latch capacitor 1204, as compared to the reloading of the electrons from the reference capacitor 1205 to the reference latch capacitor 1206 where there is no such parasitic lead resistance.

Thus, the output of the second comparator 1215 is switched earlier and thus faster than the first comparator 1214 (in other words, this means that the potential at the node V6 assumes a high level faster than the node V3, i.e., the output of the first comparator 1214.

The output signals of the comparators 1214, 1215, which are in digital form, propagate through the inverter chains (also referred to as the Verier line).

The state of the flip-flop circuits, realized for example by means of feedback NAND gates, changes at the point where the time delay of the signals between the outputs of the two comparators 1214, 1215 is equal to the skew of the inverter chains, i. the respective delay stages or reference delay stages.

In this way, the time difference of

Transhipment operations digitized. In order to determine the transit time difference between the two inverter types, the two ring oscillator circuits 1264, 1271 are additionally provided, which provide a frequency reference.

The sought parasitic resistive impedance R is calculated according to the following rule:

N fo - fI,

R = • - -, (16) k • C • In 3 f ₂ • fi

being with N is the stage number of the delay stage or the reference delay stage, at which the state of the respective flip-flop circuit changes,

K is the number of delay stages provided in the respective ring oscillator circuit 1264, 1271,

F] _ the frequency of the first ring oscillator circuit 1264,

F2 is the frequency of the second ring oscillator circuit 1271, and

• C is the capacitance of trench capacitor 1202.

The capacity of the trench capacitor 1202 is assumed to be known or determined by means of measuring methods known per se, for example in the manner described above in connection with the exemplary embodiments according to FIG.

LIST OF REFERENCE NUMBERS

100 circuit arrangement

101 chip external measuring device 102 integrated circuit

103 cables

104 Bond connection pad

105 DUT

106 capacitor 107 parasitic resistance

108 capacitance Bond connection pad

109 capacity wiring

110 ohmic resistor wiring

200 integrated circuit arrangement

201 connection pad

202 trace

203 electronic component

204 capacitors 205 parasitic resistance

206 detection circuit

207 control unit

300 circuit arrangement 301 DUT

302 capacitor

303 parasitic ohmic resistance

304 knots

305 first terminal first switch 306 first switch

307 second connection first switch

308 chip external current measuring device

309 voltage source

310 second connection second switch 311 second switch

312 first connection second switch

313 second connection third switch 314 third switch

315 first connection third switch

316 second chip external Strominesseinrichtung

317 first RS flip-flop 318 second RS flip-flop

319 third RS flip-flop

320 Output first RS flip-flop

321 control connection first switch

322 Output second RS flip-flop 323 Control connection second switch

324 Output third RS flip-flop

325 control connection third switch

326 Dynamic Element Matching Unit

327 DLL circuit 328 Set input first RS flip-flop

329 Reset input first RS flip-flop

330 Set input second RS flip-flop

331 Reset input second RS flip-flop

332 Reset input third RS flip-flop 333 Reset input third RS flip-flop

400 time diagram

401 Charging process

402 first partial discharge 403 second partial discharge

404 charging curve

405 first partial discharge curve

406 second partial discharge curve

450 circuit diagram 451 first switch drive signal

452 second switch drive signal

453 third switch drive signal

500 circuit arrangement 501 fourth switch

502 fifth switch

503 sixth switch 504 Selection logic

505 control connection fourth switch

506 control connection fifth switch

507 control connection sixth switch 508 first connection fourth switch

509 second connection fourth switch

510 first connection fifth switch

511 second connection fifth switch

512 input buffer amplifier 513 buffer amplifier

514 output buffer amplifier

515 second connection sixth switch

516 first connection sixth switch

517 buffer capacitor

600 circuit arrangement

601 DUT

602 trench capacitor

603 select transistor 604 word line

605 parasitic resistive supply resistance

606 first source / drain select transistor

607 second source / drain region select transistor

608 bit line 609 first input Schmitt trigger circuit

610 Schmitt trigger circuit

611 power source circuit

612 Schmitt trigger circuit output

613 control terminal first switch 614 first switch

615 control port second switch

616 second switch

617 first connection first switch

618 first current source 619 second terminal first switch

620 second reference voltage

621 knots 622 first connection second switch

623 second power source

624 second connection second switch

625 second reference voltage 626 reference voltage input Schmitt trigger circuit

701 voltage source switch

702 control terminal power source switch

703 first terminal power source switch 704 second terminal power source switch

705 first voltage source

706 second voltage source

800 voltage-time diagram 900 voltage-time diagram

1000 first diagram

1001 first turn

1100 second diagram

1200 integrated circuit arrangement

1201 DUT

1202 trench capacitor

1203 parasitic ohmic supply resistance 1204 intermediate storage capacitor

1205 reference capacitor

1206 reference latch capacitor

1207 first switch

1208 second switch 1209 third switch

1210 fourth switch

1211 fifth switch

1212 sixth switch

1213 reference voltage (Vj_ _n) first comparator 1214

1215 second comparator

1216 first input first comparator 1217 second input first comparator

1218 second reference potential

1219 first input second comparator 1220 second input second comparator 1221 output first comparator

1222 first input first flip-flop circuit

1223 first flip-flop circuit

1224 first inverter first delay stage

1225 first delay stage 1226 second inverter first delay stage

1227 delay stage

1228 delay level

1229 delay stage

1230 delay stage 1231 delay stage

1232 output second comparator

1233 Second input first flip-flop circuit

1234 first reference inverter

1235 first reference delay stage 1236 second inverter first reference delay stage 1237 reference delay stage 1238 reference delay stage

1239 Reference delay stage

1240 Reference delay stage 1241 Reference delay stage

1242 second flip-flop circuit

1243 third flip-flop circuit

1244 fourth flip-flop circuit

1245 fifth flip-flop circuit 1246 sixth flip-flop circuit

1247 first input second flip-flop circuit

1248 first input third flip-flop circuit

1249 first input fourth flip-flop circuit

1250 first input fifth flip-flop circuit 1251 first input sixth flip-flop circuit

1252 second input second flip-flop circuit

1253 second input third flip-flop circuit 1254 second input fourth flip-flop circuit

1255 second input fifth flip-flop circuit

1256 second input sixth flip-flop circuit

1257 output first flip-flop circuit 1258 output second flip-flop circuit

1259 output third flip-flop circuit

1260 output fourth flip-flop circuit

1261 output fifth flip-flop circuit

1262 output sixth flip-flop circuit 1263 output register

1264 first ring oscillator circuit

1265 Inverter 1266 Inverter 1267 Inverter 1268 Inverter

1269 inverter

1270 binary counter circuit

1271 second ring oscillator circuit

1272 Reference inverter 1273 Reference inverter

1274 reference inverter

1275 reference inverter

1276 reference inverter

1277 binary counter circuit

Claims

claims An integrated circuit arrangement, comprising: at least one electronic component, at least one resistance detection circuit coupled to the electronic component and monolithically integrated therewith for determining the parasitic ohmic resistance of at least the supply line to the at least one electronic component. 2. The integrated circuit arrangement of claim 1, further comprising a monolithically integrated sensing circuit in the circuit arrangement for detecting electrical quantities characterizing the at least one electronic component. 3. Integrated circuit arrangement according to claim 1 or 2, further comprising a monolithically integrated in the circuit arrangement drive unit for driving the at least one electronic component during detection of the parasitic ohmic resistance of at least the supply line to the at least one electronic component. 4. Integrated circuit arrangement according to one of claims 1 to 3, wherein the at least one electronic component is arranged as a memory cell. 5. The integrated circuit arrangement according to claim 1, wherein the at least one electronic component has at least one capacitor. 6. Integrated circuit arrangement according to claims 4 and 5, wherein the at least one electronic component has at least one capacitor for storing electrical charge carriers. 7. The integrated circuit arrangement according to claim 1, wherein the at least one electronic component comprises a component selection unit for selecting the at least one electronic component. The integrated circuit device of claim _1, wherein the component selection unit is formed by at least one component selection transistor. The integrated circuit arrangement according to one of claims 4 to 8, wherein the at least one memory cell is a dynamic random access memory memory cell. 10. The integrated circuit arrangement according to claim 3, wherein the drive unit is set up to control the charging and discharging of the electronic component with or from electrical charge carriers. 11. Integrated circuit arrangement according to claims 4 and 10, wherein the drive unit is set up such that The at least one capacitor is substantially completely charged in a first activation phase, • a capacitor is discharged in a second actuation phase ^• at least partially, and • The at least one capacitor is substantially completely discharged in a third drive phase. 12. The integrated circuit arrangement according to claim 11, wherein the drive unit is set up such that the three drive phases are repeatedly performed. 13. Integrated circuit arrangement according to one of claims 3 to 12, wherein the drive unit is formed by one of. following circuits: • Delay locked loop circuit, • Phase Locked Loop Circuit, • Ring Oscillator Circuit. 14. An integrated circuit arrangement according to any one of claims 10 to 13, wherein the detection circuit is adapted to detect at least one of the following electrical Sizes: Discharge current of the at least one electronic component, and / or • voltage applied to the at least one electronic component. An integrated circuit device according to any one of claims 2 to 14, wherein the resistance detection circuit is arranged to detect the parasitic resistance of the lead using the electrical quantities detected by the detection circuit. 16. An integrated circuit device according to claims 2 and 10, wherein the resistance detection circuit is arranged to detect the parasitic ohmic resistance the lead using time averaged values of the electrical quantities detected during charging and discharging of the at least one electronic component. 17. An integrated circuit arrangement according to claims 11 and 16, wherein the resistance-determining circuit is arranged such that the parasitic resistance is determined according to the following rule:

where with '• R the parasitic resistance of the supply line, N is the number of time slots of charging and discharging the capacitor, • Ii the time average of the charging current during the first activation phase, • 13 the time average of the discharge current during the third activation phase, • Vi is a voltage provided for charging the capacitor. 18. Integrated circuit arrangement according to one of claims 1 to 17, further comprising an output amplifier, which is the input side coupled to the electronic component and which provides an output side amplifier output voltage. 19. Integrated circuit arrangement according to claims 11, 16, and 17, wherein the resistance detection circuit is arranged such that the parasitic resistance is determined according to the following rule:

being with R the parasitic resistance of the supply line, N is the number of time slots of charging and discharging the capacitor, Ii is the time average of the charging current during the first activation phase, Vi is a voltage supplied to charge the capacitor, ΔVQTJT is the amplifier output voltage. 20. An integrated circuit arrangement according to one of claims 1 to 19, further comprising a unit for balancing temporal Inequalities of different time slots. 21. The integrated circuit arrangement according to claim 10, wherein the drive unit is set up such that: the at least one capacitor is charged in a charge drive phase, • the at least one capacitor is discharged in a discharge drive phase. 22. The integrated circuit device according to claim 21, wherein the drive unit comprises an oscillation measurement circuit, wherein the oscillation measurement circuit is configured such that In the charge-drive phase, the capacitor is charged until a charging threshold is reached, Upon reaching the charging threshold, the drive unit is switched to the discharge drive phase, so that the capacitor is discharged, • in the discharge drive phase, the capacitor is discharged until a discharge threshold is reached, and • When the discharge threshold is reached, the drive unit is switched to the charge drive phase so that the capacitor is charged. 23. An integrated circuit arrangement according to claim 22, wherein the Oszillationsmess circuit comprises a Schmitt trigger whose first threshold of the Charging threshold and its second threshold is the discharge threshold. 24. The integrated circuit arrangement according to claim 23, wherein the drive unit further comprises: A first current source for providing a charging current for charging the capacitor, A second current source for providing a discharge current for discharging the capacitor, At least one switch for selectively coupling the first power source or the second power source to the capacitor, Wherein the at least one switch is coupled to the output of the Schmitt trigger such that, depending on the output signal of the Schmitt trigger, the first current source or the second current source couples to the capacitor. 25. Integrated circuit arrangement according to claim 23 or 24, Wherein the charging threshold is a first reference voltage and wherein the discharging threshold is a second reference voltage. The integrated circuit device according to any one of claims 22 to 25, wherein the resistance detection circuit is arranged to detect the parasitic resistance using the oscillation frequency of the oscillation measurement circuit. 27 integrated circuit arrangement according to claim 25 and 26, wherein the resistance-determining circuit is arranged such that the parasitic resistance is determined according to the following rule: ΔU 2 R = f • C _τ R the parasitic resistance of the supply line, ΔU is the difference between the first reference voltage and the second reference voltage, I the charging current for charging the capacitor, F the oscillation frequency of the oscillation measuring circuit, • C _{τ is} the capacitance of the capacitor. 28. Integrated circuit arrangement according to claim 10, • further comprising at least one reference component, • wherein the drive unit is set up such that the at least one electronic component and charging the at least one reference component with the same voltage or with two voltages that are uniquely correlated with each other. 29. An integrated circuit device according to claim 28, wherein the reference component comprises at least one reference capacitor. 30. The integrated circuit arrangement according to claim 4 and 29, further comprising At least one buffer capacitor coupled to the capacitor, At least one reference latch capacitor coupled to the reference capacitor, Wherein the drive unit further comprises: A first switch connected between a first voltage source and the capacitor, a second switch connected between the first Voltage source and the capacitor is connected or which is connected between a second voltage source and the capacitor, • a third switch, which between the Capacitor and the latch capacitor is connected, A fourth switch connected between the reference capacitor and the reference latch capacitor, • wherein the drive unit is set up such that In a first phase, the first switch and the second switch are closed and the third switch and the fourth switch are open, and In a second phase, the first switch and the second switch are open and the third switch and the fourth switch are closed. 31. The integrated circuit assembly of claim 30, further comprising A fifth switch connected between the latch capacitor and a reference potential, A sixth switch connected between the reference latch capacitor and the reference potential. 32. The integrated circuit arrangement according to claim 31, wherein the drive unit is set up such that • in the first phase the fifth switch and the sixth switch are closed, and • in the second phase the fifth switch and the sixth switch are open. 33. The integrated circuit arrangement according to claim 28, wherein the resistance determination circuit is configured to determine the parasitic ohmic resistance of the supply line using the time difference of a charge transfer of electric charges of the at least one electronic component and a charge transfer of electric charges of the at least a reference component. 34. The integrated circuit assembly of claim 28, further comprising A comparator whose first input is coupled to the electronic component and whose second input is coupled to a third voltage source, A reference comparator whose first input is coupled to the reference component and whose second input is coupled to the third voltage source or to a fourth voltage source; wherein the resistance determination circuit is arranged to determine the parasitic ohmic resistance of the supply line using the time difference switching the comparator and the reference comparator. 35. The integrated circuit assembly of claim 28, further comprising A first signal propagation path having at least one first signal propagation delay element, a second signal propagation path having at least one second signal propagation delay element, Wherein the at least one second signal propagation delay element is set up in such a way that its signal propagation delay is greater than that of the at least one first signal propagation delay Delay element. 36. An integrated circuit arrangement according to claim 35, Wherein the first signal propagation path is a plurality of series connected first signal propagation paths; Delay elements, wherein one or more first signal propagation delay elements are grouped into first signal propagation delay stages, wherein the second signal propagation path comprises a plurality of series connected second signal propagation delay elements, wherein one or more second signal propagation delay elements are grouped into second signal propagation delay stages , 37. An integrated circuit arrangement according to claim 36, wherein a bistable flip-flop is connected between the output of the comparator and the output of the reference comparator. ^' 38. An integrated circuit arrangement according to claim 36 or 37, wherein between the output of at least a portion of the first signal propagation delay stages and a corresponding second signal propagation delay stage is in each case a bistable flip-flop connected. 39. The integrated circuit arrangement according to claim 35, wherein the at least one first signal propagation delay element is formed from at least one first inverter. Wherein the at least one second signal propagation delay element is formed from at least one second inverter, 40. An integrated circuit arrangement as claimed in claim 38 or 39, wherein the resistance detection circuit is arranged to detect the parasitic ohmic resistance of the supply line using the output signals of the bistable flip-flops. 41. Integrated circuit arrangement according to one of claims 36 to 40, Having a first reference structure having signal propagation delay elements whose signal propagation delay is equal to that of the first signal propagation delay elements, Having a second reference structure which has signal propagation delay elements, whose signal propagation delay is equal to that of the second signal propagation delay elements. 42. An integrated circuit arrangement according to claim 41, Wherein the first reference structure comprises a first ring oscillator with the signal propagation delay elements, Wherein the second reference structure comprises a second ring oscillator with the signal propagation Having delay elements. 43. The integrated circuit arrangement according to claim 42, wherein the resistance-determining circuit is set up such that the parasitic resistance is determined according to the following rule: _{R =} N. ^f 2 - fl k ^■ C _τ ^• In 3% • f2 R the parasitic resistance of the supply line, N is the number of the signal propagation delay stage at which the state of the associated bistable multivibrators changes compared to the immediately preceding bistable multivibrators, K is the number of signal propagation delay elements in the first reference structure, the number of signal propagation delay elements in the first reference structure and the number of signal propagation delay elements in the first reference structure; Delay elements in the second reference structure is the same, • fi the frequency of the first ring oscillator, • f _{2 is} the frequency of the second ring oscillator, • C _{τ is} the capacitance of the capacitor. 44. Method for determining the parasitic ohmic Resistance of at least the supply line to at least one memory cell of an integrated circuit arrangement, the method comprising: On-chip detection of electrical quantities characterizing the at least one memory cell. On-chip determination of the parasitic ohmic resistance using the detected electrical quantities.