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WO2007085978A3 - A method of controlling a page cache memory in real time stream and best effort applications - Google Patents

A method of controlling a page cache memory in real time stream and best effort applications Download PDF

Info

Publication number
WO2007085978A3
WO2007085978A3 PCT/IB2007/050115 IB2007050115W WO2007085978A3 WO 2007085978 A3 WO2007085978 A3 WO 2007085978A3 IB 2007050115 W IB2007050115 W IB 2007050115W WO 2007085978 A3 WO2007085978 A3 WO 2007085978A3
Authority
WO
WIPO (PCT)
Prior art keywords
controlling
real time
applications
best effort
time stream
Prior art date
Application number
PCT/IB2007/050115
Other languages
French (fr)
Other versions
WO2007085978A2 (en
Inventor
Ozcan Mesut
Gassel Jozef P Van
Nijs Gilein De
Steven B Luitjens
Siarhei Yermalayeu
Artur Burchard
Original Assignee
Koninkl Philips Electronics Nv
Ozcan Mesut
Gassel Jozef P Van
Nijs Gilein De
Steven B Luitjens
Siarhei Yermalayeu
Artur Burchard
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Koninkl Philips Electronics Nv, Ozcan Mesut, Gassel Jozef P Van, Nijs Gilein De, Steven B Luitjens, Siarhei Yermalayeu, Artur Burchard filed Critical Koninkl Philips Electronics Nv
Publication of WO2007085978A2 publication Critical patent/WO2007085978A2/en
Publication of WO2007085978A3 publication Critical patent/WO2007085978A3/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0866—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches for peripheral storage systems, e.g. disk cache
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/12—Replacement control
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)

Abstract

The present invention relates to controlling a page cache memory in devices which are implemented to run both best effort (BE) applications and simultaneously real time stream applications, where the controlling is based on adapting the buffer size dynamically to these applications. The aim of the present invention is therefore to maintain the power consumption associated with storage means, especially hard disk drive (HDD), for such real time stream and best effort applications optimally.
PCT/IB2007/050115 2006-01-26 2007-01-15 A method of controlling a page cache memory in real time stream and best effort applications WO2007085978A2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP06300071.5 2006-01-26
EP06300071 2006-01-26

Publications (2)

Publication Number Publication Date
WO2007085978A2 WO2007085978A2 (en) 2007-08-02
WO2007085978A3 true WO2007085978A3 (en) 2007-10-18

Family

ID=38091197

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/IB2007/050115 WO2007085978A2 (en) 2006-01-26 2007-01-15 A method of controlling a page cache memory in real time stream and best effort applications

Country Status (1)

Country Link
WO (1) WO2007085978A2 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9143381B2 (en) 2009-04-16 2015-09-22 Microsoft Technology Licenising, LLC Sequenced transmission of digital content items
CN103763371A (en) * 2014-01-21 2014-04-30 深圳市脉山龙信息技术股份有限公司 Method for dynamically controlling mobile end application cache

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5581736A (en) * 1994-07-18 1996-12-03 Microsoft Corporation Method and system for dynamically sharing RAM between virtual memory and disk cache
US6122708A (en) * 1997-08-15 2000-09-19 Hewlett-Packard Company Data cache for use with streaming data
US6438668B1 (en) * 1999-09-30 2002-08-20 Apple Computer, Inc. Method and apparatus for reducing power consumption in a digital processing system
US20030074524A1 (en) * 2001-10-16 2003-04-17 Intel Corporation Mass storage caching processes for power reduction

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5581736A (en) * 1994-07-18 1996-12-03 Microsoft Corporation Method and system for dynamically sharing RAM between virtual memory and disk cache
US6122708A (en) * 1997-08-15 2000-09-19 Hewlett-Packard Company Data cache for use with streaming data
US6438668B1 (en) * 1999-09-30 2002-08-20 Apple Computer, Inc. Method and apparatus for reducing power consumption in a digital processing system
US20030074524A1 (en) * 2001-10-16 2003-04-17 Intel Corporation Mass storage caching processes for power reduction

Also Published As

Publication number Publication date
WO2007085978A2 (en) 2007-08-02

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