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WO2007084202A3 - Processor core and method for managing branch misprediction in an out-of-order processor pipeline - Google Patents

Processor core and method for managing branch misprediction in an out-of-order processor pipeline Download PDF

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Publication number
WO2007084202A3
WO2007084202A3 PCT/US2006/041614 US2006041614W WO2007084202A3 WO 2007084202 A3 WO2007084202 A3 WO 2007084202A3 US 2006041614 W US2006041614 W US 2006041614W WO 2007084202 A3 WO2007084202 A3 WO 2007084202A3
Authority
WO
WIPO (PCT)
Prior art keywords
instruction
pipeline
processor
misprediction
processor core
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US2006/041614
Other languages
French (fr)
Other versions
WO2007084202A2 (en
Inventor
Karagada Ramarao Kishore
Kjeld Svendsen
Vidya Rajagopalan
Maria Ukanwa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
MIPS Tech LLC
Original Assignee
MIPS Technologies Inc
MIPS Tech LLC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US11/261,655 external-priority patent/US7734901B2/en
Priority claimed from US11/261,654 external-priority patent/US7711934B2/en
Application filed by MIPS Technologies Inc, MIPS Tech LLC filed Critical MIPS Technologies Inc
Publication of WO2007084202A2 publication Critical patent/WO2007084202A2/en
Publication of WO2007084202A3 publication Critical patent/WO2007084202A3/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3861—Recovery, e.g. branch miss-prediction, exception handling
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3838—Dependency mechanisms, e.g. register scoreboarding
    • G06F9/384—Register renaming
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3854—Instruction completion, e.g. retiring, committing or graduating
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3854—Instruction completion, e.g. retiring, committing or graduating
    • G06F9/3858—Result writeback, i.e. updating the architectural state or memory
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3854—Instruction completion, e.g. retiring, committing or graduating
    • G06F9/3858—Result writeback, i.e. updating the architectural state or memory
    • G06F9/38585—Result writeback, i.e. updating the architectural state or memory with result invalidation, e.g. nullification
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3861—Recovery, e.g. branch miss-prediction, exception handling
    • G06F9/3863—Recovery, e.g. branch miss-prediction, exception handling using multiple copies of the architectural state, e.g. shadow registers

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)

Abstract

A processor core and method for managing branch misprediction in an out-of-order processor pipeline. In one embodiment, the pipeline of the processor core includes a front-end instruction fetch portion, a back-end instruction execution portion, and pipeline control logic. Operation of the instruction fetch portion is decoupled from operation of the instruction execution portion. Following detection of a control transfer misprediction, operation of the instruction fetch portion is halted and instructions residing in the instruction fetch portion are invalidated. When the instruction associated with the misprediction reaches a selected pipeline stage, instructions residing in the instruction execution portion of the pipeline are invalidated and the flow of instructions from the instruction fetch portion to the instruction execution portion of the processor pipeline is restarted. A mispredict instruction identification checker and instruction identification tags are used to determine if a control transfer instruction is permitted to redirect instruction fetching.
PCT/US2006/041614 2005-10-31 2006-10-26 Processor core and method for managing branch misprediction in an out-of-order processor pipeline Ceased WO2007084202A2 (en)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US11/261,655 US7734901B2 (en) 2005-10-31 2005-10-31 Processor core and method for managing program counter redirection in an out-of-order processor pipeline
US11/261,654 US7711934B2 (en) 2005-10-31 2005-10-31 Processor core and method for managing branch misprediction in an out-of-order processor pipeline
US11/261,654 2005-10-31
US11/261,655 2005-10-31

Publications (2)

Publication Number Publication Date
WO2007084202A2 WO2007084202A2 (en) 2007-07-26
WO2007084202A3 true WO2007084202A3 (en) 2007-10-04

Family

ID=38267515

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2006/041614 Ceased WO2007084202A2 (en) 2005-10-31 2006-10-26 Processor core and method for managing branch misprediction in an out-of-order processor pipeline

Country Status (2)

Country Link
TW (1) TW200745945A (en)
WO (1) WO2007084202A2 (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8145890B2 (en) * 2009-02-12 2012-03-27 Via Technologies, Inc. Pipelined microprocessor with fast conditional branch instructions based on static microcode-implemented instruction state
US20140156977A1 (en) * 2011-12-28 2014-06-05 Mark J. Dechene Enabling and disabling a second jump execution unit for branch misprediction
CN115617402B (en) * 2022-11-18 2023-04-07 北京数渡信息科技有限公司 Decoupling branch prediction method and device suitable for general processor

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5586278A (en) * 1994-03-01 1996-12-17 Intel Corporation Method and apparatus for state recovery following branch misprediction in an out-of-order microprocessor
US6079014A (en) * 1993-12-02 2000-06-20 Intel Corporation Processor that redirects an instruction fetch pipeline immediately upon detection of a mispredicted branch while committing prior instructions to an architectural state
US6249862B1 (en) * 1996-05-17 2001-06-19 Advanced Micro Devices, Inc. Dependency table for reducing dependency checking hardware
US6760835B1 (en) * 2000-11-22 2004-07-06 Lsi Logic Corporation Instruction branch mispredict streaming

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6079014A (en) * 1993-12-02 2000-06-20 Intel Corporation Processor that redirects an instruction fetch pipeline immediately upon detection of a mispredicted branch while committing prior instructions to an architectural state
US5586278A (en) * 1994-03-01 1996-12-17 Intel Corporation Method and apparatus for state recovery following branch misprediction in an out-of-order microprocessor
US6249862B1 (en) * 1996-05-17 2001-06-19 Advanced Micro Devices, Inc. Dependency table for reducing dependency checking hardware
US6760835B1 (en) * 2000-11-22 2004-07-06 Lsi Logic Corporation Instruction branch mispredict streaming

Also Published As

Publication number Publication date
TW200745945A (en) 2007-12-16
WO2007084202A2 (en) 2007-07-26

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