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WO2007054844A2 - Transistor fet a ailette et procede de fabrication - Google Patents

Transistor fet a ailette et procede de fabrication Download PDF

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Publication number
WO2007054844A2
WO2007054844A2 PCT/IB2006/053890 IB2006053890W WO2007054844A2 WO 2007054844 A2 WO2007054844 A2 WO 2007054844A2 IB 2006053890 W IB2006053890 W IB 2006053890W WO 2007054844 A2 WO2007054844 A2 WO 2007054844A2
Authority
WO
WIPO (PCT)
Prior art keywords
fin
contact
effect transistor
gate
field effect
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/IB2006/053890
Other languages
English (en)
Other versions
WO2007054844A3 (fr
Inventor
Gilberto A. Curatola
Radu Surdeanu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Koninklijke Philips NV
NXP BV
Original Assignee
NXP BV
Koninklijke Philips Electronics NV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NXP BV, Koninklijke Philips Electronics NV filed Critical NXP BV
Publication of WO2007054844A2 publication Critical patent/WO2007054844A2/fr
Publication of WO2007054844A3 publication Critical patent/WO2007054844A3/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/63—Vertical IGFETs
    • H10D30/635—Vertical IGFETs having no inversion channels, e.g. vertical accumulation channel FETs [ACCUFET] or normally-on vertical IGFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/025—Manufacture or treatment of FETs having insulated gates [IGFET] of vertical IGFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/63—Vertical IGFETs

Definitions

  • the invention relates to a FINFET (field effect transistor) and a method of manufacture.
  • the doping needed for such devices combined with the short channel length results in device characteristics which can be seriously degraded, known as the "short channel effect".
  • FIG. 1 illustrates a FINFET.
  • Substrate 10 has a plurality of fins 12 extending vertically from the substrate and laterally across the substrate. The fins extend longitudinally in the direction into the page of Figure 1. The fins are separated by buried oxide (BOX) layer 14.
  • a gate dielectric 16 extends over the top of each fin 12 between the BOX layers 14, and a gate 18 extends over the gate dielectric.
  • Source and drain contacts are provided on either end of the gate 18 and the gate controls conduction between source and drain.
  • a common gate voltage may be applied to all gate electrodes in parallel.
  • inversion layers are formed on either side of the fin, controlled by the two gates one on either side.
  • the use of two gates instead of one reduces the short channel effect. Further the provision of two inversion layers, one on either side of the fin, can increase current carrying capacity.
  • US2005/0035399. Another similar structure and manufacturing method is described in US2005/0035399. Again, the structure is difficult to fabricate to precise dimensions. US2005/0035399 deals with this by providing a central semiconducting region in each body region to reduce the channel thickness in spite of the thick fin. It would however be more beneficial to provide a method and device with narrower bodies to increase the integration density.
  • a gold nanoparticle on a substrate is used as a mask to form a nanopillar.
  • a gate stack is deposited, the nanopillar removed to form a hole and a gate conductor, gate dielectric and semiconductor channel formed within the hole, with the channel in the centre.
  • a vertical transistor is thus formed, with the base of the channel connected through a highly doped region of the substrate and the top of the channel formed to have a source or drain contact.
  • the method allows a fin FET to be fabricated at reduced cost compared to alternative methods. Further, the resulting structure has the advantage that the separate contacts on either side of the fin allow the FET to be operated in either a symmetric or an asymmetric configuration.
  • the step of fabricating at least one semiconductor fin may conveniently be carried out by etching the first major surface to form the at least one semiconductor fin.
  • the method may further form an oxide layer at the base of the fin on either side of the fin. This keeps the gate spaced from the substrate on either side of the fin so that when a voltage is applied to the gate the voltage creates an inversion layer in the fin but not the substrate on either side of the fin.
  • the method may further include implanting a dopant to form a source/drain implant at the top of the fin. This may be carried out before forming the gate dielectric which can reduce damage caused by the implantation step in the subsequently formed structure.
  • the step of etching back the top of the fin includes carrying out a chemical mechanical polishing step.
  • the method may further include etching the gate dielectric and the gate material from the top of the sides of the fin, after the step of etching back the top of the fin. This separates the gate from the contact at the top of the fin in the finished structure.
  • the method may further include depositing oxide on either side of the fin to the top of the fin after etching back the top of the fin. This protects the device while the next step is carried out.
  • the step of forming a contact at the top of the fin may be carried out by growing a silicon epilayer on the exposed semiconductor at the top of the fin, and suiciding the silicon epilayer to form the contact of suicide.
  • the invention also relates to a fin FET as set out in claim 9.
  • an array of fin FETs is provided.
  • the fin FETs may have a common contact to the base of the fins and separate contacts to the top of each fin.
  • Figure 1 shows a prior art FINFET
  • Figures 2 to 7 show stages in the manufacture of a FINFET according to a first embodiment of the invention; and Figure 8 illustrates a second embodiment of the invention.
  • a semiconductor substrate 10 is provided having a first major surface 20.
  • a fin 12 is patterned by etching the first major surface 20. The fin 12 extends into the substrate 10 from the first major surface and extends longitudinally.
  • a deep implantation step is carried out to deposit a source or drain implant 24 at the base of the fins, as illustrated schematically by the arrows 28 indicating the implantation in Figure 2 and resulting drain contact 30.
  • a gate dielectric layer 16 is then deposited over the whole of the first major surface.
  • the gate dielectric layer 16 may be of silicon oxide, silicon nitride, silicon oxynitride, a medium k material or a high k material.
  • a metal gate 18 is then deposited over the whole surface and patterned as illustrated in Figure 3.
  • a chemical-mechanical polishing step is carried out to remove the top of the fin 12, and a timed selective etch-back carried out to remove the gate dielectric 16 and gate metal 18 from the upper region 30 of the fin 12, leaving the fin exposed in the upper region 30, as illustrated in Figure 4, and the gate metal divided into a first gate 42 and a second gate 44 on opposed sides of the fin 12.
  • Oxide 32 is then grown up to the top of each fin leaving the top 34 of each fin 12 exposed. If required, oxide can be grown over the whole surface and then selectively etched back to expose the top 34 of the fin.
  • a silicon epilayer 35 is selectively grown on the exposed top 34 of each fin, resulting in the structure shown in Figure 5.
  • the silicon epilayer 35 is then suicided to form a suicide source layer 36.
  • a source contacts 38 to the suicide layer are formed.
  • First and second gate contacts 46, 48 are provided to contact the respective first and second gates 42,44 on respective opposed sides of the fin. Note that care is taken to avoid a short between the gate contacts 46,48 and the suicide source layer 36 or source contact 38.
  • a substrate contact 40 in contact with drain region 24 is then formed, adjacent to the fin, as illustrated in Figure 6 which is a side section of Figure 5 showing the length of the fin 12 in the horizontal direction.
  • the structure delivers a vertical FINFET with all the advantages of reduced short channel effects.
  • the semiconductor in the fin can be undoped because of quantum confinement effects in the fin, which leads to improved mobility.
  • the fabrication process is cheap compared to silicon-on- insulator devices.
  • the buried oxide layer can be fabricated using normal oxidation processes.
  • the source and drain resistance can be a very significant factor leading to poor device performance.
  • the source and drain contacts are no longer affected by the length of the source and drain regions of the fin which can greatly improve (reduce) the series resistance.
  • the separate gate contacts 46, 48 on either side of the fin can be separately controlled to allow the FINFET to be operated symmetrically or asymmetrically.
  • a plurality of FINFETs are connected to one another as illustrated in Figure 8.
  • Figure 8 also shows a further alternative.
  • the deep implantation 24 extends through the full thickness of substrate 10 and the drain contact 40 is provided on the rear of the substrate instead of the source.
  • the bulk drain contact 40 can be used as a common contact for each of a plurality of FINFETs on a wafer, with the individual source/drain contacts 38 being connected individually or in parallel depending on the application.

Landscapes

  • Thin Film Transistor (AREA)

Abstract

L'invention concerne un transistor FET à ailette qui inclut au moins une ailette semiconductrice (12) s'étendant dans une direction verticale, un diélectrique de grille (16) sur les flancs de l'ailette (12) et une paire de grilles opposées (42, 44) sur l'un ou l'autre côté de l'ailette. Des contacts de source et de drain (38, 40) sont prévus sur le sommet et sur le fond de l'ailette (12). Un réseau de transistors FET à ailette peut inclure un contact commun au niveau de la base de l'ailette et des contacts séparés au sommet de l'ailette. L'invention concerne un procédé de fabrication du transistor FET à ailette.
PCT/IB2006/053890 2005-11-14 2006-10-23 Transistor fet a ailette et procede de fabrication Ceased WO2007054844A2 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP05110721.7 2005-11-14
EP05110721 2005-11-14

Publications (2)

Publication Number Publication Date
WO2007054844A2 true WO2007054844A2 (fr) 2007-05-18
WO2007054844A3 WO2007054844A3 (fr) 2007-11-22

Family

ID=37831673

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/IB2006/053890 Ceased WO2007054844A2 (fr) 2005-11-14 2006-10-23 Transistor fet a ailette et procede de fabrication

Country Status (1)

Country Link
WO (1) WO2007054844A2 (fr)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI566403B (zh) * 2012-06-14 2017-01-11 聯華電子股份有限公司 場效電晶體及其製造方法
CN106601618A (zh) * 2015-10-15 2017-04-26 中芯国际集成电路制造(上海)有限公司 一种半导体器件及其制造方法和电子装置
US9871123B2 (en) 2012-06-14 2018-01-16 United Microelectronics Corp. Field effect transistor and manufacturing method thereof

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19846063A1 (de) * 1998-10-07 2000-04-20 Forschungszentrum Juelich Gmbh Verfahren zur Herstellung eines Double-Gate MOSFETs
US7372091B2 (en) * 2004-01-27 2008-05-13 Micron Technology, Inc. Selective epitaxy vertical integrated circuit components

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI566403B (zh) * 2012-06-14 2017-01-11 聯華電子股份有限公司 場效電晶體及其製造方法
US9871123B2 (en) 2012-06-14 2018-01-16 United Microelectronics Corp. Field effect transistor and manufacturing method thereof
CN106601618A (zh) * 2015-10-15 2017-04-26 中芯国际集成电路制造(上海)有限公司 一种半导体器件及其制造方法和电子装置
CN106601618B (zh) * 2015-10-15 2019-12-10 中芯国际集成电路制造(上海)有限公司 一种半导体器件及其制造方法和电子装置

Also Published As

Publication number Publication date
WO2007054844A3 (fr) 2007-11-22

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