WO2007049199A1

WO2007049199A1 - Electronic device for receiving rf signals and method for rf sampling

Info

Publication number: WO2007049199A1
Application number: PCT/IB2006/053855
Authority: WO
Inventors: Xuecheng Qian
Original assignee: NXP BV; Koninklijke Philips Electronics NV
Current assignee: Koninklijke Philips NV; NXP BV
Priority date: 2005-10-26
Filing date: 2006-10-19
Publication date: 2007-05-03
Anticipated expiration: 2008-04-26
Also published as: TW200740132A

Abstract

An electronic device is provided with RF filter (RFF) for receiving a RF signal and for filtering the received RF signal; low-noise amplifier unit (LNA) for amplifying the filtered RF signal; and a transconductor unit (Gm) for converting the RF signal into a current signal. Furthermore, a first switch unit (Sl) is provided which is controlled by a first clock signal (φl) for periodically integrating the current signal. A first capacitance (Ch) is charged in accordance with the first clock signal (φl). A second capacitance (Co; Cm) is provided for sharing the charge on the first capacitance (Ch). A second switch unit (S2) is controlled by a second clock signal (φ2) and is coupled between the first and second capacitance (Ch; Co; Cm). The charge on the first capacitance (Ch) is shared with the second capacitance (Co; Cm) if the second switch unit (S2) is activated by the second clock signal (φ2).

Description

Electronic device for receiving RF signals and method for RF sampling.

Field of the invention

The present invention relates to an electronic device for receiving RF signals, and a method for RF sampling.

Background of the invention

Typical wireless receivers are designed on a continuous-time basis for performing a down-conversion of the received radio frequency RF signal as well as a sufficient filtering. In order to implement low-cost receivers the analog circuits have to share the same die as low-cost digital signal processing circuits. Nowadays, receiver architecture using radio frequency (RF) the sampling is very attractive because of its high flexibility for reconfiguration and its suitability for using same silicon process for both analog and digital circuitries. Fig.l shows a block diagram of an example of such a receiver architecture according to the prior art. The receiver comprises an antenna, RF filters RFF, a low-noise amplifier LNA, a switch operated at the clock frequency CIk, discrete filters DF, an analog/digital conversion ADC and a subsequent digital signal processing DSP. The analog RF signal received from antenna is sampled directly after limited RF filtering and amplification. Usually, the signal as received by the antenna does not only comprise wanted signal, but also wideband interference, and RF filters have limited selectivity on out-of-band interference. Therefore, the required sampling rate must be very high in order to avoid aliasing of interference into the wanted signal band.

However, as the required sampling rate of a RF-sampling receiver is very high, a high power dissipation is resulted. Normally, the more circuits operate at high frequency, the higher power dissipation of the receiver. This is the main reason that traditional RF-sampling receiver does not have wide applications.

In "A 3-V 230-MHz CMOS Decimation Subsampler", by

Saska Lindfors, Aarno Parssinen, Kari A. I. Halonen; IEEE Trans, on Circuits and Systems-II: Analog and Digital Signal Processing, vol.50, No.3, March 2003, a finite- impulse-response (FIR) decimation filter is used to decrease the sampling rate in a voltage-sampling receiver. Nevertheless, the circuit architecture is quite complicated compared with traditional sampler.

In a charge-sampling receiver, the analog voltage input signal is firstly converted into a current signal, and then the current signal is used to charge a capacitor during a certain period. By summing up charges in consecutive periods, an equivalent decimation FIR filter is formed and therefore, the output is at a lower sampling rate.

This charge-sampling technique is shown in "A Charge Sampling Mixer with Embedded Filter Function for Wireless Applications", by Jiren Yuan; IEEE 2000 2nd International conference on microwave and millimeter wave technology proceedings; and in WO 01/24192, "Versatile charge sampling circuits" as well as in "A discrete-time Bluetooth receiver in a 0.13/spl mu/m digital CMOS process", by Muhammad K. Leipold, et al, IEEE International So lid-State Circuits Conference (ISSCC), vol.l, pp.268-527 February 15-19 2004.

However, since the notches formed by the FIR filter are normally not very wide, the decimation ratio cannot be very large. Muhammad, K et al suggest to use analog infinite-impulse-response (HR) and FIR filters to suppress the out-of-band interference before the signal is further down-sampled. However, the required circuitry is also very complicated and a great number of clock signals are required which will increase the cost, and the power dissipation of the circuits.

In "Direct RF Sampling Mixer with Recursive Filtering in Charge Domain", by Muhammad et al, in ISCAS 2004, an HR filter is realized based on a charge sharing between history capacitor Ch and a couple of rotating capacitors Cr. US 2005/0025268 shows two lst-order HR filters and an embedded

FIR filter within a RF receiver. A 1st HR filter is achieved by charge sharing between a history capacitor Ch and different rotating capacitors Cr. A 2nd HR filter is achieved by charge sharing between rotating capacitors Cr and output capacitor Cb. The embedded FIR filter is formed by charge sharing between rotating capacitors Cr. Accordingly, the decimation rate (n) at this stage is fixed to the half number of rotating capacitors. In particular, 3+4n switches, 2n flip-flops, and 2n+2 capacitors (Ch+2nCr+Cb) are required and the circuitry needs to be reconfigured for different applications when the required decimation rate n differs. One simple way of reconfiguration can be performed by providing different sampler pipes for different application, however this will increase the cost because of the duplicated capacitors, flip-flops, and switches.

Summary of the invention

It is an object of the invention to provide an electronic device for receiving RF signals with a RF sampling as well as a method for RF sampling at lower cost and with less complexity.

This object is solved by an electronic device according to claim 1 a method according to claim 7 and by a receiver according to claim 8.

Therefore, an electronic device is provided comprising RF filter for receiving a RF signal and for filtering the received RF signal, a low-noise amplifier unit for amplifying the filtered RF signal; and a transconductor unit for converting the RF signal into a current signal. Furthermore, a first switch unit is provided and is controlled by a first clock signal for periodically integrating the current signal. A first capacitor is charged in accordance with the first clock signal. A second capacitor is provided for sharing the charge on the first capacitors. A second switch unit is controlled by a second clock signal and is coupled between the first and second capacitors. The charge on the first capacitor is shared with the second capacitor if the second switch unit is activated by the second clock signal

Accordingly, merely one output capacitor is used for a large range of decimation rates due to the big selectivity of the 2nd-order HR filter. If the output capacitor is divided into two smaller capacitors, an even larger range of decimation ratios can be expected. A further advantage constitutes the lower power dissipation due to the simpler circuits and less clock signals required. By switching the second switching unit a 1^st order HR filter is achieved, i.e. by periodic charge sharing between the first and second capacitance.

According to an aspect of the invention a third capacitor is coupled to the second capacitor, and a third switch unit is coupled between the third and second capacitor . The charge on the second capacitor is shared with the third capacitor if the third switch unit is activated by the third clock signal.

The invention also relates to a method for sampling a RF signal. A RF signal is received and filtered, the filtered RF signal is amplified, and the RF signal is converted into a current signal. A first switch unit is switched controlled by a first clock signal for periodically integrating the current signal. A first capacitor is charged in accordance to the first clock signal. The charge on the first capacitor is shared by a second capacitor, and a second switch unit is switched controlled by a second clock signal and is coupled between the first and second capacitor. The charge on the first capacitor is shared with the second capacitor if the second switch unit is activated by the second clock signal

The invention further relates to a wireless receiver corresponding to the above mentioned electronic device. As compared to the prior art, no rotating capacitors Cr are required such that the receiver can be implemented at lower cost as capacitors are expensive in silicon and the cost does not decrease much with the scaling down of silicon technologies. Furthermore, merely 4 switches, and 3 capacitors (Ch+Cm+Co) are required for implementing the same function as compared to the prior art. In addition a much higher flexibility for reconfiguration is achieved.

The required sampling rate is typically very high, and therefore a high power dissipation is present. The radio frequency (RF) sampling receiver architecture according to the invention is advantageous because of its high flexibility for reconfiguration and suitability for use with the same silicon process for both RF and base band circuits. According to the invention, very efficient methods of RF sampling are provided. Although the analog signal is originally sampled at a high rate, the data rate is immediately decreased by using very simple decimation filters. The sampling rate after the decimation filters is significantly lower than the original sampling rate, such that the power dissipation of this sampler is also significantly lower than traditional RF samplers.

The architectures according to the invention use simple discrete filters to achieve a high selectivity. It uses the charge-sampling technique to decrease the sampler noise and simplify the FIR decimation filter. Then, very simple lst-order or 2nd-order HR filters are employed to suppress the out-of-band interference before further decimation. Finally, simple down-sampling architecture is used to decrease the sampling frequency. The overall circuit consists of very few capacitors, switches, and necessary down-sampling circuits. Additionally, it needs very few clock signals. Therefore, the lower complicity and a reduced power dissipation of this sampler is present.

Brief description of the drawings The invention is now described in more detail with reference to the drawings:

Fig.1 shows a block diagram of an example of a receiver according to the prior art; Fig.2 shows a block diagram of a receiver according to a first embodiment and a timing diagram of the receiver; Fig.3 shows a graph illustrating a normalized amplitude response of a

FIR filter of a receiver of Fig.2A;

Fig.4 shows a graph illustrating a response of an HR filter of Fig.2A for different capacitance ratios;

Fig.5 shows a block diagram of a receiver according to a second embodiment and a timing diagram of the receiver; Fig.6 shows a block diagram of a receiver according to a third embodiment and a timing diagram of the receiver; Fig.7A and 7B show a block diagram of a down-sampling circuit by voltage tracking and by current integration, respectively; Fig.8 shows a block diagram of a receiver according to the first embodiment of Fig.2A with voltage tracking for down sampling and a timing diagram of the receiver; Fig.9 shows a block diagram of a receiver according to the second embodiment of Fig.5 A with voltage tracking for down sampling and a timing diagram of the receiver; Fig.10 shows a block diagram of a receiver according to the third embodiment of Fig.βA with voltage tracking for down sampling and a timing diagram of the receiver;

Fig.11 shows a block diagram of a receiver according to the first embodiment of Fig.2A with current integration for down sampling and a timing diagram of the receiver; Fig.12 shows a block diagram of a receiver according to the second embodiment of Fig.5 A with current integration for down sampling and a timing diagram of the receiver; and

Fig.13 shows a block diagram of a receiver according to the third embodiment of Fig.βA with current integration for down sampling; and a timing diagram of the receiver.

Description of the preferred embodiments

Fig.2 shows a block diagram of a receiver according to a first embodiment, and a timing diagram of the receiver. The RF receiver comprises an antenna ANT, RF filter RFF, a low noise amplifier LNA, a transconductor unit Gm, a first switch Sl controlled by a first clock signal φl, a hold capacitor Ch, a second switch S2 controlled by a second clock signal φ2, an output capacitor Co, and a first reset switch Srh controlled by a first reset clock signal φrh. The first switch Sl is coupled between the transconductor unit Gm and the hold capacitor Ch. The second switch S2 is coupled between the hold capacitor Ch and the output capacitor Co. The first reset switch Srh is coupled in parallel to the hold capacitor Ch.

In Fig.2 the relation between the first, second clock signal and a first reset clock φl, φ2, φrh is depicted. The time period Ti corresponds the first clock signal being on a high level and the time period Ts corresponds to the clock cycle of the first clock signal φl. The time To for an output corresponds to the time period between a falling edge and the next rising edge of the second clock signal φ2. The first reset clock signal φrh is used to reset the capacitor Ch.

The input signal from antenna ANT is first passed through RF filters RFF and the low-noise amplifier LNA. Thereafter, input signal V_1n is converted into the current signal by a transconductor unit Gm. The current signal is integrated periodically into the hold capacitor Ch at the rate fs by switching the first switch at a rate of f_s. The capacitor Ch is charged during a time period Ti when the first clock signal φl is at high level. The rate fs corresponds to the sampling frequency and should be high enough in order to avoid the aliasing of interference into wanted signal band. By adding up n consecutive charges, a n-tap FIR (finite-impulse-response) filter is formed. The response of this FIR filter is

where: T_s = — .

The second switch S2 is switched at a rate of fs/n such that a first-order IIR (infinite-impulse-response) filter is formed by the periodic charge sharing between the history capacitor Ch and the output capacitor Co. Accordingly, a RF sampler is formed with a FIR decimation filter (the first switch Sl and the capacitor Ch) and a 1^st order input-reset IIR filter (capacitor Ch, switch S2, capacitor Co and switch Srh).

Fig.3 shows a graph illustrating a normalized amplitude response of a FIR filter of the receiver of Fig.2. Here, n equals to 8 as an example for illustrating the function of the FIR filter. The resulted decimation does not cause a strong aliasing of interference into wanted signal band for sufficiently small n because of the notches in the spectrum response of this FIR filter. The output of the FIR filter operate at a rate of fs/n. The summation of n charges on the capacitor Ch (the first switch Sl has switched n times) is then shared with the output capacitor Co when the second clock signal φ2 is high and the second switch S2 is closed. Accordingly, the resulting charge sharing forms a lst-order infinite-impulse-response (IIR) filter operating at the rate of fs/n.

The response of this IIR filter corresponds to

V_n (z) a aZ

H(Jw) =

Q_n (z) 1 - βZ T -^"I¹ Z - β Z=e^]w

where: α =

C + C

β = c_h ^C +c₀

The normalized frequency response depends a great deal on β, and

C C therefore the ratio — - . A higher ratio — - , will result in a higher zero-frequency gain.

C C

Before the next charging period, the first reset clock signal φrh controls the first reset switch Srh to reset the voltage over the hold capacitor Ch to zero. Fig.4 shows a graph illustrating a response of the HR filter of Fig.2 for different capacitance ratios. Here, examples of the normalized response are shown for the capacitance ratios 10, 40, 100, and 200, respectively.

Fig.5 shows a block diagram of a receiver according to a second embodiment, and a timing diagram of the receiver. As in the first embodiment the RF receiver comprises an antenna ANT, RF filter RFF, a low noise amplifier LNA, a transconductor unit Gm, a first switch Sl controlled by a first clock signal φl, a hold capacitor Ch, a second switch S2 controlled by a second clock signal φ2, an output capacitor Co, and a second reset switch Sro controlled by a second reset clock signal φro. The first switch Sl is coupled between the transconductor unit Gm and the hold capacitor Ch. The second switch S2 is coupled between the hold capacitor Ch and the output capacitor Co. The second reset switch Sro is coupled in parallel to the output capacitor Co. Accordingly, the second switch S2 corresponds to the second switch S2 according to Fig.2. The time To for an output corresponds to the time period between a falling edge of the second clock signal φ2 and a rising edge of the second reset clock signal φro.

In Fig.5 the relation between the first, second clock φl, φ2, and a second reset clock signal φro is depicted. The time period Ti corresponds the first clock signal φl being on a high level and the time period Ts corresponds to the clock cycle of the first clock signal φl. The first clock signal here corresponds to the first clock of Fig.2.

The input signal from antenna ANT is first passed through RF filters RFF and low-noise amplifier LNA. Thereafter, input signal V_1n is converted into the current signal by a transconductor unit Gm. The current signal is integrated periodically into the hold capacitor Ch at the rate fs by switching the first switch at a rate of f_s. The capacitor Ch is charged during a time period Ti when the first clock signal φl is at high level. The rate fs corresponds to the sampling frequency and should be high enough in order to avoid the aliasing of interference into wanted signal band. By adding up n consecutive charges, a n-tap FIR filter is formed. The response of this FIR filter corresponds to

1 where : T_s

The second switch S2 is switched at a rate of fs/n such that a first-order IIR (infinite-impulse-response) filter is formed by the periodic charge sharing between the history capacitor Ch and the output capacitor Co. Accordingly, a RF sampler is formed with a FIR decimation filter (the first switch Sl and the capacitor Ch) and a 1^st order output-reset IIR filter (capacitor Ch, switch S2, capacitor Co and reset switch Sro). The sum of n consecutive charges on the hold capacitor Ch is then shared with the output capacitor Co when the second clock signal φ2 is high. This charge sharing forms a lst-order IIR filter operating at the rate of fs/n. The response of this IIR filter is

C₁, where α = , β =

C + C C + C The normalized frequency response depends a great deal on β, and

C C therefore the ratio the ratio — - . A higher ratio — - , will result in a higher zero-

C₀ C₀ frequency gain. Before the next charging period, the second reset clock signal φro controls the second reset switch Sro to reset the voltage over the output capacitor Co to zero. The time To for an output corresponds to the time period between a falling edge of the second clock signal φ2 and the next rising edge of the reset clock signal φro.

Fig.6 shows a block diagram of a receiver according to a third embodiment, and a timing diagram of the receiver. Here, the RF sampler is depicted with FIR decimation filter and the 2nd-order IIR filter. As in the first and second embodiment the RF receiver comprises an antenna ANT, RF filter RFF, a low noise amplifier LNA, a transconductor unit Gm, a first switch S 1 controlled by a first clock signal φl, a hold capacitor Ch, a second switch S2 controlled by a second clock signal φ2, an output capacitor Co, a third switch S3 controlled by a third clock signal φ3, an intermediate capacitor Cm and a third reset switch Srm controlled by the third reset clock signal φrm. The first switch Sl is coupled between the transconductor unit Gm and the hold capacitor Ch. The second switch S2 is coupled between the hold capacitor Ch and the intermediate capacitor Cm. The third reset switch Srm is coupled in parallel to the intermediate capacitor Cm. The third switch S3 is coupled between the intermediate capacitor Cm and the output capacitor Co.

In Fig.6 the relation between the first, second and third clock φl, φ2, φ3 and the third reset clock signal φrm is depicted. The time period Ti corresponds the first clock signal being on a high level and the time period Ts corresponds to the clock cycle of the first clock signal φl. The first clock signal here corresponds to the first clock of Fig.2.

The input signal from antenna ANT at first passes through RF filters RFF and low-noise amplifier LNA. Thereafter, input signal is converted into the current signal by a transconductor unit Gm. The mechanism of the FIR filter is same as those according to Fig.2 and 5 The current signal is integrated periodically into the hold capacitor Ch at the rate of fs by switching the first switch at a rate of f_s. The capacitor Ch is charged during a time period Ti when the first clock signal φl is at high level. The rate fs corresponds to the sampling frequency and should be high enough in order to avoid the aliasing of interference into wanted signal band. By adding up n consecutive charges, a n-tap FIR filter is formed. The response of this FIR filter is

where : T_s = — .

The output of the FIR filter is of the rate fs/n. The sum of n consecutive charges on Ch is then shared with the intermediate capacitor Cm when the second clock signal φ2 is high. This charge sharing forms a lst-order HR filter operating at the rate of fs/n. The response of this HR filter is

C₁, where : α = , β = c_h + c_m c_h + c_m

The normalized frequency response depends a great deal on β, and therefore the ratio

C C the ratio — — . A higher ratio of — — , will result in a higher zero-frequency gain.

The charge on capacitor Cm is then shared with the output capacitor Co when the third clock signal φ3 is high. This charge sharing forms another lst-order IIR filter operating at the rate of fs/n. The response of this HR filter is

C C where : q = ^m , p = ^■ c_m + c₀ c_m + c₀ c

The normalized frequency response depends on p, and therefore the ratio — — . A

C_m

C higher ratio — — , results in a higher the zero-frequency gain. The third reset clock

signal φrm controls the third reset switch Srm to reset the voltage on capacitor Cm to zero before the next charge sharing occurs between Ch and Cm. The time To for an output corresponds to the time period between a falling edge and the next rising edge of the third clock signal φ3.

Fig.7A and 7B show a block diagram of a down-sampling circuit by voltage tracking and by current integration, respectively. As the lst-order IIR filters according to Fig.2, Fig.5 and the 2^nd-order IIR filter according to Fig.6 operate at the rate of fs/n while suppressing the out-of-band interference, their outputs can be down- sampled to a lower rate if the aliasing is insignificant. The down-sampling could be implemented by either circuit in of Fig.7A or 7B Fig.8 shows a block diagram of a receiver according to the first embodiment of Fig.2 with voltage tracking for down sampling and a timing diagram of the receiver of Fig.8. In particular a RF sampler with FIR decimation filter, a lst- order input-reset HR filter, and a voltage tracking circuit is shown. The sampler of Fig.8 is based on the sampler of Fig.2 with an additional down-sampling circuit implemented by a voltage tracking unit Ao, an additional fourth switch S4 controlled by a fourth clock signal φ4 and a further capacitor Coh. The fourth switch S4 is operated at a rate of fs/n/m. The time for the output of the HR filter corresponds to the time period between a m-th falling edge of the second clock signal φ2 and the following 1^st rising edge of the second clock signal φ2. The period tχ_r is the time available for the tracking unit Ao to track the output signal of the HR filter. Hence, tχ_r shall be within the time period for HR output IIRO. The time To for an output corresponds to the time period between a falling edge and the next rising edge of the fourth clock signal φ4. Fig.9 shows a block diagram of a receiver according to the second embodiment of Fig.5 with voltage tracking for down sampling and a timing diagram of the receiver. In particular, a RF sampler with FIR decimation filter, a lst-order output-resetting HR, and a voltage tracking circuit is shown. The sampler of Fig.9 is based on the sampler of Fig.5 with an additional down-sampling circuit implemented by a voltage tracking unit Ao, an additional fourth switch S4 controlled by a fourth clock signal φ4 and a further capacitor Coh. The fourth switch S4 is operated at a rate of fs/n/m. The time for the output of the HR filter corresponds to the time period between a m-th falling edge and the following 1^st rising edge of the third clock signal φ3. The period tχ_r is the time available for the tracking unit Ao to track the output signal of HR filter. Hence, tχ_r shall be within the time period for HR output IIRO. The time To for an output corresponds to the time period between a falling edge and the next rising edge of the fourth clock signal φ4.

Fig.10 shows a block diagram of a receiver according to the third embodiment of Fig.6 with voltage tracking for down sampling and a timing diagram of the receiver. In particular, a sampler with FIR decimation filter, a 2nd-order HR, and a voltage tracking circuit is shown. The sampler of Fig.10 is based on the sampler of Fig.6 with an additional down-sampling circuit implemented by a voltage tracking unit Ao, an additional fourth switch S4 controlled by a fourth clock signal φ4 and a further capacitor Coh. The fifth switch S5 is operated at a rate of fs/n/m. The time for the output of the HR filter corresponds to the time period between a m-th falling edge and the following 1^st rising edge of the third clock signal φ3. The period tχ_r is the time available for the tracking unit Ao to track the output signal of HR filter. Hence, tχ_r shall be within the time period for HR output IIRO. The time To for an output corresponds to the time period between a falling edge and the next rising edge of the fourth clock signal φ4.

Fig.11 shows a block diagram of a receiver according to the first embodiment of Fig.2 with current integration for down sampling and a timing diagram of the receiver. In particular a RF sampler with FIR decimation filter, a lst-order input-reset HR filter, and a current integration circuit is shown. The sampler of Fig.11 is based on the sampler of Fig.2 with an additional transconductor unit Gm, additional down-sampling circuit implemented by current integration unit with an additional fourth switch S4 controlled by a fourth clock signal φ4, a further capacitor Coh and a fifth switch S5 controlled by a fifth clock signal φ5, wherein the fifth switch is coupled in parallel to the capacitor Coh. The fourth switch S4 is operated at a rate of fs/n/m. The time for the output of the HR filter corresponds to the time period between a m-th falling edge and the following 1^st rising edge of the second clock signal φ2. The period tc is the time available for capacitor to be charged. Hence, tc is within the time period for HR output IIRO. The time To for an output corresponds to the time period between a falling edge of the fourth clock signal φ4 and the following rising edge of the fifth clock signal φ5. The voltage on the output capacitor Coh shall be reset to 0 before it is charged in the next period.

Fig.12 shows a block diagram of a receiver according to the second embodiment of Fig.5 with current integration for down sampling and a timing diagram of the receiver of Fig.12. In particular, a RF sampler with FIR decimation filter, a lst- order output-resetting HR, and a current integration circuit is shown. The sampler of Fig.12 is based on the sampler of Fig.5 with an additional down-sampling circuit implemented by current integration unit with an additional transconductor unit Gm, additional fourth switch S4 controlled by a fourth clock signal φ4, a further capacitor Coh, and a fifth switch unit S5 controlled by a fifth clock signal φ5 . The fourth switch S4 is operated at a rate of fs/n/m. The time for the output of the HR filter corresponds to the time period between a m-th falling edge and the following 1^st rising edge of the second clock signal φ2. The period tc is the time available for capacitor to be charged. The time To for an output corresponds to the time period between a falling edge of the fourth clock signal φ4 and the following rising edge of the fifth clock signal φ5. The voltage on the output capacitor Coh shall be reset to 0 before it is charged in the next period.

Fig.13 shows a block diagram of a receiver according to the third embodiment of Fig.6 with current integration for down sampling and a timing diagram of the receiver of Fig.13. In particular, a sampler with FIR decimation filter, a 2nd- order HR, and a current integration circuit is shown. The sampler of Fig.13 is based on the sampler of Fig.6 with an additional down-sampling circuit implemented by current integration unit with an additional transconductor unit Gm, an additional fourth switch

54 controlled by a fourth clock signal φ4, a further capacitor Coh, and a fifth switch

55 controlled by a fifth clock signal φ5. The fourth switch S4 is operated at a rate of fs/n/m. The time for the output of the HR filter corresponds to the time period between a m-th falling edge and the following 1^st rising edge of the third clock signal φ3. The period tc is the time available for capacitor to be charged. Hence, tc is within the time period for HR output IIRO. The time To for an output corresponds to the time period between a falling edge of the fourth clock signal φ4 and a rising edge of the fifth clock signal φ5. The voltage on the output capacitor Coh shall be reset to 0 before it is charged in the next period.

The above described receivers can be implemented in all RF-sampling receivers e.g. for wireless communications.

It should be noted that the above-mentioned embodiments illustrate rather than limit the invention, and that those skilled in the art will be able to design many alternative embodiments without departing from the scope of the appended claims. In the claims, any reference signs placed between parentheses shall not be construed as limiting the claim. The word "comprising" does not exclude the presence of elements or steps other than those listed in a claim. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. In the device claim enumerating several means, several of these means can be embodied by one and the same item of hardware. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage.

Furthermore, any reference signs in the claims shall not be constrained as limiting the scope of the claims.

Claims

CLAIMS:

1. Electronic device for receiving radio frequency RF signals, comprising: RF filter (RFF) for receiving a RF signal and for filtering the received

RF signal; a low-noise amplifier unit (LNA) for amplifying the filtered RF signal; a transconductor unit (Gm) for converting the RF signal into a current signal; a first switch unit (Sl) controlled by a first clock signal (φl) for periodically integrating the current signal; a first capacitance (Ch) being charged in accordance with the first clock signal (φl); a second capacitance (Co; Cm) for sharing the charge on the first capacitance (Ch), and a second switch unit (S2) controlled by a second clock signal (φ2) being coupled between the first and second capacitance (Ch; Co; Cm); wherein the charge on the first capacitance (Ch) is shared with the second capacitance (Co; Cm) if the second switch unit (S2) is activated by the second clock signal (φ2).

2. Electronic device according to claim 1, further comprising: a third capacitance (Co) coupled to the second capacitance (Cm), and a third switch unit (S3) controlled by a third clock signal (φ3) and coupled between the third and second capacitance (Co; Cm), wherein the charge on the second capacitance (Cm) is shared with the third capacitance (Co) if the third switch unit (S3) is activated by the third clock signal (φ3).

3. Electronic device according to claim 1 or 2, further comprising: a reset switch unit (Srh; Sro; Srm), being coupled in parallel to the first, second or third capacitance (Ch, Cm; Co) and controlled by a first, second or third reset clock signal (φrh, φro, φrm) for resetting the first, second or third capacitance (Ch, Cm; Co).

4. Electronic device according to claim 2, wherein the frequency of the second clock signal (φ2) and/or the frequency of the third clock signal (φ3) correspond to the frequency of the first clock signal (φl) divided by an integer n.

5. Electronic device according to claim 1 or 2, further comprising a down-sampling circuit coupled to the second or third capacitance (Co); said down-sampling circuit having voltage tracking unit (AO), a fourth capacitance (Coh) and a fourth switch unit (S4) coupled between the voltage tracking unit (AO) and the fourth capacitance (S4) and controlled by a fourth clock signal (φ4).

6. Electronic device according to claim 1 or 2, further comprising a down-sampling circuit coupled to the second or third capacitance (Co); said down-sampling circuit having a transconductor unit (Gm), a fourth capacitance (Coh), a fourth switch unit (S4) coupled between transconductor unit (Gm), and the fourth capacitance (S4) and controlled by a fourth clock signal (φ4), and a fifth switch unit (S5) coupled in parallel to the fourth capacitance (Coh) and being controlled by a fifth clock signal (φ5).

7. Method for sampling a radio frequency RF signal, comprising to steps of : receiving and filtering a RF signal; amplifying the filtered RF signal; converting the RF signal into a current signal; switching a first switch unit (Sl) controlled by a first clock signal (φl) for periodically integrating the current signal; charging a first capacitance (Ch) in accordance with the first clock signal (φl); sharing the charge on the first capacitance (Ch) by a second capacitance (Co; Cm) , and switching a second switch unit (S2) controlled by a second clock signal (φ2) being coupled between the first and second capacitance (Ch; Co; Cm); wherein the charge on the first capacitance (Ch) is shared with the second capacitance (Co; Cm) if the second switch unit (S2) is activated by the second clock signal (φ2).

8. Wireless receiver, comprising: RF filter (RFF) for receiving a RF signal and for filtering the received