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WO2006126998A1 - Mosfet a tranchees - Google Patents

Mosfet a tranchees Download PDF

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Publication number
WO2006126998A1
WO2006126998A1 PCT/US2005/018096 US2005018096W WO2006126998A1 WO 2006126998 A1 WO2006126998 A1 WO 2006126998A1 US 2005018096 W US2005018096 W US 2005018096W WO 2006126998 A1 WO2006126998 A1 WO 2006126998A1
Authority
WO
WIPO (PCT)
Prior art keywords
regions
source
region
semiconductor layer
gate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US2005/018096
Other languages
English (en)
Inventor
Deva Pattanayak
Jason Jianhai Qi
Yuming Bai
Kam-Hong Lui
Ronald Wong
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Vishay Siliconix Inc
Original Assignee
Vishay Siliconix Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Vishay Siliconix Inc filed Critical Vishay Siliconix Inc
Priority to JP2008513438A priority Critical patent/JP5350783B2/ja
Priority to PCT/US2005/018096 priority patent/WO2006126998A1/fr
Priority to DE112005003584T priority patent/DE112005003584B4/de
Priority to CN2005800502609A priority patent/CN101208803B/zh
Priority to KR1020077026898A priority patent/KR101047945B1/ko
Publication of WO2006126998A1 publication Critical patent/WO2006126998A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/66—Vertical DMOS [VDMOS] FETs
    • H10D30/668—Vertical DMOS [VDMOS] FETs having trench gate electrodes, e.g. UMOS transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/028—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs
    • H10D30/0291—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs
    • H10D30/0295—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs using recessing of the source electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/028—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs
    • H10D30/0291—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs
    • H10D30/0297—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs using recessing of the gate electrodes, e.g. to form trench gate electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/66—Vertical DMOS [VDMOS] FETs
    • H10D30/664—Inverted VDMOS transistors, i.e. source-down VDMOS transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/393—Body regions of DMOS transistors or IGBTs 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/111—Field plates
    • H10D64/117—Recessed field plates, e.g. trench field plates or buried field plates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/23—Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
    • H10D64/251—Source or drain electrodes for field-effect devices
    • H10D64/252—Source or drain electrodes for field-effect devices for vertical or pseudo-vertical devices
    • H10D64/2527—Source or drain electrodes for field-effect devices for vertical or pseudo-vertical devices for vertical devices wherein the source or drain electrodes are recessed in semiconductor bodies

Definitions

  • Embodiments of this writing relate to metal-oxide-semiconductor field effect transistors (MOSFET), and more particularly to vertical MOSFET devices having a trench gate geometry. This writing discusses drain side gate trench metal-oxide-semiconductor field effect transistor.
  • MOSFET metal-oxide-semiconductor field effect transistors
  • FIG. 1 a cross-sectional perspective view of a striped trench metal-oxide-serniconductor field effect transistor (TMOSFET) 100 according to the conventional art is shown.
  • the striped TMOSFET 100 comprises a plurality of source contacts 110, a plurality of source regions 115, a plurality of gate regions 120, a plurality of gate insulator regions 125, a plurality of body regions 130, a drain region 135, 140 and drain coniact 145.
  • the drain region 135, 140 may optionally include a first drain portion 140 and a second drain portion 135.
  • the body regions 130 are disposed above the drain region 135, 140.
  • The- source regions 115, gate regions 120 and the gate insulator regions 125 are disposed wi ⁇ hin the body regions 130.
  • the gate regions 120 and the gate insulator regions 125 are formed as parallel-elongated structures.
  • the gate insulator region 125 surrounds the-gate region 120.
  • the gate regions 120 arc electrically isolated from the suuoimdiug regions by the gate insulator regions 125-
  • the gate regions 120 are coupled to form a common gate of the device 100 «
  • the source regions 115 are formed as parallel-elongated structures along the periphery of the gate insulator regions 125,
  • the source regions 115 are coupled to form a common source of the device 100, by the source contacts 110.-
  • source contacts 110 may be implemented as a single conductive layer coupling all the source regions 115, The source contacts 110 also couple the source regions 115 to the body regions 130.
  • the source regions 115 and. the drain region 140 are heavily n-doped
  • the body regions 130 are p-doped (P) semiconductor, such as silicon doped with boron.
  • the gate regions 120 are heavily n-doped (N+) semiconductor, such as polysilicon doped with phosphorous.
  • the gate insulator regions 125 may be an insulator, such as silicon dioxide.
  • the drain region 135, 140 comprises a second drain portion 135 disposed above a first drain portion 140, the second portion of the dram region 135 L lightly n-doped (N-) semi-conductor,. sxich as silicon doped with phosphorous or arsenic, and the first portion of the drain tfegion 140 is heavily n-doped (N+) semiconductor, such as silicon doped with phosphorous or arsenic.
  • the lightly n-doped (N-) second portion of the drain region 135 results in a depletion region that extends into both the body ⁇ regions 130 and the second portion of the drain region 135, thereby reducing the punch through effect. Accordingly, the lightly n-doped (N-) second portion of The drain region 135 acts to increase the breakdown voltage of the striped TMOSFET 100.
  • the channel width of the striped TMOSFET 100 is a function of the length of the plurality of the source regions 115.
  • the stiiped TMOSFET 100 provides a large channel width to length ratio. Accordingly, the striped TMOSFET may advantageously be utilized for power MOSFFET applications, such as switching elements
  • TMOSFET closed cell trench metal-oxide-semiconductor field effect transistor
  • the source contacts 210 may optionally include a first drain portion 240 and a second drain portion 235.
  • the body regions 230, the source regions 215, the gate region 220 and the gate insulator region 225 are disposed above the drain region 235, 240.
  • a first po ⁇ ion of the gate region 220 and the gate insulator region 225 is formed as substantially parallel ' elongated structures 221.
  • a second portion of the gate region 220 and the gate insulation region 225 is formed as substantially normal-to-paraliel elongated structures 222.
  • The- - first and second portions of the gate region 220 are all interconnected and form a plurality of cells.
  • the body regions 230 are disposed within the plurality of cells formed by the gate region 220.
  • the gate insulator region 225 surrounds the gate region 220.
  • the gate region 220 is electrically isolated Iron f rom surrounding regions by the gate insuIator region 225.
  • the source regions 215 arc coupled to form a. common source of the device 200, by the source contacts 210. Although shown as a plurality of individual source contacts 210, it is appreciated that the source contacts 210 may be implemented as a plurality of conductive strips each coupling a plurality of source regions 215, a single conductive layer coupling all the source regions 215, or the like. The source contacts 210 also couple The source regions 215 to the body regions 230,
  • the source regions 215 and the drain region 240 are heavily n-doped (+N) semiconductor, such as silicon doped with phosphorous or arsenic.
  • the body regions 230 arc p-doped (P) semiconductor, such as silicon doped with boron.
  • the gate region 220 is heavily n-doped semiconductor (N-I-), such as polysilicon doped with ' phosphorous.
  • the gate insulator region 225 may be an insulator, such as silicon dioxide.
  • the drain region 235, 240 comprises a second portion 235 disposed above a first portion 240, the second portion of the drain region 235 is lightly n-do ⁇ ed 5 (N-) semiconductor, such as silicon doped with phosphorous or arsenic, and the first portion of the drain region 240 is heavily n-doped (N+) semiconductor, such as silicon doped with phosphorous.
  • N- lightly n-do ⁇ ed 5
  • N+ n-doped
  • the lightly n-doped (N-) second portion of the drain region 235 results in a depletion region that extends into both the body regions 230 and the second portion of the drain region 235, thereby reducing the punch through effect fl Accordingly, the lightly n-doped (N-) second portion of the drain region 235 acts to increase the breakdown voltage of the closed cell TMOSFET 200.
  • the channel width of the closed cell TMOSFET 200 is a function of the sum of the width of the source regions 215.
  • the closed cell TMOSFET 200 geometry advantageously increases the width of the channel region, as compared to the S striped TMOSFET 100.
  • the closed cell TMSOFET 200 has a relatively low channel resistance (e.g., on resistance), as compared to the striped TMOSFET;100 geometry- The low channel resistance reduces power dissipated in the closed cell s TMOSFET 200, as compared to the striped TMOSFET 100.
  • the gate-to-drain capacitance of the closed cell TMOSFET 0 220 is a function of the area of overlap between the bottom of the gate region 220 and the drain region 240. Accordingly, the closed cell TMOSFET 200 geometry suffers from a higher gate-to-drain capacitance, as compared to the striped TMOSFET 100. The relatively high gate to drain capacitance limits the switching speed of the closed cell TMOSFET 200, as compared to the striped TMOSFET 10Q.
  • embodiments here described provide a trench metal-oxide-semiconductor field effect transistor (TMOSFET) having its gate and drain regions on the same side while the source region is oppositely disposed.
  • TMOSFET trench metal-oxide-semiconductor field effect transistor
  • Embodimfinrs provide a striped or closed cell TMOSFET having an on resistance substantially equivalent to a striped or closed cell TMOSFET. Further, embodiments provide a striped or closed cell TMOSFET having a low gate-to- drain capacitance.
  • Embodiments also provide a striped or closed cell TMOSFET comprising a source region, a body region disposed above the source region, a drift region disposed above the body region, a drain region disposed above the drift region.
  • a gate region is disposed above the source region and adjacent to the body region.
  • a gate insulator region electrically isolates the gate region from the source region, body region, drift region and drain region. The body region is electrically coupled to the source region.
  • Embodiments also provide a method of fabricating a striped or closed cell TMOSFET.
  • the method of fabrication comprises growing a p-doped epitaxial silicon layer on an n-doped silicon substrate, and growing an n-do ⁇ ed epitaxial silicon layer upon the p-doped silicon layer.
  • silicon layers and a portion of the substrate are selectively etched to form a set of trenches.
  • the silicon proximate the trenches h rtvirlifced to form a gate oxide region.
  • a first portion of the trenches are filed with a polysilicon and the remaining portion of the trenches are filled with a dielectric.
  • N-typc impurities arc implanted to form d ⁇ tt regions and drain regions.
  • P-type impurity is implanted to form the body region of the N-channel MOSFET.
  • FIG. 1 shows a cross-sectional perspective view of a striped trench metal-oxitde- semiconductor field effect transistor (TMOSFET) according to the conventional art-
  • TMOSFET striped trench metal-oxitde- semiconductor field effect transistor
  • FIG. 2 shows a cross-sectional perspective view of a closed cell trench rnetal- oxide-semiconductor field effect transistor (TMOSFET) according to the conventional art.
  • TMOSFET closed cell trench rnetal- oxide-semiconductor field effect transistor
  • FIG. 1 shows a cross-sectional perspective view of a striped cell trench metal- oxide-semiconductor field effect transistor (TMOSFET), in accordance with one embodiment of the present invention.
  • TMOSFET striped cell trench metal- oxide-semiconductor field effect transistor
  • FIG. 4 shows a cross-sectional perspective view of another striped cell trench metal-oxide-semiconductor field effect transistor (TMOSFET), in accordance with one embodiment of the present invention.
  • TMOSFET striped cell trench metal-oxide-semiconductor field effect transistor
  • Figures 5A-5D show a flow diagram of a method of fabricating a striped cell
  • TOSFRT trench metal-oxide-semiconductor field effect transistor
  • Figures 6A-6O show a cross-sectional plane view of various phases of fabricating a striped cell trench metal-oxide-semiconductor field effect transistor (TMOSFET), in accordance with one embodiment of the present invention.
  • TMOSFET striped cell trench metal-oxide-semiconductor field effect transistor
  • FIG. 7 shows a cross-sectional perspective view of a closed cell trench metal- oxide-semiconductor field effect transistor (TMOSFET). in accordance with one embodiment of the present invention.
  • TMOSFET metal- oxide-semiconductor field effect transistor
  • FIGS 8 ⁇ -SD show a flow diagram of a method of fabricating a closed cell trench metal -oxide-semiconductor 'field effect transistor (TMOSFET), in accordance with one embodiment of the present invention.
  • TMOSFET trench metal -oxide-semiconductor 'field effect transistor
  • FIGS 9A-9O show a cross-sectional plane view of various phases of fabricating a closed cell trench metal-oxide-semiconductor field effect transistor (TMOSFET), in accordance with one embodiment of the present invention.
  • TMOSFET closed cell trench metal-oxide-semiconductor field effect transistor
  • FIGS 10 ⁇ -10D ahow a flow diagram of a method of fabricating a closed cell trench raetal-oxide-semicond ⁇ ctor field effect transistor (TMOSFET), in accordance with
  • Figures 1 1A-11N show a cross-sectional plane view of various phases of fabricating a closed cell trench metal-oxide-semico ⁇ ductor field effect transistor
  • FIG. 3 a cross-sectional perspective view of a striped cell trench metal-oxide-semiconductor field effect transistor (TMOSFET) 300, in accordance with one embodiment of the present invention, is shown.
  • the striped cell TMOSFET 300 comprises a source contact 310, a source region 315, a plurality of gate regions 320, a plurality of gate insulator regions 325, a plurality of body regions 330. a plurality of drift regions 335, a plurality of drain regions 340 and a drain contact 345.
  • the striped cell TMOSFET 300 may further comprise a first source-body contact region 350, a second source-body contact region 355. and a source-body contact insulator region 360.
  • The- plurality of gate regions 320, the plurality of gate insulator regions 325, the plurality of body regions 330, the plurality of drift regions 335 and the plurality of drain regions 340 are disposed above the source region 315.
  • the gate regions 320 and the gate insulator regions 325 are formed as substantially parallel elongated structures.
  • the body regions 330 are disposed above the source region 315 and between the parallel elongated structures formed by the gate regions 320 and gate insulator regions 325.
  • the drift regions 335 arc disposed above the body regions 330 and between the parallel elongated structures formed by the gate ⁇ egions 320 and gate juisularor regions 325.
  • the drain regions 340 are disposed above the drift ramons 335 and between the parallel ' elongated structures formed by the gate regions 320 and gate insulator regions 325.
  • the gate regions 320 are surrounded by corresponding gate insulator regions 325.
  • the gate regions 320 are electrically isolated from the surrounding regions (e.g., source region 315, body regions 330, drift regions 335. drain regions 340 and drain contact 345) by the gate insulator regions 325.
  • the gate regions 320 arc interconnect to each other (e.g., in the periphery region of the device by a gate contact).
  • the plurality of drain regions 340 arc coupled to form a common drain of the device by the drain contact 345. From the above, description, it is appreciated iliat lie
  • present striped TMOSFET 300 has its gate regions 320 arid drain regions 340 substantially on the same side.
  • the source region 315 and. the drain regions 340 may be heavily n-doped (N+) semiconductor, such as silicon doped with phosphorous or
  • the body regions 330 may be p-doped (P) semiconductor, such as silicon doped with boron.
  • the drift regions may be lightly n-doped (N-) semiconductor, such as silicon doped with phosphorous or arsenic.
  • the gate regions 320 may be heavily n-doped (N- 1 -) or p-doped (P+) semiconductor, such as polysilicon doped with phosphorous or arsenic, or polysilicon doped with boron.
  • the gate insulator region 325 may be an oxide, such as silicon dioxide.
  • the source region 315 and the drain regions 340 may be heavily p-doped (P+) semiconductor, such as silicon doped with boron.
  • the body regions 330 may be lightly n-doped (N-) semiconductor, such as silicon, doped, with phosphorous or arsenic.
  • the drift regions may be lightly p-doped (P-) semiconductor, such as silicon doped with boron.
  • the gate regions 320 may be heavily n-doped (N+) or p-doped (P+) semiconductor, such as polysilicon doped with phosphorous or arsenic of polysilicon doped with boron.
  • the gate insulator region 325 may be an oxide, such as silicon dioxide.
  • the body regions 330 are electrically coupled to the source region 315.
  • the body regions 330 are coupled to the source region 315 by the first and second source-body contact regions 350. 355.
  • the second source-body contact regions 355 are a silicide, such as tungsten suicide.
  • the source-body contact regions 350, 355 are electrically isolated from the surrounding regions (e.g., drift regions 335) by the source-body coub ⁇ ci insulator region 360
  • the source-body contact insulator region 360 may be an oxide. such as
  • tne sourcebody contact insulator region 360 may be p-doped poly silicon, silicon nitride or the like.
  • the width of the channel is a function of the sum of the lengths of the drain regions 340. Hence, ihc width of the channel region is substantially equal to the legacy striped cell TMOSFET 100, Therefore, the on resistance (Rds-on) of the device
  • the 300 is substantially equal to the legacy striped cell TMOSFET 100.
  • a lead wire is utilized, to connect the source on the die to an external device.
  • the source wire bad increases the effective inductance of the source in the legacy stripped cell TMSOFRT 100.
  • the source of the present striped cell TMOSFET 300 may be connected directly to a PCB or a legacy striped cell TMOSFET (e.g., source contact covers the bottom of the die and may be wave soldered to a PCB or the like).
  • the wire lead of the source may be eliminated, and therefore the effective source inductance is reduced.
  • the present sniped cell TMOSFET 300 may be fabricated such that the gate regions 320 do not overlap the drain regions 340. Therefore the separation of the gate regions 320 and d ⁇ ain regions 340 is increased. Accordingly, the gate-to-drain capacitance (Cgd) may be substantially reduced as compared to the tegacy striped cell TMOSFET 100.' For example, in one implementation the gate regions substantially overlap the body regions and do not substantially overlap the drift regions or the drain regions.
  • the present striped cell TMOSFET 300 has a relatively large gaie-to-source capacitance (Cgs) as a result of the overlap of the gate regions 320 with the source region 315. Therefore lhe gate-to-source capacitance (Cgs) of the present striped cell TMOSFET 300 is generally greater than the gate-to-source capacitance (CgS)
  • the ratio of the gate to-drain capacitance (Cgd) to the source-to-drain capacitance (Cgs). a figure of merit, of the present stripe cell TMOSFET 300 is -less (e.g., better figure of merit) than the legacy striped cell TMOSFET 100. It is also appreciated that the ratio of the gate-to-drain capacitance (Cgd) to gate-to-source capacitance (Cgs) u ⁇ ay be adjusted by adjusting the thickness of the portion of the gate oxide regions 325 proximate the source region 315 and/or the portion of the gate insulator regions 325 proximate the drain regions 340.
  • FIG 4 a cross-sectional perspective view of another striped cell trench metal-oxide-semiconductor field effect transistor (TMOSFET-) 400, in accordance with one embodiment of the present invention, is shown.
  • the striped, cell TMOSFET 400 is the same as described with reference to Figure 3, with the addition of a plurality of super source regions 365.
  • the super source regions 365 areib ⁇ ned as * . substantially parallel elongated structures disposed above the gate regions 320.
  • the gate insulator regions also surround the super source regions 365 and electrically isolate the super source regions 365 from the surrounding regions (e.g., gate regions 320, body regions 330, drift regions 335, drain regions 340 and drain contact 345).
  • the super source regions 365 are electrically coupled to the's ⁇ urce region 315 (e.g., by a contact in the periphery region).
  • the super source regions 365 are adapted to decrease the on state iesistance (Rds-on) and to increase the breakdown voltage in the off state.
  • drain contact 345 is also shown substantially cutaway to reveal the striped cell structure in greater detail. However, it is understood that the drain contact 345 overlays the surface of the core region of the present striped cell TMOSET 400.
  • FIG. 5 A-5D a flow diagram of a method of fabricating a striped cell trench metal-oxide-semiconducror field effect transistor (TMOSFET), in accordance with one embodiment of the present invention.
  • the method of fabricating the striped cell TMOSFET, in accordance with one embodiment of the present invention is illustrated in Figures 6A-6O-
  • the process begins, at 502, with various initial processes upon a substrate 502', such as cleaning, depositing, doping, etching and/or the like.
  • the substrate 502' comprises silicon heavily doped with phosphorous (N+). It is appreciated that the semiconductor substrate 502' will substantially comprise a source region of the TMOSFET upon completion of the fabrication process.
  • a first semiconductor layer 504' is epitaxial deposited Upon the substrate 502'.
  • the first semiconductor layer 504' comprises p-
  • the epitaxial deposited silicon may be doped by introducing the desired impurity, such as boron, into the epitaxal reaction chamber.
  • the doping of the first semiconductor layer 504' may be achieved by a high-energy implantation with a p-type dopant, such as boron.
  • a second semiconductor layer 506' is epitaxial deposited upon the first semiconductor layer 504'.
  • the second semiconductor layer 506' comprises lightly p-doped (P-) silicon.
  • the epitaxial deposited silicon may be doped by introducing the desired impurity, such as boron, into the reaction chamber.
  • the doping of the second semiconductor layer 506' may be achieved by a high-energy implantation with a p-type dopant, such as boron.
  • a sacrificial oxide layer 508' is fouiicd upon the second semiconductor layer 506'.
  • the sacrificial oxide 508' is formed by oxidizing the surface of the second semiconductor layer 506'.
  • a photoresist is deposited and patterned by any well-know lithography process to form a gate trench resist layer 510'.
  • the exposed portions of the sacrificial oxide layer 50S 1 , the . second semiconductor layer 506", the first semiconductor layer 504' and a portion of the substrate 502 are etched by any well-known anisotropic etching method (e.g., dry etch),
  • an ionic etchant interacts with the sacrificial Oxide layer 508', second semiconductor layer 506 ⁇ first semiconductor layer 504' and the substrate 502' exposed by the gate trench resist layer 510 ' .
  • the etching process results in a first plurality of trenches 512' formed as substantially parallel structures.
  • the gate trench resist layer 510 ' is removed utilizing an appropriate resist stripper or a resist ashign process
  • a dielectric layer 516' is formed on the walls of the first plurality of trenches 512'. In one implementation, the
  • dielectric layer 516' is formed by oxidizing the exposed surface of the silicon to form a silicon dioxide layer. The resulting dielectric layer 516' along the trench walls forms a first portion of the gate insulator regions.
  • a polysilicon layer is deposited in the first plurality of trenches 512'.
  • the pojysilicon is deposited m the trenches 512' by a « method such as decomposition of silane (SiH4),
  • the polysilicon is doped with n-type
  • the polysilicon may be doped by introducing the impurity during the deposition, process.
  • an etch-back process is performed to remove excess polysilicon material to form the gate regions 520'.
  • the polysilicon layer is etched back such that the desired separation/overlap between the gate region formed from the polysilicon layer in the trench and the subsequently formed body, drift and drain regions,
  • the excess polysilicon is removed by a combination of a chemical mechanical polishing (CMP) process and an anisotropic etching method.
  • CMP chemical mechanical polishing
  • a dielectric layer is formed over the gate regions 520'.
  • the polysilicon of the gate regions 512' is oxidized to form a silicon dioxide layer.
  • a second polysilicon layer is deposited over the dielectric layer formed upon the gate regions 520'. Another etch back process is utilizes to'form super source regions from the second polysilicon layer.
  • a dielectric layer is deposited in the first plurality of trenches 512'. at 522.
  • the dielectric is deposited in the trenches by a method such as decomposition of tctracthlortliobilicate (TEOS) or high density plasma fill (HDP).
  • TEOS tctracthlortliobilicate
  • HDP high density plasma fill
  • excess dielectric material is removed to complete the gate insulator regions 524'. In one implementation, the excess dielectric is removed by a chemical mechanical polishing (CMP) process.
  • CMP chemical mechanical polishing
  • the first semiconductor layer 504' is p-doped to adjust the doping concentration to form body regions 526' between the first plurality of trenches 512',
  • the doping process implants a p-type impurity 527' 3 such as boron, in the first semiconductor layer 504'.
  • a tne ⁇ rial cycle is utilized to ! drive (e.g., diffusion) the implanted impurity substantially through ike depth of the first, semiconductor layer 504', thereby forming the body regions 526'.
  • the second semiconductor layer 506' is n-doped.
  • the doping process implants an n-type impurity 531', such as phosphorous or arsenic, in the second semiconductor layer 506'.
  • a second thermal cycle is utilized to drive (e.g., diffusion) the implanted impurity substantially through the depth of the second semiconductor layer 506'.
  • the upper portion of the second semiconductor layer 506' is heavily n-doped to form the drains 534' in the upper portion and the drift regions 530' in the lower portion Qf the second semiconductor layer 506' between the first plurality of trenches 512',
  • the doping process implants an n-type impurity 533', such as phosphorous or arsenic, in the upper portion of the second semiconductor layer 506'.
  • Al 536, a third thermal cycle may be utilized to drive the third implant to achieve the desired depth of the drain regions 534'.
  • a second sacrificial oxide layer 538' is formed upon the wafer.
  • the sacrificial oxide layer 538' is formed by oxidizing the surface of the wafer.
  • a photo-resist is deposited and patterned by any well-know lithography process to form a source-body contact trench resist layer
  • the exposed portions of the second sacrificial oxide layer 538'. the drain regions 534' and the drift regions 530' are etched by any well-known anisotropic etching method, at 544.
  • an ionic etchant interacts with sacrificial oxide layer 538' the drain regions 534' and the drift regions 530' exposed by the source-body contact trench resist layer 542'.
  • the etching process forms a second plurality of substantially parallel trenches 544'. Each of the second plurality of trenches 544' is disposed between each of the first plurality of trenches 512'.
  • the exposed poiti ⁇ n of the body regions 526' are heavily p- doped to form first source-body contacts 5-16".
  • the doping process implants a p-type impurity 545'. such as boron, in the body regions 526'.
  • a thermal cycle may be utilized to drive the source-body implant substantially throughout the'exposed portions of the body regions 526', ⁇ It is appreciated that a portion of the implant will diffuse laterally into the adjacent uii-cxposed portion of the body regions 526',
  • the source-body contact trench resist layer 542* is removed utilizing an appropriate resist stripper or a resist ashing process.
  • a dielectric layer 550' is formed on the walls of the second plurality of trenches 544'. In one implementation, the dielectric layer 550' is formed by oxidizing the exposed surface of the silicon to form a silicon dioxide layer.
  • the dielectric formed at the bottom of the second plurality of trenches 544' and the exposed portions of the body regions 526 are etched by any -well- known anisotropic etching method.
  • the etching process is performed until the second plurality of trenches 552' extend partially into the source region 502' (e.g. substrate).
  • the etching process leaves the adjacent portions of the body regions 526 and source region 502' exposed, while the drift regions 53 Q' and the drain regions remain protected by the dielectric layer 550' along the .sidewalls. It is appreciated that the portions of the source- body contact implant that diffused laterally into the un-exposed portions of the body . regions 526' substantially remains after the present etching process.
  • the remaining portions of the source-body contact implant form first source-body contacts.
  • a first metal layer 554' is deposited in the bottoms of the second plurality of trenches 552' and reacted with the source region 502' and body regions 526'.
  • titanium is sputtered and rapidly thermal annealed to form titanium suicide (TiSi) along the exposed portions of the source region 502' and body regions 526'.
  • TiSi titanium suicide
  • the titanium suicide forms second source-body contacts 556', which in combination with the first source-body contacts 546', electrically couples the body
  • a second dielectric is deposited in the second plurality of trenches 552' to form source-body insulator regions 560'.
  • the dielectric is deposited in the trenches 552' by a method such as decomposition of tetraethlorthosilicate (TEOS) or high density plasma fill (HDP).
  • TEOS tetraethlorthosilicate
  • HDP high density plasma fill
  • a photo-resist is deposited and patterned by any well-known lithography process to form a gate contact resist layer (not shown).
  • the gate contacts are. formed in the periphery (not shown).
  • the exposed portion of the gate insulators 524' are, etched by any well-known anisotropic etching method (not shown).
  • an ionic etchant interacts with the gate oxide exposed by the gate contact resist layer.
  • the gate contact openings extend down to the gates 520*.
  • the gate contact resist layer is removed utilizing an appropriate resist stripper or a resist ashing process (not shown).
  • a photo-resist is deposited and patterned by any well-known lithography process"to form a drain contact resist layer (not shown)-.
  • the exposed portion of the third sacrificial oxide is etched by any well-known anisotropic etching " method (not shown).
  • an ionic etchant interacts with the third
  • drain contact openings extend down to the drain regions.
  • the drain contact ⁇ esist layer is removed utilising an appropriate resist stripper or a resist- ashing process.
  • a second metal layer is deposited on the wafer.
  • the second metal layer such as aluminum, is deposited by any well- known method such as sputtering.
  • the second metal layer covers the tops of the drains 534', the gate insulators 524' and the source-body contact insulators 560'.
  • the second metal layer extends down into the gate contact openings to make an electrical contact to the gates 520' and " down into the drain contact openings to make an electrical contact to the drains.
  • the second' metal layer is then patterned utilizing a photo-resist mask and • selective etching method to form a gate contact layer (not shown) and a drain contact layer 578 at 578.
  • fabrication continues with various backside processes to form a source contact.
  • the various processes typically include etching, deposition, doping, : cieanmg, annealing, passivation, cleaving and/or the like.
  • FIG. 7 a cross-sectional perspective view of.a closed-cell trench metal-oxide-semiconducto ⁇ field effect transistor (TMOSFET) 700, in. accordance with one embodiment of the present invention, is shown.
  • The. closed cell TMOSFET 700 comprises ' a- source contact 710, a source region 715, a gate region 720, a gate insulator region 725, a plurality of body regions 730, a plurality of drift regions 735, a plurality of drain regions 740 and a drain contact 745.
  • the closed cell TMOSFET 700 may further comprise a plurality of , first source-body contact regions 750. a plurality of second source>body contact regions 755, and a plurality of source-body contact insulator regions 760,
  • the gate region 720, the gate insulator region 725, the plurality of body regions 730, the plurality of drift regions 735 and the plurality of drain regions 740 are disposed above the source region 715, A first portion of the gate region 720 and the gate insulator region 725 arc formed as substantially parallel elongated structures.
  • a second portion of the gate region 620 and die gate insulator region 625 are formed as substantially normal -to-parallel elongated structures (e.g., in the surface, plane of the wafer, the second portion of the gate region and gate insulator region comprise a plurality of substantially parallel elongated structures formed at right angles is the first portion of the gate region ' and gate insulator region).
  • the first and second portions of the gate region 720 are all interconnected and form a plurality of cells.
  • the body regions 730 are disposed within the plurality of cells and above the source region 715.
  • the drift regions 735 are disposed within the plurality of cells and above the body regions 730,
  • the drain regions 740 are * disposed within the plurality of cells and above the drift regions 735.
  • the drain contact 745 is shown substantially cutaway to reveal the closed cell structure in greater detail: However, it is to be understood that the drain contact 745 overlays the entire surface of "
  • the gate region 720 is surrounded by the gate insulator region 725.
  • the gate region 720 is electrically isolated from the surrounding regions (e.g., source region 715, body regions 730 » drift regions 735» drain regions 740 and drain contact 745) by the gate insulator region 725.
  • the plurality of drain regions 740 are coupled to form a common drain of the device by the drain contact 745. From the above description, it is appreciated that the present closed cell TMOSKET 700 has its gate and drain terminals on the same side.
  • the source region 715 and the drain regions 740 may be heavily n-dopcd (N+) semiconductor, such as silicon doped with phosphorous or arsenic.
  • the body regions 730 may be p-doped (P) semiconductor, such as silicon doped with boron.
  • the drift regions 735 may lightly n-dopod (N-) semiconductor, such as ' silicon doped with phosphorous or arsenic.
  • the gate region 720 may be heavily n-doped (N+) or p-doped (P+) semiconductor, such as polysilicon doped with phosphorous or > arsenic, or polysilicon doped with boron.
  • the gate insulator region 725 may be an oxide, such as silicon dioxide.
  • the source region 715 and the drain regions 740 may be heavily p-doped (P+) semiconductor, such as silicon doped with boron.
  • the body regions 730 may be lightly n-dopcd (N-) semlcouduetor, such as silicon doped with ⁇
  • the drift regions 735 may lightly p-dopcd (P-) semiconductor,'" such as silicon doped with boron.
  • the gate region 720 may he heavily p-doped (P+) or n- doped (N+) semiconductor, such as polysilicon doped with boron, or polysilicon doped- with phosphorous or arsenic.
  • the gace insulator region 725 may be an oxide, such as silicon dioxide.
  • the body regions 730 are electrically coupled to the source region 715.
  • the body regions 730 are coupled to the source region 715 by the first and second source-body contact regions 750, 755.
  • the second source-body contact regions' 750 may be a suicide, such as tungsten suicide.
  • the first source-body contact regions 755 may be heavily p-do ⁇ ed (P+) semiconductor, such as silicon doped with b ⁇ ron.
  • the source-body contact regions 750, 755 are electrically isolated from the surrounding drift regions 735 by the source-body contact insulator region 760.
  • the source-body contact insulator region 760 may be an oxide, such as silicon dioxide.
  • the source-body contact insulator region 760 may be p-doped polysilicon, silicon nitride or the like.
  • the source-body contact regions 750, 755 and source-body insulator regions 760 are formed substantially in the middle of each cell.
  • the front comer of the cross-sectional view is cut away to show the structure of the source-body contact regions 750, 755 and source-body insulator regions 760 in ' greater detail.
  • the width of the channel is a function of the sum of the perimeter, adjacent the gate insulator region 725., of the drain regions 740. Hence, the width of the channel region is substantially equal to the legacy closed cell TMOSFET 200. Therefore, the on resistance (Rds-on) of the device 700 is substantially equal to the legacy closed cell TMOSFET 200.
  • a lead wire is utilized to connect the source on the die to an external device.
  • the source wire: lead increases the effective inductance of the source in the legacy closed cell TMSOFET 200.
  • the source of the present closed cell TMOSFET 700 may be connected directly to a PCB or a legacy closed cell' TMOSFET 200 (e.g.-, source contact covers the bottom of the die and may be wave soldered to a PCB or the like).
  • the wiic lead of the source may be eliminated, and therefore the effective source inductance of the present closed cell TMOSFET 700 is
  • the present closed cell TMOSFET 700 may be fabricated such that the gate region 720 does not overlap the drain regions 740. Therefore, ihc separation of the
  • gate region 720 and drain regions'740 is increased.
  • the increased separation reduces the gate-to-drain capacitance (Cgd). Accordingly, the gate-to-drain capacitance (Cgd) of the present closed cell TMOSFET 700 is reduced as compared to the legacy closed cell TMOSFET 200.
  • the present closed cell TMOSFET 700 has a relatively large gate-to-source capacitance (Cgs) as a result of the overlap of the gate region 720 with the source region 715. Therefore, the gate-to-source capacitance (Cgs) of the present closed cell TMOSFET 700 is generally greater than the gate-to-so ⁇ rce capacitance (Cgs) of the' legacy closed cell TMOSFET 200.
  • the ratio of the gate-to-dram capacitance (Cgd) to "the source-to-drain capacitance (Cgs), a figure of merit of the present closed cell TMOSFET 700 is less (e.g., better figure ' of merit) than the legacy closed cell TMOSFET 200.
  • the ratio of the gate-to-drain capacitance (Cgd) to gate-to-source capacitance (Cgs) may be adjusted by adjusting the thickness of the portion of the gate insulator region 725 proximate the source region 715 and/or the portion of the gate insulator region 725 proximate the drain regions 740.
  • the on resistance (Rds-on) of the present closed cell TMOSFET 700 may be further reduced,
  • the closed cell TMOSFET 700 may further include a super source region.
  • the super source region is formed as a substantially parallel elongated structure disposed above the gate region 720.
  • the gate insulator region 725 also surrounds the super source region and electrically isolates the super source region from the surrounding regions (e.g., gate region 720, body regions 730, drift regions 735, drain regions 740 and drain contact 745).
  • the super source region is electrically coupled to the source region 715 (e.g., by a contact in the periphery region)
  • the super source region is adapted Lo further decrease the on state resistance (Rds-on) and to increases the breakdown voltage in the off state of ihc closed cell TMOSFET 700.
  • TMOSFET closed cell trench metal-oxide-semiconductor field effect transistor •
  • FIGS 9A-9N The method of fabricating the closed cell TMOSFET, in accordance with one embodiment of the piebcnt invention, is illustrated in Figures 9A-9N.
  • the process begins, al 802, with various initial processes upon a substrate 8O2', such as cleaning, depositing, doping, etching and/or the like.
  • the substrate 802' comprises silicon heavily doped with phosphorous (N i ).
  • the semiconductor substrate 802' will substantially comprise a source region of the TMOSFFT upon completion of the fabrication processes.
  • a first semiconductor layer SQ4" is epitaxial deposited upon the
  • the first semiconductor layer 804' comprises heavily p-doped (P+) silicon.
  • the epitaxial deposited silicon may be doped by introducing the desired impurity, such as boron, into the epitaxal reaction chamber.
  • the doping of the first semiconductor layer may be achieved by a high energy implantation with a p-ty ⁇ e dopant, such as boron.
  • a second semiconductor layer 806' is epitaxial deposited upon the first semiconductor layer 804'-
  • fhe second semiconductor layer 806' comprises n-doped (N) silicon.
  • the epitaxial deposited silicon may be doped by introducing the desired impurity, such as phosphorous or arsenic, into the reaction chamber.
  • the doping of the second semiconductor layer may be achievec by a high energy implantation with an n-type dopant, such as phosphorous or arsenic.
  • a first sacrificial oxide layer 8O8 ' is formed upon the second acmiconductoi layer 806'
  • the sacrificial oxide layer 808' is formed by oxidizing the surface of the second semiconductor layer 806".
  • a photo-resist is deposited and patterned by any well know lithography process to
  • the exposed portions of the sacrificial oxide; layer 808', the second semiconductor layer 806'. the first semiconductor layer 80-1 ' and a portion of the substrate 802 1 are etched by any well-known anisotropic etching method (e.g., dry etch).
  • an ionic etchant interacts with the sacrificial oxide layer 808', second semiconductor layer 806', first semiconductor layer 804' and the substrate 802' exposed by the gate trench resist layer 810 ⁇
  • the etching process results in plurality of trenches 812' having a plurality of cells disposed therein.
  • the plurality of trenches 812' are formed having a first portion of substantially parallel structures and a second portion of substantially no ⁇ nal-to-parallel structures.
  • the gate trench resist layer SlO' is removed utilizing an appropriate resist stripper or a resist ashing process.
  • a -first dielectric 816' is ⁇ formed on the walls of the plurality of trenches 812'.
  • the first dielectric 816' is formed by oxidizing the exposed surface of the silicon to form a silicon dioxide layer. The resulting dielectric 816' along the trench walls forms a first portion of gate insulator regions .
  • a polysilicon layer 820' is deposited in the first plurality of , trenches 812'.
  • the polysilicon 820' is deposited in the trenches 812' by a method such as decomposition of silanc (S1H4).
  • the polysilicon may be doped
  • n-type impurity such as phosphorous or arsenic.
  • the polysilicone may " be doped by introducing the impurity during the deposition process.
  • an etch-back process is performed to remove excess polysilicon material to form gate regions.
  • the polysilicon layer is etched back such thai (lie desired separation/overlap between the gate region, formed from the polysilicon layer in the trenches and the subsequently formed body, drift, and drain regions.
  • the excess polysilic ⁇ n is removed by a combination of a chemical mechanical polishing (CMP) process and an anisotropic: etching method.
  • CMP chemical mechanical polishing
  • a dielectric layer is formed over the gate.
  • the polysilicon of the gate is oxidized to form a silicon dioxide.
  • a second polysilicon layer is deposited over the dielectric layer formed upon the gate. Another etch back process is utilizes to form a super source from the second polysilicon layer.
  • a second dielectric 824. ' is deposited in the first plurality of trenches 812', at 822.
  • the dielectric is deposited in the trenches by a method such as decomposition of tstraethlorthosilicate (TEOS) or high density plasma -fill (HDP).
  • TEOS tstraethlorthosilicate
  • HDP high density plasma -fill
  • excess dielectric material is removed to complete the gate insulator region, in one implementation, the excess dielectric is- removed by a chemical mechanical polishing (CMP) process.
  • CMP chemical mechanical polishing
  • the first semiconductor layer 804' is p-doped to adjust the
  • the doping process implants a p-rype impurity 827', such as boron, in the first semiconductor layer 804'.
  • a thermal cycle is utilized to drive (e.g., ' • •' • diffusion) the implanted impurity substantially through the depth of the first semiconductor layer 804, thereby forming the body regions 826',
  • the second thermal cycle is utilized to drive (e.g., ' • •' • diffusion) the implanted impurity substantially through the depth of the first semiconductor layer 804, thereby forming the body regions 826',
  • the second thermal cycle is utilized to drive (e.g., ' • •' • diffusion) the implanted impurity substantially through the depth of the first semiconductor layer 804, thereby forming the body regions 826',
  • the second thermal cycle is utilized to drive (e.g., ' • •' • diffusion) the implanted impurity substantially through the depth of the first semiconductor layer 804, thereby forming the body regions 826',
  • the second thermal cycle is utilized
  • semiconductor layer 806' is n-doped.
  • the doping process implants an n-type impurity 831', such as phosphorous or arsenic, in the second semiconductor layer 806'.
  • a second thermal cycle is utilized to drive (e.g., diffusion) the implanted impurity substantially through the depth of the second semiconductor layer 806'.
  • the upper portion of the second semiconductor layer 806' is heavily n-doped to form drain regions 834' in the upper portion and drift regions " 830' in the lower portion of the second semiconductor layer 806' between the plurality of trenches 812'.
  • the doping process implants an ⁇ -type impurity 833', such as phosphorous or arsenic, in the upper portion of the second semiconductor layer 806'.
  • ⁇ t 836 a third thermal cycle may be utilized to drive the drain region implant to achieve the desired depth of the drain regions 834'.
  • a second sacrificial oxide layer 838' is formed upon the wafer.
  • the second sacrificial oxide 838" is formed by oxidising the surface of the wafer.
  • a photo-resist is deposited and patterned by any well-know lithography process to form a source-body contact opening resist layer 840 ⁇
  • the exposed portions of the second sacrificial oxide layer 838', the source regions 834' and the drift regions 830' are etched by any well-known anisotropic etching method, at 842.
  • an ionic. - ewhant interacts with sacrificial oxide layer 836' the source regions 834' and the drift regions 830' exposed by the source-body contact opening resist layer 840".
  • the etching process forms a plurality of source-body contact opening 842'.
  • Each of the source-body contact openings 842' are disposed within the cells formed by the plurality of Trenches 812'
  • the exposed portion of the body regions 826' are heavily doped to form fjrst source-body contact regions 844',
  • the doping process implants a p-type impurity 843', such as boron, in the body region 826'.
  • a thermal cycle may be utilized to drive the source-body implant substantially throughout the exposed portion of the body regions 826'. Il is appreciated that a portion of the implant will diffuse laterally into the 'adjacent un-e ⁇ osed portion of the body regions " 826'.
  • the source-body contact opening resist layer 840' is removed utilizing an appropriate resist stripper or a resist ashing process.
  • a dielectric 848' is formed on the walls of the source-body contact openings 842'. In one implementation,, the dielectric 848' is formed by oxidizing the exposed surface of the silicon to form a
  • the portion of the dielectric 848' formed at the bottom of the source-body contact openings 842' and the exposed portion of the body regions 826' are etched by any well-known anisotropic etching method.
  • the etching process is performed until the source-body contact openings 850' extend partially into the source region 802' (e.g., substrate).
  • the etching process leaves the adjacent portions of the body regions 826' and source region 802' exposed, while the drift icgions 830" and drain regions 834'
  • Source-body contact implant 844' that diffused laterally into the un-exposed portion of the body regions 826' substantially remains after the present etching process. The remaining portions of the source-body contact implant form first source-body contacts 844'.
  • a first metal 852' is deposited in the bottom of the source-body contact openings 850' and reacted with the exposed portions of the body regions 826' and fee source region 802'.
  • titanium us sputtered in the openings and rapidly thermal annealed to form titanium silicide (TiSi).
  • TiSi titanium silicide
  • the titanium suicide tbrms second source-body contacts 854 ⁇ which in combination with the first source-body contacts electrically coupled the body regions 826' to the source 802*.
  • the un- reacted portion of the titanium along the dielectric lined walls of the source-body contact openings 850' is etched iway.
  • a third dielectric layer is deposited in the source-body contact openings 850' to form a source-body insulator region 856'.
  • the dielectric 856' is deposited in the openings H50' by a method such as decomposition of ⁇ tetraethlorthosilicate (TEOS) or high density plasma fill (HDP)- [0090J
  • TEOS ⁇ tetraethlorthosilicate
  • HDP high density plasma fill
  • a photoresist is deposited and patterned by any well-known ltihography process to form a gate contact resist layer (not shown). The gate contacts are
  • the exposed portion of the gate insulator region 822* is etched by any well-known anisotropic etching method to form gate contacts in the periphery region (not shown), at 864.
  • an ionic etchant interacts with the gate oxide exposed by the gate contact resist layer.
  • the gate contact openings extend down to the gate regions 820'.
  • the gate contact resist layer is removed utilizing an appropriate resist stripper or a resist ashing process.
  • a photo-resist is deposited and patterned by any well-known lithography process to form a drain contact resist layer (not shown).
  • the exposed portion of the excess dielectric material and the third sacrificial oxide in the core is etched by any well-known anisotropic etching method to a form drain contact opening (not shown).
  • an ionic etchant interacts with the excess dielectric material and the third sacrificial oxide to form a drain contact opening.
  • the drain contact opening extends down to the drain region ' s 834'.
  • the drain contact resist layer is removed utilizing an appropriate resist stripper or a resist ashing process (not shown).
  • a second metal layer is deposited on the wafer.
  • the second metal layer such as aluminum
  • the metal layer covers the tops of the drain regions 834'. the gate insulator regions 856', the source-body contact insulator regions 856'/"
  • the second metal layer extends down into the gate contact openings to make an electrical contact to the gate regions and down into the drain contact openings to make an electrical contact to the drain regions 834'.
  • the second me ⁇ al layer is then patterned utilizing a photo-resist mask and selective etching method to form a gale contact layer (not shown) and a drain contact layer 876', at 876,
  • fabrication continues with various backside processes to form a source contact.
  • the various processes typically include etching, deposition, doping, cleaning, annealing, passivation, cleaving and/or the like.
  • FIG. 10A- 1OD a flow diagram of a method of fabricating a closed cell trench metal-oxide-semiconductor field effect transistor (TMOSFET), in accordance with another embodiment of the present invention, is - ⁇ own.
  • the method of fabricating the closed cell TMOSFET, in accordance with, another embodiment of the present invention, is illustrated in Figures 1 IA-110.
  • the process begins, at 1002, with various initial processes upon a substrate 1002', such as cleaning, depositing, doping, etching and/or the like.
  • the substrate 1002' comprises silicon heavily doped with phosphorous (N+).
  • the semiconductor substrate 1002' will substantially comprise a source ⁇ egion of the TMOSFET upon completion of the fabrication process.
  • a first semiconductor layer 1004 is epitaxial deposited upon the substrate 1002'.
  • the first semiconductor layer 1004' comprises heavily p-doped (P ⁇ ) silicon.
  • the epitaxial deposited silicon may be doped by introducing the desired impurity, such as boron, into the epitaxal reaction chamber.
  • the doping of first semiconductor layer 1004' may be achieved by a high energy implantation with a p- ⁇ ype dopant, such ⁇ a boron.
  • a second semiconductor layer 1006' is epitaxial deposited upon the first semiconductor layer 1004',
  • the second semiconductor layer comprises lightly n-doped (N-) silicon.
  • the epitaxial deposited silicon may be doped by introducing the desired impurity, such as phosphorous or arsenic, mto the reaction chamber.
  • the doping of second semiconductor laye. 1006' may be achieved by a high energy implantation with an n-type dopant, such as phosphorous? of arsenic.
  • a first sacrificial oxide layer 1008' is formed upon the second semiconductor layer 1006'.
  • the sacrificial oxide layer 1008 1 is formed by oxidizing the surface of the second semiconductor layer 1006'.
  • a photo-resist is deposited and patterned by any-well know lithography process to form a gate trench resist layer 1010'.
  • the exposed portions of the first sacrificial oxide layer 1008', the second semiconductor layer 1006', the first semiconductor layer 1004' and a portion of the substrate 1002' are etched by any well-known anisotropic etching method (e.g., dxy etch).
  • an ionic etchant interacts with the sacrificial oxide layer 1008', second semiconductor layer 1006', first-semiconductor layer 1004' and the - substrate 1002' exposed by the gate trench resist layer 1010'.
  • 1012' are formed having a first portion of substantially parallel structures and a second portion of substantially normal to parallel structures.
  • the gate trench resist layer 1010' is removed utilizing an appropriate resist stripper or a resist ashing process.
  • a first dielectric layer 1016' is formed on the walls of the plurality of trenches 1012'.
  • the dielectric layer 1016' is formed by oxidizing the exposed surface of the silicon to form a silicon dioxide layer
  • the resulting dielectric layer 1016" along the trench walls forms a first portion of a gate insulator region.
  • a first polysilicon layer is deposited in the plurality of trenches.
  • the polysilicon is deposited in the trenches by a method such as decomposition of silane (SiH4).
  • the polysilicon may be doped with n-type
  • the polysilicon may be doped by introducing the impurity during the deposition process.
  • an etch-back process is performed to remove excess p ' olysilicon material to form the gate regions 1020*.
  • the polysilicon layer is etched back such that the desired separation/overlap between the gate region formed from the polysilicon layer in the trenches and the subsequently formed body, drift and drain regions.
  • the excess polysilicon is removed by a combination of a chemical mechanical polishing (CMP) process and an anisotropic etching method.
  • CMP chemical mechanical polishing
  • a second, dielectric layer 1022' is formed over the gate regions 1020', at optional process 1022.
  • the polys ⁇ licon of the gate 1020' is oxidized to form silicon dioxide.
  • a second polysilicon layer is deposited over the dielectric layer 1022* formed upoh the gate 1020'.
  • another etch back process is utilizes to form super source regions 1026' from the second polysilicon layer.
  • a third dielectric layer is deposited in the plurality of trenches 1012'- In one implementation, the dielectric is deposited utilizing a sub-atmospheric chemical vapor deposition (SACVD) process.
  • SACVD sub-atmospheric chemical vapor deposition
  • excess dielectric material is .,-em ⁇ ved to complete the gate insulator region 1030'- In one implementation, the excess dielectric material is removed by a chemical mechanical polishing (CMP) process.
  • CMP chemical mechanical polishing
  • the lower portion of the second semiconductor layer 1004' is- doped with a p-type impurity.
  • the doping process implants a p- type impurity 1032", such as boron, in the lower portion of the second semiconductor layer 1006'.
  • a thermal cycle is utilized to drive (e.g., diffusion) the implanted impurities, thereby forming the body regions 1035', It is appreciated that the thermal cycle will cause the impurities in the first semiconductor layer 1004' and the implanted impurities, from process 1034, in the lower portion of the second semiconductor layer 1006' to diffuse such that body regions 1035' are formed substantially from the first semiconductor layer 1004' and The lower portion of the second semiconductor layer 1006', [00104]
  • the upper portion of the second semiconductor layer 1006' is n-doped to adjust the doping c ⁇ ii ⁇ ;ciiLralJon of the drift region 1036'.
  • the doping process implants an n-type impurity 1037', such as phosphorous or arsenic, in the upper portion of the second semiconductor layer 1006".
  • a second thermal cycle is utilized to drive (e.g., diffusion.) the second implanted impurities, thereby forming the drift regions 1036'.
  • a second sacrificial oxide layer 1042' is formed upon the wafer.
  • the sacrificial oxide layer is formed by oxidizing the surface of the wafer.
  • a photo-resist is deposited and patterned by any well-know lithography process to form a source-body contact opening resist layer 1046", at 1046,
  • the exposed portions of the second sacrificial oxide layer 1042'and drift regions 1036' are etched by any well-known anisotropic etching method.
  • an ionic etchant interacts with the second sacrificial oxide layer 1042'and the drift regions 1036' exposed by the source-body contact opening resist layer 1046'.
  • the etching process forms a plurality of source-body contact openings 1048'. • Each of the source-body contact openings are disposed within the cells formed by the plurality of trenches 1012'.
  • the exposed portion of the body regions are heavily p-doped to form source-body implant regions 1050'.
  • the doping process implants a p-type impurity 1049', such as boron, in the body regions 1035'.
  • a thermal cycle may be utilized to drive the source-body implant 1050' substantially throughout the exposed portion of the body regions 1035'. IL is appreciated that a portion of the source- body implant 1050' will diffuse laterally into the adjacent un exposed portions of the
  • the source-body contact opening resist layer 1046' is removed utilizing an appropriate resist stripper or a resist ashing process.
  • a fourth dielectric layer 1054' is formed on the walls of the source-body contact openings 1048'.
  • the dielectric layer 1054' is formed by oxidizing the exposed surface of the silicon to form a silicon dioxide layer.
  • the portion of the dielectric layer 1054' formed at the bottom, of the source-body contact openings 1048' and the exposed portion of the body regions 1035' are etched by any well-known anisotropic etching method.
  • the etching process is performed until the source-body contact openings 1056' extend partially into the substrate 1002'.
  • the etching process leaves the adjacent portions of the body regions 1035' and source region 1002' exposed, while the drift regions 1036' remain protected by the dielectric layer 1054'. It is appreciated that the portions of the source-body contact implant that diffused laterally into the un-exposed portion of the body regions 1035' substantially remains after the present etching process.
  • first source-body contacts 1050' The remaining portions of the source-body contact implant form first source-body contacts 1050'.
  • a first metal layer 1060' is deposited in the bottoms of the s ⁇ urcc-b ⁇ dy c ⁇ iUacl openings 105C and reacted with the exposed portions of the body regions 1035' and the substrate 1002'.
  • titanium is sputtered in the
  • titanium suicide forms second source-body contacts 1060', which in combination with the first source-body contacts 1050', electrically coupled the body regions 1035' to the substrate region 1002'.
  • the un-reacted portion of the titanium along the dielectric lined walls of the source-body contact openings is etched away.
  • a fifth dielectric layer is deposited in the source-body contact openings to form a source-body insulator region 1064'.
  • the dielectric layer is deposited in the source-body contact openings 1056' utilizing a sub-atmospheric chemical vapor deposition (SACVD) process.
  • SACVD sub-atmospheric chemical vapor deposition
  • a photo-resist is deposited and patterned by any well-known lithography process to form a gate contact resist layer (not ' shown), at 1068.
  • the gate contacts are formed in the periphery (not shown).
  • the - exposed portion df the fifth dielectric layer and the gate insulator regions 1030' are etched r any well-known anisotropic etching method (not shown).
  • an ionic etchant interacts with the gate oxide exposed by the gate contact resist layer.
  • The- gate contact opening extends down to the gate regions 1020'.
  • the gate contact resist layer is removed utilizing an appropriate resist stripper or a resist ashing process (not shown).
  • a photo-resist is deposited and patterned, by any well-known
  • the exposed poiiion ⁇ f the fifth dielectric layer is etched by any well-known anisotropic etching method. In one implementation- an ionic etch ⁇ nt interacts with the fifth diclcctiic
  • drain contact openings extend down to the drift regions 1036 ⁇
  • the upper portion of the drift region is heavily n-doped to form drain regions.
  • a third thermal cycle is utilized to drive (e.g., dififusion) the implanted impurity to achieve the desired depth of the drain regions 1080'.
  • the drain contact resist layer is removed utilizing an appropriate resist stripper or a resist ashing process.
  • a second metal layer is deposited on the wafer,
  • the second metal lay ⁇ ⁇ uch as aluminum, is deposited by any WeU- known method such as sputtering.
  • the metal layer covers the tops of the diani, the gate oxide and the source-body contact oxide regions and makes electrical contact with the drain regions.
  • the second metal layer also extends down into the gate contact opening to make an electrical contact to the gate region.
  • the metal layer is then patterned utilizing a photo-resist mask and selective etching method to form a gate contact layer (not shown) and a drain contact layer 1086', at 1086.

Landscapes

  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

L'invention porte sur un MOSFET à tranchées (metal-oxide semiconductor field effect transistor) dont les cellules sont inversées, dénudées ou fermées. Le TMOSFET à cellules dénudées ou fermées comprend, s'empilant de bas en haut, une région source, un corps, une région de dérive, une région drain. Une région de grille coiffe la région source à côté du corps. Une région d'isolation de grille sépare électriquement la région de grille de la région source, le corps, la région de dérive et la région de drain. Le corps est couplé électriquement à la région source.
PCT/US2005/018096 2005-05-24 2005-05-24 Mosfet a tranchees Ceased WO2006126998A1 (fr)

Priority Applications (5)

Application Number Priority Date Filing Date Title
JP2008513438A JP5350783B2 (ja) 2005-05-24 2005-05-24 トレンチ型金属酸化物半導体電界効果トランジスタの製造方法
PCT/US2005/018096 WO2006126998A1 (fr) 2005-05-24 2005-05-24 Mosfet a tranchees
DE112005003584T DE112005003584B4 (de) 2005-05-24 2005-05-24 Verfahren zum Herstellen eines Trench-Metalloxid-Halbleiter-Feldeffekttransistors
CN2005800502609A CN101208803B (zh) 2005-05-24 2005-05-24 沟槽金属氧化物半导体场效应晶体管
KR1020077026898A KR101047945B1 (ko) 2005-05-24 2005-05-24 트렌치 금속 산화막 반도체 전계 효과 트랜지스터

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/US2005/018096 WO2006126998A1 (fr) 2005-05-24 2005-05-24 Mosfet a tranchees

Publications (1)

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WO2006126998A1 true WO2006126998A1 (fr) 2006-11-30

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PCT/US2005/018096 Ceased WO2006126998A1 (fr) 2005-05-24 2005-05-24 Mosfet a tranchees

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JP (1) JP5350783B2 (fr)
KR (1) KR101047945B1 (fr)
CN (1) CN101208803B (fr)
DE (1) DE112005003584B4 (fr)
WO (1) WO2006126998A1 (fr)

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US9431530B2 (en) 2009-10-20 2016-08-30 Vishay-Siliconix Super-high density trench MOSFET
US9437729B2 (en) 2007-01-08 2016-09-06 Vishay-Siliconix High-density power MOSFET with planarized metalization
US9443974B2 (en) 2009-08-27 2016-09-13 Vishay-Siliconix Super junction trench power MOSFET device fabrication
US9553185B2 (en) 2010-05-27 2017-01-24 Fuji Electric Co., Ltd. MOS-driven semiconductor device and method for manufacturing MOS-driven semiconductor device
US9761696B2 (en) 2007-04-03 2017-09-12 Vishay-Siliconix Self-aligned trench MOSFET and method of manufacture
US9882044B2 (en) 2014-08-19 2018-01-30 Vishay-Siliconix Edge termination for super-junction MOSFETs
US9887259B2 (en) 2014-06-23 2018-02-06 Vishay-Siliconix Modulated super junction power MOSFET devices
US10234486B2 (en) 2014-08-19 2019-03-19 Vishay/Siliconix Vertical sense devices in vertical trench MOSFET
CN111599860A (zh) * 2019-02-20 2020-08-28 联华电子股份有限公司 金属氧化物半导体晶体管及其制造方法

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US9484451B2 (en) 2007-10-05 2016-11-01 Vishay-Siliconix MOSFET active area and edge termination area charge balance
US9425305B2 (en) * 2009-10-20 2016-08-23 Vishay-Siliconix Structures of and methods of fabricating split gate MIS devices
US9419129B2 (en) 2009-10-21 2016-08-16 Vishay-Siliconix Split gate semiconductor device with curved gate oxide profile
KR101728363B1 (ko) 2010-03-02 2017-05-02 비쉐이-실리코닉스 듀얼 게이트 디바이스의 구조 및 제조 방법
US20120028425A1 (en) * 2010-08-02 2012-02-02 Hamilton Lu Methods for fabricating trench metal oxide semiconductor field effect transistors
JP2014518017A (ja) 2011-05-18 2014-07-24 ビシャイ‐シリコニックス 半導体デバイス
US9842911B2 (en) 2012-05-30 2017-12-12 Vishay-Siliconix Adaptive charge balanced edge termination
CN109037337A (zh) * 2018-06-28 2018-12-18 华为技术有限公司 一种功率半导体器件及制造方法
US11217541B2 (en) 2019-05-08 2022-01-04 Vishay-Siliconix, LLC Transistors with electrically active chip seal ring and methods of manufacture
US11218144B2 (en) 2019-09-12 2022-01-04 Vishay-Siliconix, LLC Semiconductor device with multiple independent gates
KR102515335B1 (ko) * 2021-06-23 2023-03-29 서강대학교산학협력단 Mosfet 소자 및 그 제조 방법

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Publication number Priority date Publication date Assignee Title
US9437729B2 (en) 2007-01-08 2016-09-06 Vishay-Siliconix High-density power MOSFET with planarized metalization
US9947770B2 (en) 2007-04-03 2018-04-17 Vishay-Siliconix Self-aligned trench MOSFET and method of manufacture
US9761696B2 (en) 2007-04-03 2017-09-12 Vishay-Siliconix Self-aligned trench MOSFET and method of manufacture
US9443974B2 (en) 2009-08-27 2016-09-13 Vishay-Siliconix Super junction trench power MOSFET device fabrication
US9431530B2 (en) 2009-10-20 2016-08-30 Vishay-Siliconix Super-high density trench MOSFET
US9818845B2 (en) 2010-05-27 2017-11-14 Fuji Electric Co., Ltd. MOS-driven semiconductor device and method for manufacturing MOS-driven semiconductor device
US9553185B2 (en) 2010-05-27 2017-01-24 Fuji Electric Co., Ltd. MOS-driven semiconductor device and method for manufacturing MOS-driven semiconductor device
US9887259B2 (en) 2014-06-23 2018-02-06 Vishay-Siliconix Modulated super junction power MOSFET devices
US10283587B2 (en) 2014-06-23 2019-05-07 Vishay-Siliconix Modulated super junction power MOSFET devices
US9882044B2 (en) 2014-08-19 2018-01-30 Vishay-Siliconix Edge termination for super-junction MOSFETs
US10234486B2 (en) 2014-08-19 2019-03-19 Vishay/Siliconix Vertical sense devices in vertical trench MOSFET
US10340377B2 (en) 2014-08-19 2019-07-02 Vishay-Siliconix Edge termination for super-junction MOSFETs
US10444262B2 (en) 2014-08-19 2019-10-15 Vishay-Siliconix Vertical sense devices in vertical trench MOSFET
US10527654B2 (en) 2014-08-19 2020-01-07 Vishay SIliconix, LLC Vertical sense devices in vertical trench MOSFET
CN111599860A (zh) * 2019-02-20 2020-08-28 联华电子股份有限公司 金属氧化物半导体晶体管及其制造方法
CN111599860B (zh) * 2019-02-20 2023-10-13 联华电子股份有限公司 金属氧化物半导体晶体管及其制造方法

Also Published As

Publication number Publication date
JP5350783B2 (ja) 2013-11-27
CN101208803A (zh) 2008-06-25
DE112005003584B4 (de) 2011-06-16
KR20080025041A (ko) 2008-03-19
KR101047945B1 (ko) 2011-07-12
CN101208803B (zh) 2012-05-30
DE112005003584T5 (de) 2008-04-30
JP2008543046A (ja) 2008-11-27

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