[go: up one dir, main page]

WO2006017339A3 - Architecture de processeur programmable - Google Patents

Architecture de processeur programmable Download PDF

Info

Publication number
WO2006017339A3
WO2006017339A3 PCT/US2005/024867 US2005024867W WO2006017339A3 WO 2006017339 A3 WO2006017339 A3 WO 2006017339A3 US 2005024867 W US2005024867 W US 2005024867W WO 2006017339 A3 WO2006017339 A3 WO 2006017339A3
Authority
WO
WIPO (PCT)
Prior art keywords
processor
sub
type sub
processors
types
Prior art date
Application number
PCT/US2005/024867
Other languages
English (en)
Other versions
WO2006017339A2 (fr
Inventor
Ramchandran Amit
Reid Hauser John Jr
Original Assignee
3Plus1 Technology Inc
Ramchandran Amit
Reid Hauser John Jr
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 3Plus1 Technology Inc, Ramchandran Amit, Reid Hauser John Jr filed Critical 3Plus1 Technology Inc
Priority to EP05771043A priority Critical patent/EP1779256A4/fr
Priority to JP2007521614A priority patent/JP2008507039A/ja
Priority to CA002572954A priority patent/CA2572954A1/fr
Publication of WO2006017339A2 publication Critical patent/WO2006017339A2/fr
Publication of WO2006017339A3 publication Critical patent/WO2006017339A3/fr

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7839—Architectures of general purpose stored program computers comprising a single central processing unit with memory
    • G06F15/7864—Architectures of general purpose stored program computers comprising a single central processing unit with memory on more than one IC chip
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/3001—Arithmetic instructions
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30018—Bit or string instructions
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30032—Movement instructions, e.g. MOVE, SHIFT, ROTATE, SHUFFLE
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30036—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
    • G06F9/30038—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations using a mask
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Mathematical Physics (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • Computational Mathematics (AREA)
  • Advance Control (AREA)
  • Microcomputers (AREA)

Abstract

Un mode de réalisation de la présente invention inclut un processeur hétérogène, très performant et à géométrie variable comportant un sous-processeur de type W capable de traiter W bits en parallèle, W étant un entier, et au moins un sous-processeur de type N capable de traiter N bits en parallèle, N étant un entier inférieur à W d'un facteur deux. Le processeur inclut en outre, d'une part un bus partagé couplant le sous-processeur de type W à celui de type N, et d'autre part une mémoire partagée couplée au sous-processeur de type W et au sous-processeur de type N. En l'occurrence, le sous-processeur de type W réorganise la mémoire pour admettre l'exécution d'applications permettant des opérations rapides.
PCT/US2005/024867 2004-07-13 2005-07-12 Architecture de processeur programmable WO2006017339A2 (fr)

Priority Applications (3)

Application Number Priority Date Filing Date Title
EP05771043A EP1779256A4 (fr) 2004-07-13 2005-07-12 Architecture de processeur programmable
JP2007521614A JP2008507039A (ja) 2004-07-13 2005-07-12 プログラム可能なプロセッサのアーキテクチャ
CA002572954A CA2572954A1 (fr) 2004-07-13 2005-07-12 Architecture de processeur programmable

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US58769104P 2004-07-13 2004-07-13
US60/587,691 2004-07-13
US59841704P 2004-08-02 2004-08-02
US60/598,417 2004-08-02

Publications (2)

Publication Number Publication Date
WO2006017339A2 WO2006017339A2 (fr) 2006-02-16
WO2006017339A3 true WO2006017339A3 (fr) 2006-04-06

Family

ID=35839807

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2005/024867 WO2006017339A2 (fr) 2004-07-13 2005-07-12 Architecture de processeur programmable

Country Status (5)

Country Link
EP (1) EP1779256A4 (fr)
JP (1) JP2008507039A (fr)
KR (1) KR20070055487A (fr)
CA (1) CA2572954A1 (fr)
WO (1) WO2006017339A2 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7856246B2 (en) 2007-03-21 2010-12-21 Nokia Corporation Multi-cell data processor

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2474901B (en) * 2009-10-30 2015-01-07 Advanced Risc Mach Ltd Apparatus and method for performing multiply-accumulate operations
US9430369B2 (en) * 2013-05-24 2016-08-30 Coherent Logix, Incorporated Memory-network processor with programmable optimizations
JP6102528B2 (ja) 2013-06-03 2017-03-29 富士通株式会社 信号処理装置及び信号処理方法
KR102235803B1 (ko) * 2017-03-31 2021-04-06 삼성전자주식회사 반도체 장치

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5878085A (en) * 1997-08-15 1999-03-02 Sicom, Inc. Trellis coded modulation communications using pilot bits to resolve phase ambiguities
US5909559A (en) * 1997-04-04 1999-06-01 Texas Instruments Incorporated Bus bridge device including data bus of first width for a first processor, memory controller, arbiter circuit and second processor having a different second data width
US6166748A (en) * 1995-11-22 2000-12-26 Nintendo Co., Ltd. Interface for a high performance low cost video game system with coprocessor providing high speed efficient 3D graphics and digital audio signal processing
US20040078411A1 (en) * 2002-10-22 2004-04-22 Joshua Porten Galois field arithmetic unit for use within a processor

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB9509989D0 (en) * 1995-05-17 1995-07-12 Sgs Thomson Microelectronics Manipulation of data
AU9026498A (en) * 1997-08-22 1999-03-16 Jens Korsgaard Fluid swivel for oil production vessels and tanker vessels
JP2991694B1 (ja) * 1998-06-12 1999-12-20 日本放送協会 デジタル送信装置および受信装置
US6643332B1 (en) * 1999-07-09 2003-11-04 Lsi Logic Corporation Method and apparatus for multi-level coding of digital signals
US6539467B1 (en) * 1999-11-15 2003-03-25 Texas Instruments Incorporated Microprocessor with non-aligned memory access

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6166748A (en) * 1995-11-22 2000-12-26 Nintendo Co., Ltd. Interface for a high performance low cost video game system with coprocessor providing high speed efficient 3D graphics and digital audio signal processing
US5909559A (en) * 1997-04-04 1999-06-01 Texas Instruments Incorporated Bus bridge device including data bus of first width for a first processor, memory controller, arbiter circuit and second processor having a different second data width
US5878085A (en) * 1997-08-15 1999-03-02 Sicom, Inc. Trellis coded modulation communications using pilot bits to resolve phase ambiguities
US20040078411A1 (en) * 2002-10-22 2004-04-22 Joshua Porten Galois field arithmetic unit for use within a processor

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
HEINRICH J.: "MIPS R4000 Microprocessor User's Manual.", 1994, pages: 1 - 21, XP002928551 *

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7856246B2 (en) 2007-03-21 2010-12-21 Nokia Corporation Multi-cell data processor

Also Published As

Publication number Publication date
EP1779256A4 (fr) 2007-11-28
CA2572954A1 (fr) 2006-02-16
KR20070055487A (ko) 2007-05-30
WO2006017339A2 (fr) 2006-02-16
EP1779256A2 (fr) 2007-05-02
JP2008507039A (ja) 2008-03-06

Similar Documents

Publication Publication Date Title
WO2006017482A3 (fr) Compilation hierarchique d'une architecture processeur programmable
WO2007121275A3 (fr) Interface configurable pour relier plusieurs chipsets pour une communication sans fil avec un (multi)processeur programmable
WO2014130514A3 (fr) Exécution en parallèle de requêtes de traitement d'événement continu (cep)
WO2008003930A3 (fr) Techniques pour une exécution de programme
WO2006093662A3 (fr) Processeur de donnees par paquets presentant une architecture d'ensemble de registres etendus
WO2007095397A3 (fr) Unite de traitement programmable
WO2008074382A8 (fr) Procédé permettant d'obscurcir un code de programme informatique
GB2447200A (en) Transactional memory in out-of-order processors
MXPA05006966A (es) Sistema y metodo para la instalacion y ejecucion de una aplicacion de preferencia.
WO2006110522A3 (fr) Integration d'une logique programmable dans une architecture d'ordinateur personnel
WO2007145742A3 (fr) Traitement de feuille de calcul multifilière avec niveaux de dépendance
WO2008027574A3 (fr) Accélérateur de traitement de flux
US9588923B2 (en) Flow pinning in a server on a chip
SG155253A1 (en) Global switch resource manager
WO2006121748A8 (fr) Systemes et procedes destines a l'interfacage d'une application d'un premier type avec plusieurs applications d'un second type
US20130346428A1 (en) Processing columns in a database accelerator while preserving row-based architecture
WO2006017339A3 (fr) Architecture de processeur programmable
GB2455254A (en) Twice issued conditional move instruction,and applications thereof
WO2005088441A3 (fr) Insertion de bits dans un mot de donnee
Bertazzi et al. The bin packing problem with item fragmentation: a worst-case analysis
Vijay et al. Arm processor architecture
Prieto-Avalos et al. Reduction waste by combining lean manufacturing and six sigma in an electronics industry
KR20150107138A (ko) 마이크로프로세서에서의 명령어 디코딩 방법
WO2005072298A3 (fr) Circuit a ligne de retard configurable
TWI617987B (zh) 實現線速互連結構的方法、電腦系統、與非暫時性電腦可讀取記憶體

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A2

Designated state(s): AE AG AL AM AT AU AZ BA BB BG BR BW BY BZ CA CH CN CO CR CU CZ DE DK DM DZ EC EE EG ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KM KP KR KZ LC LK LR LS LT LU LV MA MD MG MK MN MW MX MZ NA NG NI NO NZ OM PG PH PL PT RO RU SC SD SE SG SK SL SM SY TJ TM TN TR TT TZ UA UG US UZ VC VN YU ZA ZM ZW

AL Designated countries for regional patents

Kind code of ref document: A2

Designated state(s): BW GH GM KE LS MW MZ NA SD SL SZ TZ UG ZM ZW AM AZ BY KG KZ MD RU TJ TM AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IS IT LT LU LV MC NL PL PT RO SE SI SK TR BF BJ CF CG CI CM GA GN GQ GW ML MR NE SN TD TG

121 Ep: the epo has been informed by wipo that ep was designated in this application
WWE Wipo information: entry into national phase

Ref document number: 2572954

Country of ref document: CA

WWE Wipo information: entry into national phase

Ref document number: 2007521614

Country of ref document: JP

Ref document number: 113/CHENP/2007

Country of ref document: IN

Ref document number: 2005771043

Country of ref document: EP

WWE Wipo information: entry into national phase

Ref document number: 1020077000909

Country of ref document: KR

NENP Non-entry into the national phase

Ref country code: DE

WWW Wipo information: withdrawn in national office

Ref document number: DE

WWE Wipo information: entry into national phase

Ref document number: 200580030649.7

Country of ref document: CN

WWP Wipo information: published in national office

Ref document number: 2005771043

Country of ref document: EP