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WO2006003844A1 - Dispositif semi-conducteur, procédé de fabrication dudit dispositif et appareil électronique - Google Patents

Dispositif semi-conducteur, procédé de fabrication dudit dispositif et appareil électronique Download PDF

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Publication number
WO2006003844A1
WO2006003844A1 PCT/JP2005/011605 JP2005011605W WO2006003844A1 WO 2006003844 A1 WO2006003844 A1 WO 2006003844A1 JP 2005011605 W JP2005011605 W JP 2005011605W WO 2006003844 A1 WO2006003844 A1 WO 2006003844A1
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WO
WIPO (PCT)
Prior art keywords
semiconductor device
manufacturing
source
conductive material
thin film
Prior art date
Application number
PCT/JP2005/011605
Other languages
English (en)
Japanese (ja)
Inventor
Katsura Hirai
Original Assignee
Konica Minolta Holdings, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Konica Minolta Holdings, Inc. filed Critical Konica Minolta Holdings, Inc.
Priority to JP2006528615A priority Critical patent/JP4946438B2/ja
Publication of WO2006003844A1 publication Critical patent/WO2006003844A1/fr

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B20/00—Read-only memory [ROM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0241—Manufacture or treatment of multiple TFTs using liquid deposition, e.g. printing
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H10K71/60—Forming conductive regions or layers, e.g. electrodes
    • H10K71/611—Forming conductive regions or layers, e.g. electrodes using printing deposition, e.g. ink jet printing

Definitions

  • the present invention relates to a semiconductor device, a manufacturing method thereof, and an electronic device.
  • an IC card As an example of an IC card, a radio wave (electromagnetic wave) that also generates a coil force of a reader / writer device is received by a coil on the IC card side, and power, a clock, and a transmission / reception signal are generated, and a command received from the reader / writer device is received.
  • An RFID (Radio Frequency Identification) type IC card hereinafter referred to as an RFID card) to be processed has been proposed (for example, Patent Document 2).
  • FIG. 13 is a block diagram showing an electrical configuration of a conventional RFID card.
  • the RFID card 10 rectifies the received AC signal connected to the coil 12 and converts it into a DC voltage, and drives the circuit of the RFID card 10 based on the DC voltage converted by the rectifier circuit 13.
  • a power supply circuit 14 that generates the required power supply voltage VDD, a demodulation circuit 15 that extracts (demodulates) received information contained in an AC signal supplied from the outside via the coil 12, and an AC signal that includes transmission information are formed.
  • the memory circuit 18 Based on the received information demodulated by the modulation circuit 16 that modulates and drives the coil 12, the memory circuit 18 that stores identification information for identifying the RFID card 10 and the demodulation circuit 15, the data is stored in the memory circuit 18.
  • Read / write control circuit 17 that performs processing such as writing transmission data and outputting transmission information read from memory circuit 18 to modulation circuit 16 and protocol control for transmission and reception with an external reader / writer (not shown). It is more structured etc..
  • the AC signal received by the coil 12 is input to the demodulation circuit 15, where it is demodulated from the ASK modulated (amplitude modulated) signal, and the data signal is reproduced.
  • the reproduced data is written into the memory circuit 18 by the read / write control circuit 17 that performs read / write control of the memory circuit 18 and transmission / reception protocol control.
  • transmission from the RFID card to the reader / writer Data is read from the memory circuit 18 by the read / write control circuit 17, LSK (load modulation) is performed on the coil signal by the modulation circuit 16, and the data is transmitted.
  • the RFID card 10 as an electronic device needs to hold an ID code in order to identify each other during the exchange of data with the reader / writer.
  • the memory circuit 18 that holds the ID code, it is common to use an electrically writable / erasable nonvolatile memory such as EEPROM (Electrically Erasable Programmable Read Only Memory) (for example, Patent Document 2).
  • EEPROM Electrically Erasable Programmable Read Only Memory
  • Patent Document 2 EEPROM (Electrically Erasable Programmable Read Only Memory)
  • Patent Document 1 JP-A-2-13046
  • Patent Document 2 Japanese Patent Laid-Open No. 2000-172806
  • Patent Document 3 Japanese Patent Laid-Open No. 2002-344113
  • the EEPROM of Patent Document 2 can be written with an ID code or a production number while being incorporated in an electronic device.
  • an invalid ID code or serial number is written.
  • a portable device such as an IC tag or a mobile phone
  • information is written via radio waves, so there is a risk that the contents of the EEPROM can be rewritten relatively easily.
  • an ID code and a manufacturing number can be written in a state of being incorporated in an electronic device.
  • An object of the present invention is to provide a semiconductor device that can be rewritten and difficult to rewrite, and a manufacturing method thereof.
  • the present inventor has found that the object of the present invention can be achieved by adopting one of the following configurations.
  • a plurality of thin film transistors each including a gate electrode, a gate insulating layer, and a source electrode and a drain electrode connected by a semiconductor layer on a substrate, and a gate line connecting the plurality of gate electrodes.
  • a semiconductor device having a thin film transistor array having a source line connecting the source electrode and a bit line connecting the drain electrode, the connection between the source electrode and the source line, and the drain electrode and the A semiconductor device having a separation portion in which at least one of the connections to the bit line is separated and can be connected with a conductive material.
  • a plurality of thin film transistors each including a gate electrode, a gate insulating layer, and a source electrode and a drain electrode connected by a semiconductor layer, and a gate line connecting the plurality of gate electrodes
  • a method for manufacturing a semiconductor device comprising: a connection step of connecting a separation portion between the drain electrode and the bit line, which has been previously separated based on the wiring pattern input in step 1, with a conductive material.
  • connection process is based on the wiring pattern input in the input process.
  • connection step the insulating portion to be insulated is insulated with a fluid insulating material based on the wiring pattern input in the input step, and then the other separating portion is connected with a conductive material.
  • the storage means is a semiconductor manufactured by the manufacturing method according to (1) above in (1).
  • FIG. 1 is a partial circuit diagram of a TFT array according to the present invention.
  • FIG. 2 (a) is a plan view of the TFT shown in FIG. 1, and FIG. 2 (b) is a cross-sectional view taken along the line AA in FIG. 2 (a).
  • FIG. 2 (c) is a cross-sectional view showing a state in which the source separation portion is filled with a conductive material in FIG. 2 (b).
  • FIG. 3 is a partial circuit diagram of a TFT array according to another embodiment of the present invention.
  • FIG. 4 (a) is a plan view of the TFT shown in FIG. 3, and FIG. 4 (b) is a cross-sectional view taken along the line BB in FIG. 4 (a).
  • FIG. 4 (c) is a cross-sectional view showing a state where the drain isolation portion is filled with the conductive material in FIG. 4 (b).
  • FIG. 5 is a schematic view showing an outline of a manufacturing process of a semiconductor device according to the present invention.
  • FIG. 6 is a state transition diagram of a TFT in the manufacturing process of the semiconductor device according to the invention.
  • FIG. 7 is a schematic view showing a pattern of separation part connection by an ink jet method.
  • FIG. 8 is a schematic diagram showing an outline of a manufacturing process of a semiconductor device according to another embodiment of the present invention.
  • FIG. 9 is a state transition diagram of a TFT in a manufacturing process of a semiconductor device according to another embodiment of the present invention.
  • FIG. 10 is a block diagram of a TFTROM.
  • FIG. 11 is a block diagram showing an electrical configuration of an RFID card equipped with a TFTROM.
  • FIG. 12 is an external perspective view of an RFID card equipped with a TFTROM.
  • FIG. 13 is a block diagram showing an electrical configuration of a conventional RFID card.
  • FIG. 1 shows a thin film transistor (hereinafter referred to as TFT) array which is a semiconductor device according to the present invention.
  • FIG. 6 is a partial circuit diagram of FIG.
  • the TFT array 66 includes a TFT 20, a source line 22, and a source separation unit 2 arranged in a matrix.
  • the TFT 20 is a field effect transistor, and includes a source electrode 21, a gate electrode 24, and a drain electrode 26.
  • the source line 22 is a bus provided so that the source electrodes 21 of the TFTs 20 arranged in the Y direction in the figure can be connected to each other. At least one source line 22 is provided for each column of the TFTs 20 arranged in the X direction. It is installed.
  • the source separation unit 23 which is the separation unit of the present invention, includes a source electrode 21 and a source line 2 of each TFT 20.
  • the source electrode 21 and the source line 22 are electrically separated, and can be connected with a conductive material by a method described later.
  • the gate line 25 is a bus that connects the gate electrodes 24 of the TFTs 20 arranged in the X direction in the figure, and at least one gate line 25 is provided for each row of the TFTs 20 arranged in the Y direction! /
  • FIG. 2 is a structural diagram of the TFT 20 shown in FIG. 1 and its peripheral part.
  • Fig. 2 (a) is a plan view of the TFT 20 and its peripheral part
  • Fig. 2 (b) is a cross-sectional view taken along the AA line in Fig. 2 (a).
  • FIG. 2 (c) shows a state where the conductive material 32 is filled in the source separator 23 in FIG. 2 (b).
  • the same symbols are assigned to the same elements as those described above in order to avoid duplication of explanation.
  • the TFT 20 has a gate line 25 connected to a gate electrode (not shown) on a base material 35 that is an insulating material, and an insulating layer 34 formed thereon, and further a semiconductor 31 and a bit line 27 formed thereon.
  • the source electrode 21 and the source line 22 are stacked, and are covered with an insulating layer 33 except for the source separation portion 23.
  • the semiconductor 31 is connected to the bit line 27 and the source electrode 21 provided at a constant interval.
  • the surface where the semiconductor 31 and the bit line 27 are connected corresponds to the drain electrode 26 shown in FIG.
  • the source electrode 21 and the source line 22 are formed so that a source separation portion 23 whose upper surface is opened up to the insulating layer 34 is formed. It is provided.
  • the source separator 23 is selectively filled in accordance with a desired wiring pattern with the conductive material 32 supplied from the opened upper cover, and is electrically connected. Is done.
  • the conductive material 32 any material may be used as long as it includes a conductive material.
  • a conductive polymer described later, a conductive paste containing metal fine particles, An ink or a metal thin film precursor material can be suitably used.
  • Materials for the metal fine particles include platinum, gold, silver, nickel, chromium, copper, iron, tin, antimony lead, tantalum, indium, palladium, tellurium, rhenium, iridium, aluminum, ruthenium, germanium, Molybdenum, tungsten, zinc, or the like can be used.
  • the solvent or dispersion medium is preferably a solvent or dispersion medium containing 60% or more, preferably 90% or more of water in order to suppress damage to the organic semiconductor.
  • conductive polymer dispersions whose conductivity has been improved by doping or the like, such as conductive polyarine, conductive polypyrrole, conductive polythiophene, polyethylene dioxythiophene and polysulfonic acid complex, etc. are also preferably used.
  • a ⁇ -conjugated material is used as the semiconductor 31 material.
  • polypyrrole such as polypyrrole, poly ( ⁇ -substituted pyrrole), poly (3-substituted pyrrole), and poly (3,4-disubstituted pyrrole).
  • Polythiophene poly (3-substituted thiophene), poly (3,4-disubstituted thiophene), polybenzones such as polybenzothiophene, polyisothianaphthenes such as polyisothianaphthene, and polychelenylene bilene
  • Polyethylene vinylenes poly ( ⁇ phenylene vinylenes) such as poly ( ⁇ phenylene vinylene), polyaniline, poly ( ⁇ substituted alkylene), poly (trisubstituted vinyl), poly (2, (3 substituted alkylenes), polyacetylenes such as polyacetylene, polydiacetylenes such as polydiacetylene, polyazulenes such as polyazulene, Polypyrenes such as polypyrene, polycarbazole, poly rubazoles such as poly ( ⁇ -substituted carbazole), polyselenophenes such as polyselenophene, polyfurans such as polyfuran
  • oligomers such as ⁇ , ⁇ -bis (3-butoxypropyl) -a-sectiophene and styrylbenzene derivatives can also be suitably used.
  • copper phthalocyanine is a metal phthalocyanine such as fluorine-substituted copper phthalocyanine described in JP-A-11-251601, naphthalene 1, 4, 5, 8-tetracarboxylic acid diimide, N, N, Bis (4 trifluoromethylbenzyl) naphthalene 1, 4, 5, 8—tetra-force With rubonic acid diimide, N, N, 1 bis (1H, 1H—perfluorooctyl), N, N, Naphthalene such as bis (1H, 1H perfluorobutyl) and N, N, dioctylnaphthalene 1, 4, 5, 8-tetracarboxylic diimide derivatives, naphthalene 2, 3, 6, 7 tetracarboxylic diimide Tetracarboxylic acid diimides and anthracene 2, 3, 6, 7-tetra force Fused ring tetra force such as anthracene te
  • thiophene, vinylene, thiazylene vinylene, phenylene vinylene, ⁇ -phenylene these substitution products, or a combination of two or more thereof as a repeating unit
  • Number of repeating units ⁇ Force ⁇ 10 or polymers having a repeating unit ⁇ of 20 or more, condensed polycyclic aromatic compounds such as pentacene, fullerenes, condensed ring tetracarboxylic diimides, metal phthalocyanines At least one selected from the group is preferred.
  • organic semiconductor materials include tetrathiafulvalene (TTF) -tetracyanoquinodimethane (TCNQ) complex, bisethylenetetrathiafulvalene (BEDTTTF) -perchloric acid complex, BEDTTTF iodine complex, TCNQ iodine complex, etc.
  • TTF tetrathiafulvalene
  • BEDTTTF bisethylenetetrathiafulvalene
  • TCNQ iodine complex etc.
  • the organic molecular complex can also be used.
  • ⁇ -conjugated polymers such as polysilane and polygermane can also be used as organic'inorganic hybrid materials described in JP-A-2000-260999.
  • a material having a functional group such as acrylic acid, acetamido, dimethylamino group, cyano group, strong lpoxyl group, nitro group, benzoquinone derivatives, tetracyanethylene and tetracyanoquinodimethane, and their A material that serves as an acceptor such as a derivative, a material having a functional group such as an amino group, a triphenyl group, an alkyl group, a hydroxyl group, an alkoxy group, or a phenyl group, or a substituted amine such as phenoldiamine.
  • a material having a functional group such as acrylic acid, acetamido, dimethylamino group, cyano group, strong lpoxyl group, nitro group, benzoquinone derivatives, tetracyanethylene and tetracyanoquinodimethane, and their A material that serves as an acceptor such as a derivative, a material having a functional group such as an amino group
  • Anthracene benzoanthracene, substituted benzoanthracene, pyrene, substituted pyrene, force rubazole and its derivatives, tetrathiafulvalene and its derivatives, etc.
  • a so-called doping process may be performed.
  • the doping is an electron-donating molecule (acceptor) or an electron-donating molecule (donor). Is introduced into the thin film as a dopant. Therefore, the doped thin film is a thin film containing the condensed polycyclic aromatic compound and the dopant. Known dopants can be used.
  • a resin material such as a plastic film sheet can be preferably used.
  • the plastic film include polyethylene terephthalate, polyethylene naphthalate, polyethersulfone, polyetherimide, polyetherketone, polyphenylene sulfide, polyacrylate, polyimide, polycarbonate, cellulose triacetate, and cellulose acetate propionate. Film.
  • the TFT array can be manufactured by a known semiconductor manufacturing process.
  • the TFT20 size is a rectangle or square with sides of 20 ⁇ m to 100 ⁇ m, and the bus line width including the bit line 27, source line 22, and gate line 25 is 10 ⁇ m.
  • the distance between the source electrode 21 and the source line 22 of the source separation unit 23 is 10 ⁇ m to 40 ⁇ m.
  • FIG. 3 is a circuit diagram of a part of a TFT array 66, which is a semiconductor device according to another embodiment of the present invention.
  • a difference from the TFT array 66 shown in FIG. 1 is that, instead of the source isolation portion 23 in FIG. 1, a drain isolation portion 41 corresponding to the isolation portion of the present invention is provided between the drain electrode 26 and the bit line 27. This is the point in between.
  • FIG. 4 is a structural diagram of the TFT 20 shown in FIG. Figure 4 (a) is a plan view of TFT20.
  • FIG. 4 (b) is a cross-sectional view taken along section B-B in Fig. 4 (a).
  • FIG. 4 (c) shows the state in which the drain separating part 41 of the TFT 20 is filled with the conductive material 32 in FIG. 4 (b).
  • FIG. 5 is a schematic diagram showing an outline of the manufacturing process of the semiconductor device according to the present invention.
  • the manufacturing process of the semiconductor device includes an identification information input unit 61, a wiring pattern generation unit 62, an ink jet printer 63, a heating unit 64, a sealing unit 65, and a transport unit 67. Not shown, it is controlled intensively by the control unit.
  • the identification information input unit 61 is composed of input devices such as a CPU (Central Processing Unit), a work memory, a storage unit, a display unit, a keyboard, etc. (not shown), and an ID code and a serial number written in the TFT array 66 And the like.
  • the identification information generated by the identification information input unit 61 is sent to the wiring pattern generation unit 62.
  • the wiring pattern generation unit 62 includes a CPU (Central Processing Unit), a work memory, a storage unit, and the like (not shown), and is based on the identification information sent from the identification information input unit 61 and the model information of the inkjet printer 63. To the wiring pattern information of the source separation unit 23 of the TFT array, and further to the control data such as allocation to the head and nozzle (not shown) of the inkjet printer 63, alignment of the ejection start position, and the number of ejections. To the Inkjet printer 63.
  • a CPU Central Processing Unit
  • the inkjet printer 63 applies a conductive material (not shown) to the TFT array 66 based on the control data transferred from the wiring pattern generation unit 62, and the wiring pattern of the conductive material is applied to the TFT array 66.
  • an ink containing metal particles containing any one of platinum, gold, silver, copper, cobalt, chromium, iridium, nickel, palladium, molybdenum, and tungsten can be used.
  • the heating unit 64 includes a hot plate, lamp annealing, and the like, and has a function of baking the metal particles by heating and drying the solvent of the ink 72 at 100 ° C to 300 ° C.
  • the sealing portion 65 has a function of applying a sealing material to insulate and protect the TFT array from moisture.
  • the TFT array is covered with a sealing material by a spray coating method, a blade coating method, a printing method, or an ink jet method.
  • sealing material polyimide, polyamide polybulal alcohol, polybulfenol, polyester, and polyacrylate are preferable.
  • the transport unit 67 includes rollers, a belt, a motor, a support material, a drive circuit, and the like (not shown).
  • the transport unit 67 supports and transports the TFT array, forms a wiring pattern by the ink jet printer 63, performs heat treatment by the heating unit 64, and seals 65. The sealing is performed continuously.
  • FIG. 6 is a cross-sectional view showing the state transition of the TFT 20 shown in FIG. 1 and FIG. 2 in the manufacturing process shown in FIG. 5, where the separation part is selectively connected with a conductive material (a — The cases where the separator is not connected are shown in (b–l), (b–2), and (b–3) in 1), (a–2), and (a–3).
  • the TFT array 66 having the source isolation portion between the source line and the source electrode will be described as an example.
  • the TFT array having the drain isolation portion between the bit line and the drain electrode No. 67 is applied so that the drain isolation portion is electrically connected or isolated in place of the source isolation portion.
  • the TFT array 66 located at the position PO is transported to the ejection position P 1 of the ink jet printer 63.
  • Fig. 6 (a-1) (b-l)) o TFT array 66 transported to PI receives conductive material (ink 72 containing metal particles) from wiring pattern generator 62 by ink jet printer 63.
  • a predetermined wiring pattern is applied to the source separation part 23 of the TFT array according to the control data sent (FIG. 6 (a-2)).
  • the ink 72 is not applied to the separation portion that is not connected (FIG. 6 (b-2)).
  • FIG. 7 is a schematic diagram showing how the ink 72 is ejected from the ink jet printer 63 of FIG.
  • the ink 72 is ejected from the head 74 to the TFT array 66 through the nozzle 73 toward the source separation unit 23.
  • the ejection means that the ink is ejected also with the nozzle force
  • the application means a state where the ejected ink has landed on the separation portion.
  • the source separation unit 23 on which the ink 72 has landed is filled with the ink 23.
  • the TFT array 66 to which the ink 72 has been applied by the inkjet printer 63 is conveyed to the heating unit 64 (P2).
  • the heating unit 64 the solvent contained in the ink 72 applied by the ink jet printer 63 is heated and dried, and the conductive material is baked to electrically connect the separation unit 23 to which the ink 72 has been applied.
  • the TFT array 66 transported to the position P3 is sealed with the sealing material 71 at the sealing portion 65 (P3) (FIGS. 6 (a-3) (b-3)).
  • an ID code or a serial number is used as identification information, and each separation part of TFT array 66 is connected with a wiring pattern based on the identification information.
  • identification information not shown, using the image information such as a face photograph, logo mark, fingerprint, etc. acquired by an image capture device such as a digital still camera or scanner, and connecting each separation part of the TFT array 66 with an image-like wiring pattern It may be.
  • a signal output from the TFT array 66 having an image-like wiring pattern can be used as identification information of an electronic device in which the TFT array 66 is incorporated, and a one-time password or time
  • identification information for temporary use such as restricted card keys
  • the amount of the ink 72 applied to the source separation unit 23 may be changed stepwise based on the input identification information.
  • the amount of the ink 72 to be applied is changed by changing the area covering the source separation unit 23 by a known area gradation image forming method, or changing the area covering the source separation unit 23 by a known overlaid image forming method. Or change the thickness.
  • FIG. 8 is a schematic diagram showing an outline of the manufacturing process of the semiconductor device according to the present invention.
  • the manufacturing process of the semiconductor device includes a heating unit 64 and a sealing unit in the manufacturing process illustrated in FIG.
  • a conductive material supply unit 80 is added between 65.
  • the wiring pattern generation unit 62 converts the identification information sent from the identification information input unit 61 into pattern information, further generates control data for the wiring pattern information power, and transfers the control data to the inkjet printer 63.
  • the inkjet printer 63 discharges an insulating material, which will be described later, to the TFT array on the basis of the control data transferred from the wiring pattern generation unit 62, and the insulating material to the TFT array 66.
  • a wiring pattern is formed using a material.
  • the insulating material it is possible to use an ink containing polyimide, polyamide polybulal alcohol, polybuluphenol, polyester, polyacrylate, or the like.
  • the conductive material supply unit 80 is insulated by the inkjet printer 63 by applying the above-described fluid conductive material to the entire surface of the TFT array, or by bringing a conductive sheet or aluminum foil into close contact with the entire surface of the TFT array. It has a function of electrically connecting the source separation part 23 when the material 81 is applied. Since the source separation part 23 is coated with an insulating material in advance by the ink jet printer 63, the insulating material 81 is applied and only the base separation part is connected with a conductive sheet or aluminum foil.
  • FIG. 9 is a cross-sectional view showing the state transition of the TFT 20 shown in FIGS. 1 and 2 in the manufacturing process shown in FIG. 8, where the source separation portion 23 is selectively applied with an insulating material 81.
  • (d 1), (d-2), (d-3), (d-4) are not coated with the source separator 23, (c 1), (c-2), (b-3) ) and (c 4).
  • the TFT array 66 at the position PO is transported to the ejection position P 1 of the ink jet printer 63. (Fig. 9 (c 1) (d- 1))
  • a predetermined wiring pattern is applied to the source separation unit 23 of the TFT array 66 in accordance with the control data sent from the wiring pattern generation unit 62 (FIG. 9 (d-2)). .
  • the TFT array 66 transported to the position P2 is heated, dried, and baked, and then adhered to the position P3 with a conductive material 82 such as a conductive sheet or aluminum foil.
  • the source separation portion 23 coated with the insulating material 81 is filled with the insulating material 81, it remains electrically insulated (Fig. 9 (d-3)). 81 is applied and the V-shaped separation part 23 is electrically connected by a conductive material 82 such as a conductive sheet or aluminum foil (FIG. 9 (c 3)).
  • the TFT array 66 transported to the position P4 is sealed with a sealing material such as an insulating sheet 83 at the sealing portion 65 (Fig. 9 (c 4) (d-4)) G
  • image information such as a face photograph or logo mark may be used as identification information, and each separation part of the TFT array 66 may be connected with an image-like wiring pattern! / Needless to say! /.
  • TFT ROM Read Only Memory
  • FIG. 10 is a circuit diagram schematically showing the concept of the TFTROM 100 using the TFT array 66 shown in FIG. The same configuration is used when the TFT array 67 shown in FIG.
  • TFTROM100 consists of TFT array 66, ROW decoder 551, COLUMN decoder 552
  • the TFT array 66 has the same configuration as the TFT array 66 shown in FIG. 1, and is arranged in a matrix form TFT201 to TFT205, gate lines 251 to 253, bit lines 27, source lines 221 to 2
  • the TFTROM 100 has data written in advance in storage elements arranged in two dimensions, and the contents are not lost even if the power supply is turned off and on.
  • the device is accessed using the address lines in the row and column directions.
  • the accessed storage element outputs its contents.
  • TFTs 201 to 205 are the TFTs 20 described above with reference to FIG.
  • the ROW decoder 551 and the COLUMN decoder 552 are circuits that decode binary address signal input from an external circuit (not shown).
  • the gate lines 251 to 253 are ROM address lines, and are connected to the output of the ROW decoder 551 by connecting the gate electrodes 24 in the X row direction.
  • the source lines 221 to 224 are the TFTROM 100 address lines, and the COLUMN decoder 5
  • the bit line 27 is a ROM data line, and is connected to the input of the buffer 53 by connecting all the drain electrodes 26 !.
  • One of the resistors 52 is connected to the power supply VDD 51 and the other is connected to the bit line 27.
  • the resistor 52 functions as a pull-up resistor to maintain the VDD potential.
  • the buffer 53 is a voltage level conversion IC (integrated circuit) for causing the external circuit to match the voltage of the bit line 27 that is the output of the TFTs 201 to 205.
  • One of the source lines 221 to 223 is connected to the source separator 23 and the other is connected to the output of the COLUMN decoder 552 !.
  • ROW address signal input from an external circuit (not shown) enables one of the outputs of the ROW decoder 551 to be enabled.
  • the COLUMN decoder 5 receives a COLUMN address signal input from an external circuit.
  • the COLUMN decoder 552 sets the source line 221 to low (LOW potential) and the other source lines 222 to 224 to high (HI potential).
  • the source isolation part 23 connected to the TFT 201 is connected by the conductive material 32, so that the COLUMN is connected from the power source VDD51 via the resistor 52, bit line 27, TFT201, and source line 221.
  • the potential of the bit line 27 is converted by the output buffer 53, and the output 54 to the external circuit becomes low. Since the other source lines 222 to 224 are high, no current flows between the drains and sources of the TFTs 202 to 204.
  • the source separation part 23 of the TFT 202 is not connected by the conductive material 32, and therefore the bit line 27 from the power supply VDD 51
  • the current does not flow to the output of the COLUMN decoder 552 via the TFT 202 and the source line 202, and the bit line 27 maintains the same potential as the power supply VDD51. Therefore, the potential of the bit line 27 becomes high, the voltage is converted by the output buffer 53, and the output 54 to the external circuit becomes high.
  • one of the TFTs 201 to 205 is selected by the ROW address signal and the COLUMN address signal from the external circuit, and the source connected to the selected TFT.
  • the separator 23 When the separator 23 is connected with a conductive material, the output to the external circuit is low, and when it is connected, it is high.
  • the output data related to one read operation of the TFTROM 100 shown in FIG. 10 is 1 bit.
  • the source separation unit 23 if the amount of ink 72 applied to the source separation unit 23 is changed stepwise based on the input identification information, the source separation is performed. Depending on the amount of the conductive material that connects part 23, the output signal strength differs, and it becomes possible to handle multi-value signals in one TFT.
  • the ROW decoder 551, the COLUMN decoder 552, and the output buffer 53 are configured to detect the signal strength so that a multilevel signal can be handled.
  • FIG. 11 is an electrical block diagram of the RFID card 9 on which the TFTROM 100 is mounted.
  • TFTROM 101 which has a plurality of TFTROMs 100 connected in parallel, can be used to obtain multiple bits of output data in a single read operation.
  • the configuration of the memory circuit 98 of the RFID card 9 is different from that of the RFID card of Fig. 13 described above.
  • the memory circuit 98 includes an EEPROM 99 and a TFT ROM 101.
  • EEPROM99 is a read Z write memory and TFTROM101 is a read only memory.
  • the control program and temporarily stored data are written and read by EEPROM99, and the ID code is written to TFTROM101. Since TFTROM101 cannot be easily rewritten, it is possible to realize a system with high security that prevents tampering and counterfeiting.
  • FIG. 12 is an external perspective view showing the configuration of the RFID card 9.
  • the coil 92 is configured by a printed wiring or the like formed in a spiral shape on the substrate 90.
  • the IC 91 includes a rectifier 93 for generating a power supply voltage in FIG. 11, a power supply circuit 94, a demodulation circuit 95 for demodulating data captured from the coil, a modulation circuit 96 for transmitting data to the outside via the coil, data Control circuit 97 that controls the exchange of commands and commands, etc. And EEPROM99, which is part of the memory circuit.
  • TFTROM101 is connected to IC91. Since the TFTROM101 is not built in the IC91, the ID code can be physically written by the customer.
  • the wiring pattern is generated by the method shown in FIGS. 4 to 9 in a state where the TFT ROM 101 is mounted on the RFID force card 9. . In this way, it is possible to easily and quickly create the RFID card 9 that is not easily tampered with or counterfeited.
  • the information writing to the TFTROM 101 of the RFID card 9 is performed by directly using biometrics information such as fingerprints, palm prints, and nose prints using a conductive material instead of the method shown in FIGS. It is also possible to transfer to the TFT array 66 constituting the TF TROM101.
  • the electronic device includes a plurality of thin film transistors including a gate electrode, a gate insulating layer, a source electrode and a drain electrode connected by a semiconductor layer, and a plurality of thin film transistors on a substrate.
  • An electronic device identification comprising: a connection step of connecting with a material; and a step of using a signal output from the semiconductor device connected in the connection step as identification information Broadcast issuing method it is possible to configure the.
  • the image-like conductive material such as fingerprints, palm prints, and nose prints transferred to the TFT array 66 electrically connects specific separation portions of the TFT array 66.
  • the signal output from the TFT array 66 having an image-like wiring pattern can be used as the identification information of the electronic device in which the TFT array 66 is incorporated, with a one-time password or time limit.
  • identification information for the purpose of temporary use, such as card keys, it is possible to easily issue identification information that is not easily tampered with or counterfeited, and it is possible to visually recognize image-like metric information. Since it is easy, unauthorized use such as impersonation can also be prevented.
  • the description content in each of the above embodiments is a preferred example of the semiconductor device and the electronic device according to the present invention, and the present invention is not limited to this.
  • the description has been given by taking an RFID card as an example of an electronic device.
  • the present invention is also applicable to an electronic device such as a RFID tag, a mobile phone, a PDA (Personal Digital Assistant), or a digital still camera. .
  • the separation part is provided between one of the source electrode and the source line or between the drain electrode and the bit line, and the separation part is connected by a conductive material.
  • the separation part can be connected in a state of being mounted on the substrate.
  • the separation part is connected with a conductive material, it is not electrically rewritten or erased.
  • the isolation part that is insulated based on the wiring pattern input in the input process is insulated with the fluid insulating material, and the other isolation part is connected with the conductive material, all the isolation parts are connected. Since it is hermetically sealed with a conductive material or an insulating material, after that, for example, even if the entire TFT array is sealed, there is a wide range of options in selecting a sealing material that does not directly contact the electrode. Spread.
  • the storage means of the electronic device is a semiconductor manufactured by the manufacturing method according to the present invention, the identification information written in the storage means that is not easily affected by physical disturbances. This makes it possible to provide electronic devices that are difficult to be intentionally tampered with at low cost with little effort.

Landscapes

  • Thin Film Transistor (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Memories (AREA)

Abstract

Mémoire dans laquelle on peut écrire lorsqu’elle est montée sur un substrat comme mémoire de stockage du code d’identification ou du numéro de production d’un appareil électronique et dans laquelle la réécriture est très difficile, et son procédé d'écriture. Le dispositif semi-conducteur et son procédé de fabrication sont caractérisés en ce que la partie isolation dans une matrice TFT aménagée entre la source et la ligne de source ou bien entre le drain et la ligne binaire d’une matrice TFT est connectée à un matériau conducteur par un système à jet d’encre selon un motif désiré.
PCT/JP2005/011605 2004-07-06 2005-06-24 Dispositif semi-conducteur, procédé de fabrication dudit dispositif et appareil électronique WO2006003844A1 (fr)

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JP2007208009A (ja) * 2006-02-02 2007-08-16 Hitachi Ltd 有機薄膜トランジスタの製造方法および製造装置
JP2008046846A (ja) * 2006-08-15 2008-02-28 Nippon Telegr & Teleph Corp <Ntt> 電子タグ
EP2016591A1 (fr) * 2006-04-28 2009-01-21 Agfa-Gevaert Element memoire passif non volatile imprimable classiquement et son procede de realisation
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WO2017212972A1 (fr) * 2016-06-06 2017-12-14 東レ株式会社 Matrice mémoire, procédé de fabrication de matrice mémoire, feuille de matrices mémoire, procédé de fabrication de feuille de matrices mémoire, et dispositif de communication sans fil

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