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WO2006048836A1 - Inner bridges for chip-to-chip interconnections in a multi-chip ic package - Google Patents

Inner bridges for chip-to-chip interconnections in a multi-chip ic package Download PDF

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Publication number
WO2006048836A1
WO2006048836A1 PCT/IB2005/053595 IB2005053595W WO2006048836A1 WO 2006048836 A1 WO2006048836 A1 WO 2006048836A1 IB 2005053595 W IB2005053595 W IB 2005053595W WO 2006048836 A1 WO2006048836 A1 WO 2006048836A1
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WIPO (PCT)
Prior art keywords
lead frame
chip
chips
bonding
die
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/IB2005/053595
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French (fr)
Inventor
T. F. Dai
M. J. Wu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Koninklijke Philips NV
US Philips Corp
Original Assignee
Koninklijke Philips Electronics NV
US Philips Corp
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Publication of WO2006048836A1 publication Critical patent/WO2006048836A1/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49575—Assemblies of semiconductor devices on lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49113—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Definitions

  • the invention relates to integrated circuit (IC) packaging. More particularly this invention relates to the packaging of multiple IC devices in a multi-chip module package.
  • IC integrated circuit
  • MOSFET metal-oxide-semiconductor field-effect transistors
  • PMOS p-channel MOS
  • NMOS n-channel MOS
  • CMOS complementary MOS
  • Such MOSFET devices include an insulating material between a conductive gate and silicon- like substrate; therefore, these devices are generally referred to as IGFETs (insulated-gate FET).
  • IGFETs insulated-gate FET
  • Each of these semiconductor devices generally includes a semiconductor substrate on which a number of active devices are formed.
  • the particular structure of a given active device can vary between device types.
  • an active device generally includes source and drain regions and a gate electrode that modulates current between the source and drain regions.
  • Such devices may be digital or analog devices produced in a number of wafer fabrication processes, for example, CMOS, BiCMOS, Bipolar, etc.
  • the substrates may be silicon, gallium arsenide (GaAs) or other substrate suitable for building microelectronic circuits thereon.
  • a given application for an IC often dictates which fabrication process is used in the ICs construction. For example, devices requiring low power may be rendered in CMOS. Analog devices, such as amplifiers, may be rendered in BiCMOS or bipolar technologies. Radio frequency (RF) components or other high speed devices may require that they be built on GaAs substrates. Modern instruments such as cellphones, laptop computers, audio equipment, etc. are built with a mix of IC technologies. In the continuing effort to reduce the size, weight, power consumption of these devices, there are techniques that involve a mix of multiple integrated circuit devices placed into a single package, a multi-chip module (MCM) package.
  • MCM multi-chip module
  • This invention has been found useful in achieving indirect wire connections from a first chip to additional chips.
  • One or more "bridges" are integrated into the MCM lead frame to provide a medium for chip-to-chip connections. Rather than connect two or more chips together with a long bond wire, the wire length may be reduced. Two shorter wires are used in conjunction with the bridge reduce the likelihood of wire sweeping and deformation.
  • the semiconductor device ⁇ comprises a first lead frame adapted and located for a first IC chip at a first die-securing location and an additional lead frame adapted and located for an additional IC chip at an additional die-securing location.
  • Each of the first and second lead frames have respective sets of bonding fingers adapted to provide electrically-bonding connection to the respective first and second IC chips; at least one lead frame bridge is adapted to couple a bonding pad of the first IC chip with a bonding pad of the additional IC chip.
  • the electrically-bonding connection of the respective first and second IC chips includes at least one of the following: a bond wire, direct connection.
  • a multi-chip module (MCM) package for packaging a plurality of semiconductor chips
  • the MCM package comprises a die attach substrate.
  • the lead frame defines a plurality of die attach regions on the die attach surface;
  • the lead frame has a plurality of bonding fingers for each of one of the plurality of die attach regions;
  • the lead frame has a plurality of bridges to facilitate connecting of one or more bonding pads of a first die mounted on the die attach surface with one or more bonding pads of additional dice mounted on the die attach surface.
  • An encapsulating material encapsulates the first die and additional dice and lead frame, providing a seal for the MCM package. Additional features of this embodiment include the lead frame being mounted to the die attach substrate with an insulating material or the lead frame being mounted to the die-attach substrate at one or more bonding fingers with conductive material.
  • a lead frame adapted for use in TAB (tape automated bonding) used in connecting together a plurality of IC chips.
  • the lead frame comprises a first side rail having a plurality of bridges attached thereon, the plurality of bridges having a plurality of bond wire attachment locations and a second side rail having a plurality of bond fingers, the bond fingers attached thereon, the bond fingers arranged around openings to accommodate a plurality of IC chips, the bond fingers arranged to surround substantially all of the IC chips, the bond fingers having a least one bond wire attachment location.
  • Another embodiment according to the present invention is directed to a method for packaging a plurality of chips in a MCM package.
  • the embodiment involves attaching, e.g., by wire bonding, a plurality of chips to an arrangement including a suitable substrate and lead frame. Using bridges, the chips are electrically coupled to one another, thereby providing a set of wire-bonded and bridged chips over the substrate and lead frame. This arrangement is then encapsulated. In an alternative embodiment, the lead frame is trimmed to implement a singular device.
  • the above summary of the present invention is not intended to represent each disclosed embodiment, or every aspect, of the present invention.
  • Other aspects and example embodiments are provided in the figures and the detailed description that follows.
  • the present invention has been found to be useful in making interconnections between multiple IC chips packaged together in a multi-chip module package (MCM) in which using direct connections via bond wires is not feasible owing to input/output pin or power pin configurations among the multiple chips.
  • Bridges are integrated into the lead frame to provide alternative connection points to which wires can be bonded.
  • wire interconnection between chips is often required.
  • the wires may be connected between a first chip and an additional chip directly by wire bonds.
  • FIG. 1 illustrates an example embodiment of an MCM device 100 according to the present invention.
  • the MCM device 100 includes has two integrated-circuit chips, Chip 1 and Chip 2.
  • Chip 1 and Chip 2 have been attached to regions 140, 150, respectively on a substrate 170.
  • a lead frame 130 provides bonding areas to couple Chip 1 and Chip 2 to the package's pins (not illustrated).
  • a plurality of bridges 110 is provided within the lead frame 130.
  • Pins 50 on Chip 1 and pins 60 on Chip 2 are coupled via bridges 110.
  • these bridges 1 10 extend out to package pins 120.
  • a lead frame side rail 105 to provide sufficient strength in that such a lead frame may be spooled on a reel for use in tape automated bonding, in an example process.
  • the MCM devices are packaged then separated from one another as the lead frame side rail 105 is trimmed off after a multiple number of devices have been encapsulated with a suitable molding compound.
  • Lead frame side rail (not illustrated) present on the side of the lead frame without the bridges is trimmed off, as well.
  • the substrate for mounting the chip may be integral to the lead frame such as a "lead frame die pad,” useful in QFP (quad flat pack) SO, and DIP (dual in-line packages).
  • the substrate would be appropriately insulated from the bonding fingers.
  • the substrate may be coupled to selected bonding fingers to provide electrical ground to the chip.
  • a separate metal, usually copper, heat block combined with lead frame for some high thermal dissipation packages e.g., SIL- Power/HSOP packages, etc.
  • other example packages may use multiple lead frames in combination to couple multiple chips together. These chips are coupled via direct connection to bonding fingers of the lead frames or wire bonded from chip bond pads to pad landings on the lead frame bonding fingers.
  • FIGS. 2 A and 2B illustrate an example embodiment of an MCM device according to the present invention.
  • An MCM device 200 has been packaged.
  • Encapsulation 210 seals the MCM device 200.
  • Edging 205 and edging 215 provide mechanical strength for the lead frame during assembly.
  • Bridges 230a and package leads 220a are shorted together.
  • FIG. 2B after trimming of the lead frame side rail 205 and 215, the bridges 230b and package leads 220b are separated. The bridges 230b are shown in dashed lines.
  • FIG 3 illustrates an example process 300 to assemble an MCM device in a lead frame package having bridges, as outlined earlier.
  • the designer obtains a suitable substrate and lead frame combination for the multiple chips to be assembled 310. Having found the suitable substrate/lead frame combination, the multiple chip devices are attached to the substrate 320. Each chip is wire bonded 330.
  • One or more chips are coupled to one another with bridges 340. They may be directly contacted by the bridges, such as with tape automated bonding (TAB) or be wire bonded from the first chip to the bridge at a first connection point via another wire bond from the bridge to a second connection point at the additional chip, as is shown with wire bonds 50 at Chip 1 via bridges 110 to wire bonds 60 at Chip 2.
  • TAB tape automated bonding
  • the wire bonded and bridged MCM is encapsulated with a suitable molding compound 350.
  • the side rails are trimmed off the encapsulated device in a lead frame to make the singular device 360.

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Wire Bonding (AREA)

Abstract

One or more 'bridges' are integrated into the MCM lead frame to provide a medium for chip-to-chip connections. In an example embodiment, a semiconductor device comprises a first a first lead frame adapted and located for a first IC chip at a first die­securing location and an additional lead frame adapted and located for an additional IC chip at an additional die-securing location. Each of the first and second lead frames have respective sets of bonding fingers adapted to provide electrically-bonding connection to the respective first and second IC chips; at least one lead frame bridge is adapted to couple a bonding pad of the first IC chip with a bonding pad of the additional IC chip.

Description

INNER BRIDGES FOR CHIP-TO-CHIP INTERCONNECTIONS IN A MULTI-CHIP IC PACKAGE
The invention relates to integrated circuit (IC) packaging. More particularly this invention relates to the packaging of multiple IC devices in a multi-chip module package.
The electronics industry continues to rely upon advances in semiconductor technology to realize higher- function devices in more compact areas. For many applications realizing higher-functioning devices requires integrating a large number of electronic devices into a single silicon wafer. As the number of electronic devices per given area of the silicon wafer increases, the manufacturing process becomes more difficult. Many varieties of semiconductor devices have been manufactured with various applications in numerous disciplines. Such silicon-based semiconductor devices often include metal-oxide-semiconductor field-effect transistors (MOSFET), such as p-channel MOS (PMOS), n-channel MOS (NMOS) and complementary MOS (CMOS) transistors, bipolar transistors, BiCMOS transistors. Such MOSFET devices include an insulating material between a conductive gate and silicon- like substrate; therefore, these devices are generally referred to as IGFETs (insulated-gate FET). Each of these semiconductor devices generally includes a semiconductor substrate on which a number of active devices are formed. The particular structure of a given active device can vary between device types. For example, in MOS transistors, an active device generally includes source and drain regions and a gate electrode that modulates current between the source and drain regions. Furthermore, such devices may be digital or analog devices produced in a number of wafer fabrication processes, for example, CMOS, BiCMOS, Bipolar, etc. The substrates may be silicon, gallium arsenide (GaAs) or other substrate suitable for building microelectronic circuits thereon.
A given application for an IC often dictates which fabrication process is used in the ICs construction. For example, devices requiring low power may be rendered in CMOS. Analog devices, such as amplifiers, may be rendered in BiCMOS or bipolar technologies. Radio frequency (RF) components or other high speed devices may require that they be built on GaAs substrates. Modern instruments such as cellphones, laptop computers, audio equipment, etc. are built with a mix of IC technologies. In the continuing effort to reduce the size, weight, power consumption of these devices, there are techniques that involve a mix of multiple integrated circuit devices placed into a single package, a multi-chip module (MCM) package.
Described in. U.S. Patent 5,373, 188 Michii et al entitled, "Packaged Semiconductor Device Including Multiple Semiconductor Chips and Cross-Over Lead' relates to a multi- chip package (MCP) semiconductor device wherein a plurality of semiconductor elements are encapsulated within a single body of resin. Michii et al is provided as background and is incorporated by reference in its entirety.
There exists a need for alternative way to connect multiple chips that overcomes potential deficiencies in direct wire bond connects between selected pads of a given plurality of chips. Furthermore, this alternative reduces complexity and cost in the packaging of multiple chip IC devices.
This invention has been found useful in achieving indirect wire connections from a first chip to additional chips. One or more "bridges" are integrated into the MCM lead frame to provide a medium for chip-to-chip connections. Rather than connect two or more chips together with a long bond wire, the wire length may be reduced. Two shorter wires are used in conjunction with the bridge reduce the likelihood of wire sweeping and deformation.
In an example embodiment according to the present invention, there is a semiconductor device with integrated-circuit (IC) chips. The semiconductor device ■ comprises a first lead frame adapted and located for a first IC chip at a first die-securing location and an additional lead frame adapted and located for an additional IC chip at an additional die-securing location. Each of the first and second lead frames have respective sets of bonding fingers adapted to provide electrically-bonding connection to the respective first and second IC chips; at least one lead frame bridge is adapted to couple a bonding pad of the first IC chip with a bonding pad of the additional IC chip. In an alternative embodiment, the electrically-bonding connection of the respective first and second IC chips includes at least one of the following: a bond wire, direct connection.
In another embodiment according to the present invention, a multi-chip module (MCM) package for packaging a plurality of semiconductor chips, the MCM package comprises a die attach substrate. There is a lead frame fixedly mounted to the die attach substrate. The lead frame defines a plurality of die attach regions on the die attach surface; the lead frame has a plurality of bonding fingers for each of one of the plurality of die attach regions; the lead frame has a plurality of bridges to facilitate connecting of one or more bonding pads of a first die mounted on the die attach surface with one or more bonding pads of additional dice mounted on the die attach surface. An encapsulating material encapsulates the first die and additional dice and lead frame, providing a seal for the MCM package. Additional features of this embodiment include the lead frame being mounted to the die attach substrate with an insulating material or the lead frame being mounted to the die-attach substrate at one or more bonding fingers with conductive material.
In yet another embodiment according to the present invention, there is a lead frame adapted for use in TAB (tape automated bonding) used in connecting together a plurality of IC chips. The lead frame comprises a first side rail having a plurality of bridges attached thereon, the plurality of bridges having a plurality of bond wire attachment locations and a second side rail having a plurality of bond fingers, the bond fingers attached thereon, the bond fingers arranged around openings to accommodate a plurality of IC chips, the bond fingers arranged to surround substantially all of the IC chips, the bond fingers having a least one bond wire attachment location. Another embodiment according to the present invention is directed to a method for packaging a plurality of chips in a MCM package. According to this example, the embodiment involves attaching, e.g., by wire bonding, a plurality of chips to an arrangement including a suitable substrate and lead frame. Using bridges, the chips are electrically coupled to one another, thereby providing a set of wire-bonded and bridged chips over the substrate and lead frame. This arrangement is then encapsulated. In an alternative embodiment, the lead frame is trimmed to implement a singular device.
The above summary of the present invention is not intended to represent each disclosed embodiment, or every aspect, of the present invention. Other aspects and example embodiments are provided in the figures and the detailed description that follows. The present invention has been found to be useful in making interconnections between multiple IC chips packaged together in a multi-chip module package (MCM) in which using direct connections via bond wires is not feasible owing to input/output pin or power pin configurations among the multiple chips. Bridges are integrated into the lead frame to provide alternative connection points to which wires can be bonded. In some MCM (Multi Chip Module) packages, wire interconnection between chips is often required. In conventional configurations, the wires may be connected between a first chip and an additional chip directly by wire bonds. However, for some chip and package arrangements, direct wire bond connections are not feasible owing to input/output pin definitions and package construction. Furthermore, the length of wire bonds used to interconnect two chips may be taken to their wire length limits. This situation can result in over-extended bond wires sagging and being too flexible which, in turn, can result in short circuits, for example, during subsequent package processing. Referring now to the figures, FIG. 1 illustrates an example embodiment of an MCM device 100 according to the present invention. The MCM device 100 includes has two integrated-circuit chips, Chip 1 and Chip 2. Chip 1 and Chip 2 have been attached to regions 140, 150, respectively on a substrate 170. A lead frame 130 provides bonding areas to couple Chip 1 and Chip 2 to the package's pins (not illustrated). Within the lead frame 130, a plurality of bridges 110 is provided. Pins 50 on Chip 1 and pins 60 on Chip 2 are coupled via bridges 110. In turn these bridges 1 10 extend out to package pins 120. During production, these pins 120 and others are often held together by a lead frame side rail 105 to provide sufficient strength in that such a lead frame may be spooled on a reel for use in tape automated bonding, in an example process. The MCM devices are packaged then separated from one another as the lead frame side rail 105 is trimmed off after a multiple number of devices have been encapsulated with a suitable molding compound. Lead frame side rail (not illustrated) present on the side of the lead frame without the bridges is trimmed off, as well. The substrate for mounting the chip may be integral to the lead frame such as a "lead frame die pad," useful in QFP (quad flat pack) SO, and DIP (dual in-line packages). In an example package, the substrate would be appropriately insulated from the bonding fingers. Depending upon the specific application, the substrate may be coupled to selected bonding fingers to provide electrical ground to the chip.
In other example packages, there may a separate metal, usually copper, heat block combined with lead frame for some high thermal dissipation packages (e.g., SIL- Power/HSOP packages, etc.). Furthermore, other example packages may use multiple lead frames in combination to couple multiple chips together. These chips are coupled via direct connection to bonding fingers of the lead frames or wire bonded from chip bond pads to pad landings on the lead frame bonding fingers.
FIGS. 2 A and 2B illustrate an example embodiment of an MCM device according to the present invention. An MCM device 200 has been packaged. Encapsulation 210 seals the MCM device 200. Edging 205 and edging 215 provide mechanical strength for the lead frame during assembly. Bridges 230a and package leads 220a are shorted together. In FIG. 2B, after trimming of the lead frame side rail 205 and 215, the bridges 230b and package leads 220b are separated. The bridges 230b are shown in dashed lines.
FIG 3 illustrates an example process 300 to assemble an MCM device in a lead frame package having bridges, as outlined earlier. The designer obtains a suitable substrate and lead frame combination for the multiple chips to be assembled 310. Having found the suitable substrate/lead frame combination, the multiple chip devices are attached to the substrate 320. Each chip is wire bonded 330. One or more chips are coupled to one another with bridges 340. They may be directly contacted by the bridges, such as with tape automated bonding (TAB) or be wire bonded from the first chip to the bridge at a first connection point via another wire bond from the bridge to a second connection point at the additional chip, as is shown with wire bonds 50 at Chip 1 via bridges 110 to wire bonds 60 at Chip 2. After all the wire bonds have been made, the wire bonded and bridged MCM is encapsulated with a suitable molding compound 350. The side rails are trimmed off the encapsulated device in a lead frame to make the singular device 360. i While the present invention has been described with reference to several particular example embodiments, those skilled in the art will recognize that many changes may be made thereto without departing from the spirit and scope of the present invention, which is set forth in the following claims.

Claims

CLAIMS What is claimed is:
1. A semiconductor device with integrated-circuit (IC) chips, the semiconductor device comprising: a first lead frame adapted and located for a first IC chip at a first die-securing location, an additional lead frame adapted and located for an additional IC chip at an additional die-securing location; and each of the first and second lead frames having respective sets of bonding fingers adapted to provide electrically- bonding connection to the respective first and second IC chips; at least one lead frame bridge adapted to couple a bonding pad of the first IC chip with a bonding pad of the additional IC chip.
2. The semiconductor device as recited in claim 1, wherein the electrically- bonding connection of the respective first and second IC chips is at least one of the following: a bond wire, direct connection.
3. A multi-chip module (MCM) package for packaging a plurality of semiconductor chips, the MCM package comprising: a die attach substrate; a lead frame fixedly mounted to the die attach substrate, the lead frame defining a plurality of die attach regions on the die attach surface, the lead frame having a plurality of bonding fingers for each of one of the plurality of die attach regions, the lead frame having a plurality of bridges to facilitate connecting of one or more bonding pads of a first die mounted on the die attach surface with one or more bonding pads of additional dice mounted on the die attach surface; and an encapsulating material encapsulating the first die and additional dice and lead frame, providing a seal for the MCM package.
4. The MCM package as recited in claim 3, wherein the lead frame is mounted to the die-attach substrate with an insulating material.
5. The MCM package as recited in claim 3, wherein the lead frame is mounted to the die-attach substrate at one or more bonding fingers with conductive material.
6. A lead frame adapted for use in TAB (tape automated bonding) used in connecting together a plurality of IC chips comprising: a first side rail having a plurality of bridges attached thereon, the plurality of bridges having a plurality of bond wire attachment locations; and a second side rail having a plurality of bond fingers, the bond fingers attached thereon, the bond fingers arranged around openings to accommodate a plurality of IC chips, the bond fingers arranged to surround substantially all of the IC chips, the bond fingers having a least one bond wire attachment location.
7. A method for packaging a plurality of chips in a MCM package, the method comprising: obtaining a suitable substrate and lead frame combination; attaching the plurality of chips to the substrate; wire bonding each chip; coupling the plurality of chips to one another with bridges; encapsulating the wire bonded and bridged plurality of chips, substrate, and lead frame; and trimming the lead frame to make singular device.
PCT/IB2005/053595 2004-11-03 2005-11-03 Inner bridges for chip-to-chip interconnections in a multi-chip ic package Ceased WO2006048836A1 (en)

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