[go: up one dir, main page]

WO2006043931A1 - Systeme de carte de circuit a dissipation d'energie thermique amelioree - Google Patents

Systeme de carte de circuit a dissipation d'energie thermique amelioree Download PDF

Info

Publication number
WO2006043931A1
WO2006043931A1 PCT/US2004/033982 US2004033982W WO2006043931A1 WO 2006043931 A1 WO2006043931 A1 WO 2006043931A1 US 2004033982 W US2004033982 W US 2004033982W WO 2006043931 A1 WO2006043931 A1 WO 2006043931A1
Authority
WO
WIPO (PCT)
Prior art keywords
pcb
die
void
heat sink
thermal conductivity
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US2004/033982
Other languages
English (en)
Inventor
James M. Hattis
Neil Petrie
David L. Crouthamel
Jason P. Goodelle
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Agere Systems LLC
Original Assignee
Agere Systems LLC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Agere Systems LLC filed Critical Agere Systems LLC
Priority to PCT/US2004/033982 priority Critical patent/WO2006043931A1/fr
Priority to JP2007536667A priority patent/JP5025481B2/ja
Priority to KR1020077010924A priority patent/KR100952850B1/ko
Priority to US11/403,492 priority patent/US7817434B2/en
Publication of WO2006043931A1 publication Critical patent/WO2006043931A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K7/00—Constructional details common to different types of electric apparatus
    • H05K7/20—Modifications to facilitate cooling, ventilating, or heating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H01L23/3677—Wire-like or pin-like cooling fins or heat sinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0201—Thermal arrangements, e.g. for cooling, heating or preventing overheating
    • H05K1/0203—Cooling of mounted components
    • H05K1/0204—Cooling of mounted components using means for thermal conduction connection in the thickness direction of the substrate

Definitions

  • the present invention relates to printed circuit boards (PCBs), and more particularly, to dissipating thermal energy generated by an integrated circuit (IC) mounted on a PCB.
  • PCBs printed circuit boards
  • IC integrated circuit
  • Typical IC packages usually include an enclosed and/or encapsulated plastic housing with an internal lead frame, bond wires and die, as well as external electrical leads for electrically connecting the die to the outside world.
  • IC packages that house higher thermal dissipation die have an additional integral heat sink formed within the package that is connected to the IC substrate.
  • the heat sink typically comprises a metal layer.
  • a die is usually mounted on this metal layer with its electrical contact pads face up and bond wires connecting the electrical contact pads of the die to the internal lead frame of the IC package.
  • the lead frame provides a mechanically rigid electrical path from the die and the bond wires to the external electrical leads of the IC package.
  • the lead frame is usually molded partially within the plastic housing in order to bridge the electrical connection between the internal lead frame and the external leads.
  • the electrical leads make the electrical connection from the package to the PCB on which the package is mounted.
  • a heat spreader device on the PCB located directly underneath the IC package is thermally connected to the heat sink of the IC package and then to a ground plane within the PCB layers.
  • the heat spreader device dissipates heat generated by the IC into the PCB ground plane itself. Heat generated by the IC is also convectively moved away from the IC package out to the surrounding air.
  • the IC package is eliminated and the die is mounted directly to the PCB in an inverted position such that the electrical contact pads on the die face downward toward the confronting circuit traces on the PCB, and are electrically connected by electrical interconnects (e.g., solder bumps) that connect the contact pads of the die to the circuit traces on the PCB.
  • electrical interconnects e.g., solder bumps
  • the PCB used in a direct-chip-attach configuration is usually a physically flexible PCB and is known as a flex PCB or flex circuit. Because of its flexibility, the flex PCB can be shaped into a small physical area, while still maintaining the electrical contact between the PCB and the die.
  • These types of circuits are often used in situations where very little space is available to mount the PCB, such as on a read/write head that reads data from and writes data to a hard drive magnetic recording media within a hard disc drive (HDD).
  • HDD hard disc drive
  • These read/write heads typically sit on a stainless steel armature with the flex PCB mounted upon it.
  • the electrical contacts of the flex PCB typically connect the read/write heads to electrical contacts of a read/write preamplifier IC. This entire assembly is then floated aerodynamically above the magnetic recording media.
  • FIG. 6 illustrates a perspective view of a typical direct-chip-attach assembly 11, which includes a flex PCB comprising various layers 12 and an IC die 13 mounted on the flex PCB 12.
  • the IC die 13 is mounted to the flex PCB 12 in a confronting position such that electrical contact pads (not shown) on the die 13 are disposed to be easily connected by electrical interconnects (e.g., solder bumps) 19 to the circuit traces (not shown) on the flex PCB 12.
  • electrical interconnects e.g., solder bumps
  • the flex PCB 12 may include a heat sink material 14 that is in contact with the side of the PCB 12 that is opposite the die 13, a layer 15 of adhesive and thermally insulating dielectric material (e.g., polyimid) disposed on the heat sink material 14, a metal layer 16 disposed on layer 15, and a layer 17 of thermally insulating dielectric material (e.g., polyimid) disposed on the metal layer 16.
  • the aforementioned circuit traces are formed by portions of the metal layer 16 of the flex PCB 12, which is typically made of copper.
  • the heat sink material 14 functions as the heat dissipator and the thermal path is in the direction from the die 13 to the heat sink material 14, as indicated by the arrows 23 and 24 directed from the die 13 into the heat sink material 14.
  • flex PCBs include a stabilizing device, such as an aluminum stiff ener (not shown) that is located between the heat sink material 14 and the layer of polyimid and adhesive 15.
  • the stiffener provides mechanical stability to the flex PCB.
  • the heat sink material 14 need not be part of the PCB 12, but may instead be a separate device upon which the PCB 12 is placed. If a stiffener is used, it provides a path of heat dissipation into the heat sink material and ultimately into the armature and housing of the disc drive.
  • the electrical interconnects 19 that connect the contact pads of the die 13 with the circuit traces formed in the metal layer 16 are solder or lead-free bumps that are placed on the electrical contact pads (not shown) located on the bottom face of the die 13 and heated and then placed in contact with the circuit traces on the flex PCB 12. When the bumps cool and harden, they form a rigid electrical connection between the pads on the bottom face of the die 13 and the circuit traces formed in the metal layer 16 of the flex PCB 12.
  • the spacing between the die 13 and the flex PCB 12 typically is filled with an underfill material 21 that provides mechanical stability. This prevents undue mechanical stresses from being exerted upon the die 13 and the interconnects that could cause the electrical connections to fail.
  • the underfill material 21 is usually applied after the pads of the die 13 have been interconnected with the circuit traces on the flex PCB 12.
  • the underfill material 21 is typically applied using capillary flow.
  • the underfill material 21 is then heated in order to cure the material into a solid, physical state.
  • the underfill material 21 that is currently used for this purpose has poor thermal conductivity and is typically Hysol®FP4549, manufactured by the Henkel Loctite Corporation of Dusseldorf, Germany. This particular underfill material is a high purity, low stress, liquid epoxy designed for enahanced adhesion to integrated circuit passivation materials.
  • the flex PCB assembly When a flex PCB assembly such as that shown in Fig. 1 is used on a read/write head of a disc drive, the flex PCB assembly normally uses large amounts of current and/or voltage to enable the read and write operations to be performed. These types of signals typically exhibit very fast rise times, some less than 200 picoseconds (ps), and large slew rates in excess of 700 miliamperes (mA) per nanosecond (ns), which produce extremely large instantaneous currents and/or voltages. These large instantaneous currents and/or voltages produce a large amount of thermal energy that needs to be dissipated.
  • flex PCB assemblies When a flex PCB assembly is used in a very physically small environment, such as on a read/write head of a disk drive, for example, where space and cost constraints are at a premium, typical approaches for reducing thermal resistance are inadequate and/or impractical.
  • flex PCB assemblies typically use a single-layer (i.e., the metal layer 16 having traces formed in it).
  • simple multi-layer plated through-hole technology can be used to provide thermally conductive heat paths down through the PCB in order to dissipate thermal heat generated.
  • multi-layer PCBs usually cost considerably more than single-layer PCBs.
  • multi-layer conductor PCB may be cost prohibitive in some cases. Also, due to the aerodynamics of the head armature in a disc drive application, multi-layer PCBs located on the armature of a disc drive are usually unsuitable because the additional mass on the armature can result in slower read and write speeds.
  • the present invention provides a method and an apparatus for improving heat dissipation from a die to a printed circuit board (PCB) assembly.
  • the apparatus comprises a PCB assembly having improved thermal conductivity, and the method is a method for improving the thermal conductivity of the PCB.
  • the PCB assembly includes a PCB having a void formed in it where a portion of the PCB has been removed, an integrated circuit (IC) die mounted to a side of the PCB and electrically interconnected to the PCB, and a material or device disposed in the void that has a higher thermal conductivity than the thermal conductivity of a removed portion of the PCB.
  • the PCB includes at least one circuit trace.
  • the die is interconnected to the PCB by at least one electrical interconnect that interconnects an electrical contact pad on the die with a circuit trace of the PCB.
  • PCB assembly includes a PCB having a void formed in it where a portion of the PCB has been removed, an IC die mounted to the PCB in a direct-chip-attach configuration and electrically interconnected to the PCB, and a material or device attached or in close proximity to the die adjacent to the void or protruding into the void.
  • the material or device attached or in close proximity to the die has a thermal conductivity that is higher than the thermal conductivity of the removed portion of the circuit board.
  • the PCB includes at least one circuit trace.
  • the die is interconnected to the PCB by at least one electrical interconnect that interconnects an electrical contact pad on the die with a circuit trace of the PCB.
  • PCB assembly comprises removing a portion of the PCB to form a void in the PCB, disposing a device or material in the void that has a higher thermal conductivity than the thermal conductivity of the removed portion of the circuit board, and mounting the die to a side of the PCB in a direct-chip-attach configuration.
  • Fig. 1 illustrates a cross-sectional view of the PCB assembly of the present invention in accordance with an embodiment, wherein a portion of the PCB has been removed and the removed portion has been filled with a material that has a higher thermal conductivity than the removed portion of the PCB.
  • Fig. 2 illustrates a cross-sectional view of the PCB assembly of the present invention in accordance with another embodiment, wherein a portion of the PCB has been removed and a portion of the heat sink material of the PCB has been raised and/or inserted into the void such that it is closer to the lower surface of the die.
  • Fig. 2 illustrates a cross-sectional view of the PCB assembly of the present invention in accordance with another embodiment, wherein a portion of the PCB has been removed and a portion of the heat sink material of the PCB has been raised and/or inserted into the void such that it is closer to the lower surface of the die.
  • FIG. 3 illustrates a cross-sectional view of the PCB assembly of the present invention in accordance with another embodiment, wherein a portion of the PCB has been removed to form a void in the PCB and a material of high thermal conductivity (e.g., a metal rivet) has been placed in and/or protrudes from the void, thereby decreasing the physical distance between the die and the heat sink material and increasing the thermal conductivity of the thermal path.
  • a material of high thermal conductivity e.g., a metal rivet
  • FIG. 4 illustrates a cross-sectional view of the PCB assembly of the present invention in accordance with another embodiment, wherein a portion of the PCB has been removed to form a void in the PCB and a material of high thermal conductivity (e.g., copper) has been placed on the bottom surface of the die to further increase the thermal conductivity of the thermal path.
  • a material of high thermal conductivity e.g., copper
  • Fig. 5 illustrates a flow chart of the method of the present invention in accordance with the preferred embodiment.
  • Fig. 6 illustrates a cross-sectional view of a typical direct-chip-attach configuration comprising a PCB and an IC die mounted on the PCB.
  • a PCB assembly includes an
  • IC die mounted on a PCB The IC die may be mounted in a direct-chip-attach configuration. Alternatively, the IC die may be encapsulated in an IC package and the IC package is mounted to the PCB.
  • a PCB includes any substrate having a dielectric material that is both electrically and thermally insulating. Therefore, a PCB 5 as that term is used herein, includes, but is not limited to, the aforementioned flex circuits, which are single-layer printed circuit boards. The present invention also is not limited with respect to the type of material of which the PCB is made.
  • polyimid and fiber resin are materials that are most commonly used to make PCBs
  • other materials such as Teflon®, for example, which is used to make rigid PCBs, may also be used as the PCB material.
  • Teflon® for example, which is used to make rigid PCBs
  • the present invention also, however, applies to multi-layer PCBs. For ease of discussion and illustration, the present invention will be described with reference to a PCB that is a flex circuit comprising particular materials.
  • Fig. 1 illustrates a cross-sectional view of the PCB assembly 20 of the present invention in accordance with an embodiment.
  • the PCB assembly 20 includes a PCB 30 and an IC die 40 mounted on the PCB 30 in a direct-chip-attach configuration, i.e., a flip-chip configuration.
  • a direct-chip-attach configuration is intended to mean that the IC package is eliminated and the IC die is mounted directly to the PCB in a confronting relationship such that the electrical contact pads on the die face downward toward the PCB face and are electrically interconnected with circuit traces on the PCB by electrical interconnects (e.g., solder bumps, lead-free bumps, vias, etc.).
  • electrical interconnects e.g., solder bumps, lead-free bumps, vias, etc.
  • the PCB 30 is a flex circuit, although, as stated above, the invention is not limited to such a PCB. The invention also is not limited to direct-chip-attach configurations, but also applies to IC packages mounted on PCBs, such as single-layer PCBs, for example.
  • the flex PCB 30 of the present invention typically includes a heat sink material 31, a first layer 32 of electrically and thermally insulating dielectric material (e.g., polyimid) disposed on the heat sink material 31, a layer of metal 33 having one or more circuit traces formed therein disposed on the adhesive and polyimid layer 32, and a layer 34 of electrically and thermally insulating material (e.g., polyimid) disposed on top of the layer of metal 33.
  • the heat sink material 31 functions as the heat dissipator and the thermal path is in the direction from the die 40 to the heat sink material 31 5 as indicated by the arrows 43 and 44 directed from the die 41 into the heat sink material 31.
  • the metal layer 33 typically is a layer of copper. As described above with reference to Fig. 1, the metal layer 33 has the circuit traces of the flex circuit 30 formed therein. A portion of the layer of electrically and thermally insulating dielectric material 34 is removed to enable the circuit traces to be formed in the metal layer 33.
  • the die 40 is placed in electrical contact with the metal layer 33 of the PCB 30 via electrical interconnects 36, such as, for example, solder bumps, which are typically located about the periphery of the die 40 in direct-chip-attach configurations.
  • the electrical interconnects 36 interconnect electrical contact pads on the die 40 with circuit traces formed in the metal layer 33.
  • the heat sink material 31 may be part of the PCB assembly 20 or it may be separate from the PCB assembly 20.
  • the heat sink material 31 is typically metal and may be, for example, aluminum or stainless steel.
  • a stabilizing device such as aluminum, is commonly used in flex PCB assemblies to provide mechanical stability, and may be located between the layer of adhesive and electrically and thermally insulating dielectric material 32 and the heat sink material 31.
  • a portion of the PCB 30 has been removed to create a void 50 in the PCB 30 between the lower surface 41 of the die 40 and the upper surface 38 of the heat sink material 31.
  • the void 50 is formed by removing portions of all of the layers 32 - 34 down to the upper surface 38 of the heat sink material 31. From a comparison of Figs. 1 and 6, it can be seen that the void 50 shown in Fig. 1 is not present in Fig. 6.
  • the void 50 preferably is formed at a location such that it will be located directly underneath the die and centered on the die face area. In accordance with the embodiment shown in Fig.
  • the void 50 is filled with an underfill material 60 that exhibits a higher relative thermal conductivity than the removed portion of the PCB 30.
  • the underfill material 60 is represented in Fig. 1 by the areas filled with black dots.
  • the underfill material normally used to provide mechanical stability (reference numeral 21 in Fig. 6) is a very poor thermal conductor and typically has about the same thermal conductivity as that of the PCB substrate material.
  • a typical range for the thermal conductivity for the underfill material 21 used for the flip-chip assembly shown in Figs. 6 is between approximately 0.3 Watts per meter-Kelvin (W/m-K) and 0.9 W/m- K.
  • the thermal conductivity of the underfill material 60 used to fill the void 50 has a minimum value of approximately 3.0 W/m-K (i.e., a minimum of approximately 10 times the thermal conductivity of the removed portion of the PCB dielectric material). Therefore, the thermal conductivity of the underfill material 60 preferably is equal to or greater than approximately 3.0 W/m-K.
  • the underfill material may be, for example, Namics 8449-3, which is manufactured by the Namics Corporation of Nigorikawa, Niigata City, Japan.
  • This particular underfill material is a liquid epoxy that includes small-grain filler material that is thermally conductive.
  • the thermally conductive small-grain filler material is typically silver or blond nitride. It should be noted that any filler material that has suitable physical properties, such as adhesion and thermal conductivity, for example, may be suitable for this purpose.
  • the only additional processing step that may be required is forming the void 50, which, if designed into the flex PCB 30 when it is initially physically laid out, adds no additional cost to the process.
  • the PCB 30 typically requires other openings, or voids, to be formed in it for the purpose of mechanically mounting the PCB (e.g., to a read/write head armature, or to heat sink material, or to some other device).
  • the voided out area in the PCB can be filled with materials other than underfill material to improve the thermal conductivity of the path from the die to the heat sink material.
  • One of the primary goals of the present invention is to reduce the overall thermal resistance from the die to the PCB base (e.g., the heat sink material) by creating a low thermal resistance path (the void filled with underfill) in parallel with the surrounding high thermal resistance path (i.e., the PCB dielectric material layers). This is similar to placing a low value resistor in parallel with a high value resistor so that the value of the total overall effective resistance is closer to the low value resistor.
  • the PCB 80 is a flex circuit of the type shown in Fig. 1.
  • the flex circuit 80 includes a heat sink material 81, a layer 82 of adhesive and electrically and thermally insulating dielectric material (e.g., polyimid) disposed on the heat sink material 81, a metal layer 83 disposed on top of layer 82, and a layer 84 of electrically and thermally insulating dielectric material (e.g., polyimid) disposed on top of the metal layer 83.
  • the metal layer 83 has one or more circuit traces formed in it.
  • the die 90 is placed in electrical contact with circuit traces of the metal layer 83 of the PCB 80 via electrical interconnects 86 (e.g., solder bumps, lead-free bumps, vias, etc.), which interconnect electrical contact pads on the die to circuit traces of the PCB 80.
  • the heat sink material 81 may be part of the PCB assembly 70 or it may be separate from the PCB assembly 70.
  • a stiffener made of higher electrically and thermally conductive material is commonly used in flex PCB assemblies to provide mechanical stability, and may be located between the layer of adhesive and electrically and thermally insulating dielectric material 82 and the heat sink material 81. The materials used to make the PCB assembly 70 shown in Fig.
  • the void 100 preferably is formed by removing portions of the layers 82 - 84 of the PCB 80 down to the upper surface 88 of the heat sink material 81.
  • the heat sink material 81 may be, for example, aluminum or stainless steel.
  • the void 100 is then filled with either an underfill material 110 that preferably has a higher relative thermal conductivity than the removed portion of the PCB 80, such as Namics 8449-3 underfill material, or with a metal that has a higher thermal conductivity than the removed portion of the PCB 80.
  • the void 100 may be filled with any material that has a higher thermal conductivity than that of the removed portion of the PCB, including dielectric materials.
  • the upper surface 88 of the heat sink material 81 may be raised to reduce the distance between the upper surface 88 of the heat sink material and the lower surface 91 of the die 90. This may be accomplished by deforming the heat sink material 81 in some way, such as by a stamping process, for example.
  • a portion of the upper surface 88 of the heat sink material 81 protrudes into the void 100 and is closer to the die 90 than are other portions of the heat sink material 81.
  • the underfill material 110 preferably has a higher relative thermal conductivity than that of the removed portion of the PCB material 80, this is not necessary for this embodiment. Because the distance between the lower surface 91 of the die 90 and the upper surface 88 of the heat sink material 81 is reduced, it is not necessary that the underfill material 110 have a higher relative thermal conductivity than that of the removed portion of the PCB 80. Even if standard underfill material is used in this embodiment (e.g., Hysol®FP5449), the reduced distance between surfaces 88 and 81 provides improved heat dissipation.
  • Fig. 3 illustrates a cross-sectional plan view of the PCB assembly 120 of the present invention in accordance with another embodiment.
  • the PCB assembly 120 includes a PCB 130 and a die 140 mounted on the PCB 130 in a direct-chip- attach arrangement, i.e., a flip-chip configuration.
  • the PCB 130 is a flex circuit of the type shown in Figs. 1 and 2.
  • the flex circuit typically includes a heat sink material 131, a first layer of adhesive and electrically and thermally insulating dielectric material (e.g., polyimid) 132 disposed on the heat sink material 131, a layer of metal 133 disposed on top of layer 132, and a layer of electrically and thermally insulating dielectric material (e.g., polyimide) 134 disposed on top of the metal layer 132.
  • the flip-chip die 140 is placed in electrical contact with circuit traces formed in the metal layer 133 of the PCB 130 via electrical interconnects 136 (e.g., solder bumps, lead-free bumps, vias, etc.), which are typically located about the periphery of the die 140.
  • the conductive interconnects 136 interconnect electrical contact pads on the die 140 with the circuit traces formed within the metal layer 133 of the PCB 130.
  • the materials used to make the PCB assembly 120 shown in Fig. 3 may be identical to the materials used to make the PCB assemblies 20 and 70 shown in Figs. 1 and 2.
  • a portion of the PCB 130 has been removed to create a void 150 in the PCB 130 between the lower surface 141 of the die 140 and the upper surface 138 of the heat sink material 131.
  • the void 150 preferably is formed by removing portions of the layers 132 - 134 of the PCB 130 down to the upper surface 138 of the heat sink material 131.
  • the void 150 preferably is then filled with an underfill material 160 that has a higher relative thermal conductivity than that of the removed portion of the PCB 130.
  • the aforementioned Namics 8449-3 underfill material may be suitable for this purpose.
  • the upper surface 138 of the heat sink material 131 has a device 170 made of a material of relatively high thermal conductivity, such as, for example, a metal rivet or slug inserted into it that protrudes into the void 150 and reduces the length of the thermal path between the heat sink material 131 and the die 140. Because the extension or protrusion 170 reduces the length of the thermal path, it improves the thermal conductivity of the assembly 120, which improves the overall effectiveness of the heat sink.
  • a device 170 made of a material of relatively high thermal conductivity, such as, for example, a metal rivet or slug inserted into it that protrudes into the void 150 and reduces the length of the thermal path between the heat sink material 131 and the die 140. Because the extension or protrusion 170 reduces the length of the thermal path, it improves the thermal conductivity of the assembly 120, which improves the overall effectiveness of the heat sink.
  • filling at least part of the void 150 with a device that has a relatively high thermal conductivity increases the thermal conductivity of the thermal path between the die 140 and the heat sink material 131.
  • a device that has a relatively high thermal conductivity i.e., higher than the thermal conductivity of the removed portion of the PCB
  • a device such as a metal rivet or metal slug is suitable for this purpose because metal has an absolute high thermal conductivity. Therefore, using such a device would greatly increase the thermal conductivity of the thermal path between the die 140 and the heat sink material 131, which may be, for example, aluminum or stainless steel.
  • a device comprising a dielectric material may also be suitable for placement in the void 150 provided the device has a higher thermal conductivity that that of the removed portion of the PCB 130.
  • the underfill material 160 it is not necessary that the underfill material 160 have a higher thermal conductivity (e.g., Namics 8449-3) than that of the removed portion of the PCB 130. Even if standard underfill material is used (e.g., Hysol®FP5449), the reduced path length provides a more effective heat sink.
  • the amount of the improved effectiveness of thermal energy dissipation is dependant upon various factors.
  • the amount of improved effectiveness depends on the ratio of the thermal conductivity of the material or device disposed in and adjacent to the void to the relative thermal conductivity of the PCB material surrounding the void. As this ratio increases, the amount of improved effectiveness also increases. This is true regardless of whether the higher thermal conductivity material is underfill material, as described above with reference to Fig. 1, or some other material or device, such as a portion of the heat sink material shaped in a particular manner, or some other device, such as a metal rivet, as described above with reference to Figs. 2 and 3.
  • the amount of improved effectiveness of dissipating thermal energy also depends on the ratio of the area (or volume) of the void filled with a material or device of higher thermal conductivity to the area (or volume) of the PCB dielectric material (e.g., polyimid) located underneath the die. As this ratio increases, the amount of improved effectiveness also increases This is true regardless of whether the higher thermal conductivity material is underfill material, as described above with reference to Fig. 1, or some other material or device, such as a portion of the heat sink material shaped in a particular manner, or some other device, such as, for example, a metal rivet or slug, as described above with reference to Figs. 2 and 3.
  • the higher thermal conductivity material is underfill material, as described above with reference to Fig. 1, or some other material or device, such as a portion of the heat sink material shaped in a particular manner, or some other device, such as, for example, a metal rivet or slug, as described above with reference to Figs. 2 and 3.
  • the void may have high thermal conductivity underfill as well as a portion of the heat sink material or a metal rivet or device of some kind disposed in the void.
  • the amount of improved effectiveness of dissipating thermal energy increases with the increase of the ratio of the area (or volume) of the heat sink material or other material or device disposed in the void to the area (or volume) of the underfill material disposed in or adjacent to the void.
  • the extent to which the invention improves the effectiveness of dissipating thermal energy also depends on the relationship of the location of the void relative to the "hot spots" of the die. In other words, the die does not generate thermal energy uniformly across its surface area.
  • Fig. 4 illustrates a cross-sectional view of the PCB assembly 170 of the present invention in accordance with another embodiment.
  • the PCB assembly 170 includes a PCB 180 and an IC die 190 mounted on the PCB 180 in a direct-chip- attach arrangement, i.e., a flip-chip configuration.
  • the PCB 180 is a flex circuit of the type shown in Figs. 1, 2 and 3.
  • the flex circuit typically includes a heat sink material 181, a first layer of adhesive and electrically and thermally insulating dielectric material (e.g., polyimid) 182 disposed on the heat sink material 181, a layer of metal 183 disposed on top of layer 182, and a layer of electrically and thermally insulating dielectric material (e.g., polyimide) 184 disposed on top of the metal layer 182.
  • the die 190 is placed in electrical contact with circuit traces formed in the metal layer 183 of the PCB 180 via electrical interconnects 186 (e.g., solder bumps, lead-free bumps, vias, etc), which are typically located about the periphery of the die 190.
  • the interconnects 186 interconnect contact pads on the die 190 with the trace circuits formed in or on the PCB 180.
  • the materials used to create the layers of the PCB assembly 170 shown in Fig. 4 may be identical to the materials used to create the layers of the PCB assemblies 20, 70 and 120 shown in Figs. 1, 2 and 3, respectively. [0045] Like the embodiments represented by Figs.
  • a portion of the PCB 180 has been removed to create a void 200 in the PCB 180 between the lower surface 191 of the die 190 and the upper surface 188 of the heat sink material 181.
  • the void 200 preferably is formed by removing portions of the layers 182 - 184 of the PCB 180 down to the upper surface 188 of the heat sink material 181.
  • the void 200 is then filled with an underfill material 210 that preferably has a higher thermal conductivity than that of the removed portion of the PCB 180.
  • the upper surface 188 of the heat sink material 181 has a device 220 inserted into it, such as, for example, a metal device (e.g., a metal rivet or slug) that preferably at least partially protrudes into the void 200.
  • the lower surface 191 of the die 190 has a material or device 240 of relatively high thermal conductivity disposed on it or in close proximity to it.
  • the material or device 240 has a higher thermal conductivity than that of the removed portion of the PCB 180.
  • the material or device 240 is made of metal.
  • the material or device 240 may be, for example, a metal plate, such as a metal plate of copper.
  • the material or device 240 may be disposed on or adjacent to the lower surface 191 of the die 190 and may be formed by any suitable process, such as, for example, plating, deposition, sputtering, etc.
  • the material or device 240 may be attached to the upper surface of the device 220 by, for example, solder 250.
  • solder 250 It can be seen from Fig. 4 that a portion of the void 200 between the lower surface 191 of the die 190 and the upper surface 188 of the heat sink material 181 is completely filled with material of higher thermal conductivity than the removed portion of the PCB 180.
  • all of the devices or materials 220, 240 and 250 may be partially or wholly metal.
  • Fig. 5 is a flow chart of the method of the present invention in accordance with the preferred embodiment for improving the effectiveness of the heat sink in a PCB assembly. As described above, a portion of the PCB is removed to provide a void in the PCB, as indicated by block 271.
  • the thermal conductivity of the thermal path between the die and the heat sink material is improved by reducing the length of the thermal path and/or by increasing the thermal conductivity of the material disposed in the void and/or between the heat sink material and the lower surface of the die, as indicated by block 272.
  • the present invention is not limited with respect to the type of material or device that is placed in the void or that is attached to the bottom surface of the die.
  • the present invention is not limited to any particular type of PCB.
  • the present invention applies to single-layer PCBs as well as multi-layer PCBs.
  • the heat sink material may be in other locations.
  • the heat sink material may be a ground plane located between the outermost layers of the PCB.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Thermal Sciences (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Structure Of Printed Boards (AREA)
  • Wire Bonding (AREA)

Abstract

L'invention concerne un procédé et un dispositif permettant d'améliorer la conductivité thermique d'une carte de circuit (PCB), comprenant un circuit intégré (IC) monté sur une PCB. Un vide est formé dans le la PCB et un dispositif ou un matériau est placé dans le vide, qui présente une conductivité thermique supérieure à la conductivité thermique de la partie enlevée de la carte de circuit. L'efficacité de la dissipation de l'énergie thermique est améliorée par placement, dans le vide, d'un matériau présentant une conductivité thermique relativement élevée.
PCT/US2004/033982 2004-10-14 2004-10-14 Systeme de carte de circuit a dissipation d'energie thermique amelioree Ceased WO2006043931A1 (fr)

Priority Applications (4)

Application Number Priority Date Filing Date Title
PCT/US2004/033982 WO2006043931A1 (fr) 2004-10-14 2004-10-14 Systeme de carte de circuit a dissipation d'energie thermique amelioree
JP2007536667A JP5025481B2 (ja) 2004-10-14 2004-10-14 熱エネルギー放散を改善したプリント回路板組立体
KR1020077010924A KR100952850B1 (ko) 2004-10-14 2004-10-14 개선된 열 에너지 소산을 가진 인쇄 회로 기판 어셈블리
US11/403,492 US7817434B2 (en) 2004-10-14 2006-04-13 Method and apparatus for improving thermal energy dissipation in a direct-chip-attach coupling configuration of an integrated circuit and a circuit board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/US2004/033982 WO2006043931A1 (fr) 2004-10-14 2004-10-14 Systeme de carte de circuit a dissipation d'energie thermique amelioree

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US11/403,492 Continuation-In-Part US7817434B2 (en) 2004-10-14 2006-04-13 Method and apparatus for improving thermal energy dissipation in a direct-chip-attach coupling configuration of an integrated circuit and a circuit board

Publications (1)

Publication Number Publication Date
WO2006043931A1 true WO2006043931A1 (fr) 2006-04-27

Family

ID=34959034

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2004/033982 Ceased WO2006043931A1 (fr) 2004-10-14 2004-10-14 Systeme de carte de circuit a dissipation d'energie thermique amelioree

Country Status (3)

Country Link
JP (1) JP5025481B2 (fr)
KR (1) KR100952850B1 (fr)
WO (1) WO2006043931A1 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7982307B2 (en) 2006-11-22 2011-07-19 Agere Systems Inc. Integrated circuit chip assembly having array of thermally conductive features arranged in aperture of circuit substrate

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8917510B2 (en) * 2011-01-14 2014-12-23 International Business Machines Corporation Reversibly adhesive thermal interface material
JP7522695B2 (ja) * 2021-04-15 2024-07-25 日立Astemo株式会社 電子装置
WO2024075168A1 (fr) * 2022-10-03 2024-04-11 日本電信電話株式会社 Émetteur optique
WO2024075171A1 (fr) * 2022-10-03 2024-04-11 日本電信電話株式会社 Émetteur optique
WO2024075172A1 (fr) * 2022-10-03 2024-04-11 日本電信電話株式会社 Émetteur optique

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0080156A1 (fr) * 1981-11-24 1983-06-01 Siemens Aktiengesellschaft Moyens mis en oeuvre pour le refroidissement de modules à haute dissipation
US5262922A (en) * 1990-07-26 1993-11-16 Fujitsu, Limited Heat radiation structure for semiconductor device
US5812375A (en) * 1996-05-06 1998-09-22 Cummins Engine Company, Inc. Electronic assembly for selective heat sinking and two-sided component attachment
US6337228B1 (en) * 1999-05-12 2002-01-08 Amkor Technology, Inc. Low-cost printed circuit board with integral heat sink for semiconductor package

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6432657A (en) * 1987-07-29 1989-02-02 Hitachi Chemical Co Ltd High heat-dissipating semiconductor element loader
JPH01260839A (ja) * 1988-04-11 1989-10-18 Fujitsu Ltd 集積回路の実装構造
US5172301A (en) * 1991-10-08 1992-12-15 Lsi Logic Corporation Heatsink for board-mounted semiconductor devices and semiconductor device assembly employing same
JPH0669281A (ja) * 1992-08-18 1994-03-11 Fujitsu Ltd ベアチップの実装構造
JP3271631B2 (ja) * 1993-02-18 2002-04-02 太平洋セメント株式会社 半導体装置実装用基板
JP3259420B2 (ja) * 1993-03-05 2002-02-25 ソニー株式会社 フリップチップの接続構造
JPH07106470A (ja) * 1993-09-29 1995-04-21 Toshiba Corp 半導体装置
JP3353501B2 (ja) * 1994-11-09 2002-12-03 ソニー株式会社 半導体装置及び半導体装置の製造方法
JPH1126633A (ja) * 1997-07-03 1999-01-29 Nec Corp 半導体素子およびその実装構造
JPH1167958A (ja) * 1997-08-19 1999-03-09 Sumitomo Kinzoku Electro Device:Kk 高放熱タイプのフィリップチップ用パッケージ構造
JP2000164992A (ja) * 1998-11-26 2000-06-16 Kyocera Corp 配線基板およびその製造方法
JP2000164774A (ja) * 1998-11-26 2000-06-16 Sony Corp 半導体装置及びその製造方法
JP2001352021A (ja) * 2000-06-07 2001-12-21 Sony Corp 半導体パッケージ、半導体パッケージの実装構造及び半導体パッケージの製造方法
JP3827978B2 (ja) * 2001-08-28 2006-09-27 株式会社ルネサステクノロジ 半導体装置の製造方法
JP2003347460A (ja) * 2002-05-28 2003-12-05 Kyocera Corp 電子装置

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0080156A1 (fr) * 1981-11-24 1983-06-01 Siemens Aktiengesellschaft Moyens mis en oeuvre pour le refroidissement de modules à haute dissipation
US5262922A (en) * 1990-07-26 1993-11-16 Fujitsu, Limited Heat radiation structure for semiconductor device
US5812375A (en) * 1996-05-06 1998-09-22 Cummins Engine Company, Inc. Electronic assembly for selective heat sinking and two-sided component attachment
US6337228B1 (en) * 1999-05-12 2002-01-08 Amkor Technology, Inc. Low-cost printed circuit board with integral heat sink for semiconductor package

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7982307B2 (en) 2006-11-22 2011-07-19 Agere Systems Inc. Integrated circuit chip assembly having array of thermally conductive features arranged in aperture of circuit substrate

Also Published As

Publication number Publication date
KR20070058016A (ko) 2007-06-07
JP5025481B2 (ja) 2012-09-12
JP2008517459A (ja) 2008-05-22
KR100952850B1 (ko) 2010-04-13

Similar Documents

Publication Publication Date Title
US5590462A (en) Process for dissipating heat from a semiconductor package
KR100310398B1 (ko) 열전도체를구비한패드어레이반도체소자및그제조방법
JP4805901B2 (ja) 半導体パッケージ
US5471366A (en) Multi-chip module having an improved heat dissipation efficiency
US6724631B2 (en) Power converter package with enhanced thermal management
US6396136B2 (en) Ball grid package with multiple power/ground planes
JPH09153565A (ja) ヒートシンク付きボールグリッドアレーパッケージ
WO1996012299A1 (fr) Boitier pour circuit integre
JPH08222671A (ja) 回路モジュールの冷却装置
US20130068509A1 (en) Method and apparatus for connecting inlaid chip into printed circuit board
CA2075593A1 (fr) Module a puce de semiconducteur et sa methode de fabrication
US6552907B1 (en) BGA heat ball plate spreader, BGA to PCB plate interface
JP2845227B2 (ja) マルチチップモジュールの実装構造
KR100952850B1 (ko) 개선된 열 에너지 소산을 가진 인쇄 회로 기판 어셈블리
JPH0982857A (ja) マルチチップパッケージ構造
US7817434B2 (en) Method and apparatus for improving thermal energy dissipation in a direct-chip-attach coupling configuration of an integrated circuit and a circuit board
US6963129B1 (en) Multi-chip package having a contiguous heat spreader assembly
KR101212473B1 (ko) 집적 회로 및 회로 기판의 직접 칩 실장 결합 구성에서의 열에너지 분산을 개선하기 위한 방법 및 장치
JP2006135202A (ja) 電子機器の放熱構造
US7208827B2 (en) Encasing arrangement for a semiconductor component
EP4648103A1 (fr) Boîtier de cadre de conducteur à dissipation de chaleur améliorée
US20070246822A1 (en) Hard disk drive preamp heat dissipation methods
JPH10294399A (ja) Ｂｇａパッケージの実装構造
JPS6286890A (ja) 金属ベ−ス基板
JPH06152080A (ja) 配線基板

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 11403492

Country of ref document: US

AK Designated states

Kind code of ref document: A1

Designated state(s): AE AG AL AM AT AU AZ BA BB BG BR BW BY BZ CA CH CN CO CR CU CZ DE DK DM DZ EC EE EG ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MA MD MG MK MN MW MX MZ NA NI NO NZ OM PG PH PL PT RO RU SC SD SE SG SK SL SY TJ TM TN TR TT TZ UA UG US UZ VC VN YU ZA ZM ZW

AL Designated countries for regional patents

Kind code of ref document: A1

Designated state(s): BW GH GM KE LS MW MZ NA SD SL SZ TZ UG ZM ZW AM AZ BY KG KZ MD RU TJ TM AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IT LU MC NL PL PT RO SE SI SK TR BF BJ CF CG CI CM GA GN GQ GW ML MR NE SN TD TG

121 Ep: the epo has been informed by wipo that ep was designated in this application
WWP Wipo information: published in national office

Ref document number: 11403492

Country of ref document: US

WWE Wipo information: entry into national phase

Ref document number: 2007536667

Country of ref document: JP

NENP Non-entry into the national phase

Ref country code: DE

WWE Wipo information: entry into national phase

Ref document number: 1020077010924

Country of ref document: KR

122 Ep: pct application non-entry in european phase

Ref document number: 04795179

Country of ref document: EP

Kind code of ref document: A1