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WO2005122695A3 - A system for mapping defective printed circuits - Google Patents

A system for mapping defective printed circuits Download PDF

Info

Publication number
WO2005122695A3
WO2005122695A3 PCT/IL2005/000650 IL2005000650W WO2005122695A3 WO 2005122695 A3 WO2005122695 A3 WO 2005122695A3 IL 2005000650 W IL2005000650 W IL 2005000650W WO 2005122695 A3 WO2005122695 A3 WO 2005122695A3
Authority
WO
WIPO (PCT)
Prior art keywords
pcb
layer
layers
scrap
units
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/IL2005/000650
Other languages
French (fr)
Other versions
WO2005122695A2 (en
Inventor
Nir Dery
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Camtek Ltd
Original Assignee
Camtek Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Camtek Ltd filed Critical Camtek Ltd
Priority to JP2007517648A priority Critical patent/JP4923180B2/en
Priority to CN2005800248665A priority patent/CN101297305B/en
Publication of WO2005122695A2 publication Critical patent/WO2005122695A2/en
Anticipated expiration legal-status Critical
Publication of WO2005122695A3 publication Critical patent/WO2005122695A3/en
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0097—Processing two or more printed circuits simultaneously, e.g. made from a common substrate, or temporarily stacked circuit boards
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0266—Marks, test patterns or identification means
    • H05K1/0269—Marks, test patterns or identification means for visual or optical inspection
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/16—Inspection; Monitoring; Aligning
    • H05K2203/161—Using chemical substances, e.g. colored or fluorescent, for facilitating optical or visual inspection
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/16—Inspection; Monitoring; Aligning
    • H05K2203/163—Monitoring a manufacturing process

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Investigating Materials By The Use Of Optical Means Adapted For Particular Applications (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

A scrap-units-mapping system is disclosed. The system is especially designed for mapping a multi-layers PCB that contains a plurality of PCBs. The disclosed system comprised of an optical inspection system that scans each layer - both sides - of identified layers, that are intended to create a specific PCB, and marks the scrap-units on a layer map; a storage mean to store the layer maps, using any method for storing layers' information; and a combining software that combines the layer maps to create a PCB map, wherein each scrap-unit, which one of its' layers has a defect, is marked. Moreover, the system can further includes an optimization software that matches plurality of layer maps of each terrace-layer of the PCB and define sets of identified layers to join into a PCB with minimum scrap-units, enabling to collect each of the defined sets to join into a PCB.
PCT/IL2005/000650 2004-06-21 2005-06-19 A system for mapping defective printed circuits Ceased WO2005122695A2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2007517648A JP4923180B2 (en) 2004-06-21 2005-06-19 System for mapping defective printed circuits
CN2005800248665A CN101297305B (en) 2004-06-21 2005-06-19 System for Mapping Defective Printed Circuits

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
IL162650 2004-06-21
IL162650A IL162650A (en) 2004-06-21 2004-06-21 Scrap-units- mapping system for mapping multiple layers of a single board and method therefor

Publications (2)

Publication Number Publication Date
WO2005122695A2 WO2005122695A2 (en) 2005-12-29
WO2005122695A3 true WO2005122695A3 (en) 2007-05-18

Family

ID=35510182

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/IL2005/000650 Ceased WO2005122695A2 (en) 2004-06-21 2005-06-19 A system for mapping defective printed circuits

Country Status (5)

Country Link
JP (1) JP4923180B2 (en)
CN (1) CN101297305B (en)
IL (1) IL162650A (en)
TW (1) TWI275335B (en)
WO (1) WO2005122695A2 (en)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101621893B (en) * 2008-07-02 2011-04-13 欣兴电子股份有限公司 Printing and dividing method and equipment for sub-boards of defective circuit boards
CN101865652A (en) * 2009-04-15 2010-10-20 上海汽车制动系统有限公司 Detection method and system of EBS (Electronic Brake System) electromagnetic valve model discrimination
CN102338754A (en) * 2010-07-22 2012-02-01 牧德科技股份有限公司 Defect detection method for power supply layer and grounding layer of circuit board
CN102074031B (en) * 2011-01-13 2013-08-07 广东正业科技股份有限公司 Mark establishing method for printed circuit board appearance inspection machine
CN102136016A (en) * 2011-03-09 2011-07-27 瑞谷科技(深圳)有限公司 Printed circuit board (PCB) designing method and device
KR101478790B1 (en) 2013-10-14 2015-01-06 (주)에이티테크놀러지 Apparatus for testing Printed Circuit Board
US9885671B2 (en) 2014-06-09 2018-02-06 Kla-Tencor Corporation Miniaturized imaging apparatus for wafer edge
US9645097B2 (en) 2014-06-20 2017-05-09 Kla-Tencor Corporation In-line wafer edge inspection, wafer pre-alignment, and wafer cleaning
CN105588840B (en) * 2015-12-04 2019-01-25 广州视源电子科技股份有限公司 Electronic component positioning method and device
CN105873358B (en) * 2016-05-31 2019-02-05 Oppo广东移动通信有限公司 circuit board puzzle
KR101751518B1 (en) * 2016-08-24 2017-06-27 주식회사 아이디디 Marking apparatus and method for PCB panel
CN108804738B (en) * 2018-03-22 2021-04-06 广州兴森快捷电路科技有限公司 Circuit board defect tracking method and device based on positioning hole and computer equipment

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01214198A (en) * 1988-02-23 1989-08-28 Toshiba Corp Recognition of failure of multi-layer printed-circuit board
US5086477A (en) * 1990-08-07 1992-02-04 Northwest Technology Corp. Automated system for extracting design and layout information from an integrated circuit
US5204912A (en) * 1990-02-26 1993-04-20 Gerber Systems Corporation Defect verification and marking system for use with printed circuit boards
US5260779A (en) * 1992-02-21 1993-11-09 Control Automation, Inc. Method and apparatus for inspecting a printed circuit board
US20010036306A1 (en) * 2000-03-08 2001-11-01 Joachim Wienecke Method for evaluating pattern defects on a wafer surface
US20020131052A1 (en) * 2000-11-13 2002-09-19 Emery David G. Advanced phase shift inspection method
US20030086600A1 (en) * 2000-11-08 2003-05-08 Amnon Ganot Multi-layer printed circuit board fabrication system and method
US6707936B1 (en) * 1999-04-16 2004-03-16 Texas Instruments Incorporated Method and apparatus for predicting device yield from a semiconductor wafer
US6735745B2 (en) * 2002-02-07 2004-05-11 Applied Materials, Inc. Method and system for detecting defects

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000101253A (en) * 1998-09-24 2000-04-07 Ibiden Co Ltd Manufacture of multilayer printed wiring board
JP2003139720A (en) * 2001-10-31 2003-05-14 Olympus Optical Co Ltd Verifying device
IL148829A0 (en) * 2002-03-21 2002-09-12 Camtek Ltd A method for storing information on layers of a layered product
JP4282515B2 (en) * 2004-03-15 2009-06-24 パナソニック株式会社 Method for manufacturing component-embedded board and board management apparatus

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01214198A (en) * 1988-02-23 1989-08-28 Toshiba Corp Recognition of failure of multi-layer printed-circuit board
US5204912A (en) * 1990-02-26 1993-04-20 Gerber Systems Corporation Defect verification and marking system for use with printed circuit boards
US5086477A (en) * 1990-08-07 1992-02-04 Northwest Technology Corp. Automated system for extracting design and layout information from an integrated circuit
US5260779A (en) * 1992-02-21 1993-11-09 Control Automation, Inc. Method and apparatus for inspecting a printed circuit board
US6707936B1 (en) * 1999-04-16 2004-03-16 Texas Instruments Incorporated Method and apparatus for predicting device yield from a semiconductor wafer
US20010036306A1 (en) * 2000-03-08 2001-11-01 Joachim Wienecke Method for evaluating pattern defects on a wafer surface
US20030086600A1 (en) * 2000-11-08 2003-05-08 Amnon Ganot Multi-layer printed circuit board fabrication system and method
US20020131052A1 (en) * 2000-11-13 2002-09-19 Emery David G. Advanced phase shift inspection method
US6735745B2 (en) * 2002-02-07 2004-05-11 Applied Materials, Inc. Method and system for detecting defects

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
IBM TECH DIS BULL, vol. 29, no. 3, August 1983 (1983-08-01), pages 1154 - 1155 *

Also Published As

Publication number Publication date
CN101297305A (en) 2008-10-29
WO2005122695A2 (en) 2005-12-29
IL162650A0 (en) 2005-11-20
JP2008504521A (en) 2008-02-14
CN101297305B (en) 2012-08-22
TW200601927A (en) 2006-01-01
JP4923180B2 (en) 2012-04-25
IL162650A (en) 2014-09-30
TWI275335B (en) 2007-03-01

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