WO2005122396A1

WO2005122396A1 - Frequency tunable arrangement

Info

Publication number: WO2005122396A1
Application number: PCT/IB2005/051719
Authority: WO
Inventors: Johannes H. A. Brekelmans
Original assignee: Koninklijke Philips Electronics NV
Current assignee: Koninklijke Philips NV
Priority date: 2004-06-08
Filing date: 2005-05-25
Publication date: 2005-12-22
Anticipated expiration: 2006-12-08
Also published as: CN1981435A

Abstract

A tunable oscillator (VCO) provides a basic oscillator signal. A frequency scaling circuit (FDC) provides a scaled oscillator signal on the basis of the basic oscillator signal. The scaled oscillator signal has a frequency (Fmo) that is equal to the frequency (Fvco) of the basic oscillator signal divided by a scaling factor (N). A tuning control circuit (CTRL, PLC) sets the scaling factor and tunes the tunable oscillator so that the frequency of the scaled oscillator signal is at a target value. A detection circuit (ULD, LLD) detects whether an operating parameter (Vt) of the tunable oscillator has a satisfactory value (Vtmin H Vtmax). If not, the scaling factor of the frequency scaling circuit is modified.

Description

Frequency tunable arrangement

FIELD OF THE INVENTION The invention relates to a frequency tunable arrangement in which a tunable oscillator signal is scaled in frequency. The frequency tunable arrangement may be, for example, a receiver for receiving a radio frequency signal that conveys information in the form of audio, video, or data or any combination of those.

BACKGROUND OF THE INVENTION United States patent 6,370,368 describes a tuner for FM reception. The tuner comprises an oscillator that generates an oscillator signal. A frequency division circuit divides the oscillator signal so as to obtain a divided oscillator signal. A mixer circuit mixes an input signal with the divided oscillator signal. The frequency division circuit comprises a divide-by-2 divider and a divide- by-3 divider. One of the dividers is operative at a time. The divide-by-2 divider is operative in Europe and the USA where the FM band approximately ranges between 87.5 MHz and 108 MHz. The divide-by-3 divider is operative in Japan and also in Eastern Europe where the FM band approximately ranges between 76 and 91 MHz, and between 65 and 74MHz, respectively. Accordingly, oscillator frequencies required for reception in the Europe and the USA, are roughly in the same range as oscillator frequencies required for FM reception in Japan and Eastern Europe.

SUMMARY OF THE INVENTION According to an aspect of the invention, a frequency tunable arrangement comprises the following characteristics. A tunable oscillator provides a basic oscillator signal. A frequency scaling circuit provides a scaled oscillator signal on the basis of the basic oscillator signal. The scaled oscillator signal has a frequency that is equal to the frequency of the basic oscillator signal divided by a scaling factor. A tuning control circuit sets the scaling factor and tunes the tunable oscillator so that the frequency of the scaled oscillator signal is at a target value. A detection circuit detects whether an operating parameter of the tunable oscillator has a satisfactory value. If not, the scaling factor of the frequency scaling circuit is modified. The invention takes the following aspects into consideration. Tunable oscillators that are mass produced suffer from tolerances and production spread. As a result, the frequency range throughout which a tunable oscillator can be tuned will be inaccurate to a certain extent. The frequency range varies from one to another tunable oscillator of identical design. For example, let it be assumed that a tunable oscillator has been designed to have a tuning range between 1.0 and 1.2 GHz. Let it further be assumed that tolerances and production spread amount to 5%. In that case, a tunable oscillator may have a tuning range between 0.95 and 1.14 GHz. The tunable oscillator may also have a tuning range between 1.05 and 1.26 GHz. It can thus be guaranteed only that the tunable oscillator can be tuned throughout a frequency range between 1.05 and 1.14 GHz. If, however, the tunable oscillator needs to be tunable throughout the tuning range between 1.0 and 1.2 GHz, the tunable oscillator should be designed to have a tuning range between 0.95 and 1.26 GHz. The tunable oscillator should thus be designed to have a relatively large tuning range in order to account for tolerances and production spread. Only a portion of the tuning range, which the tunable oscillator will actually have, is effectively used. That is, the design needs a built-in margin. There is a further complication in oscillator design. The tunable oscillator may have one or more operating parameters, other than frequency, that are of interest. In practice, an operating parameter will have a value that varies throughout the tuning range. In a certain portion of the tuning range, the operating parameter may have satisfactory values, whereas the operating parameter may have unacceptable values in one or more other portions of the tuning range. An operating parameter of interest may be, for example, noise comprised in the basic oscillator signal. The noise will typically be relatively high at a limit of the tuning range. Since the tunable oscillator suffers from tolerances and production spread, the tunable oscillator may be close to the limit of the tuning range for a given frequency or may be relatively far from the limit. The noise will be relatively high at a frequency close to the limit of the tuning range, whereas the noise will be relatively low at a frequency that is relatively far from the limit. Consequently, there is a certain uncertainty as to the noise in the basic oscillator signal for a given frequency. The tunable oscillator may be designed such that this uncertainty is accounted for. That is, the design should have a built-in margin for noise, similar to the margin that is required for the tuning range. These margins are generally at the expense of relatively high power consumption and may adversely affect other specification points too. In accordance with the above described aspect of the invention, a frequency tunable arrangement comprises a detection circuit that detects whether an operating parameter of the tunable oscillator has a satisfactory value. If not, the scaling factor of the frequency scaling circuit is modified. The modification of the scaling factor allows that the target value for the frequency of the scaled oscillator signal can be achieved at different frequencies of the basic oscillator signal. The operating parameter of the tunable oscillator may have a satisfactory value at one or more of those frequencies whereas the operating parameter may not have a satisfactory value at other frequencies. The detection circuit forces the frequency tunable arrangement to set the scaling factor so that the tunable oscillator is at a frequency at which the operating parameter of interest is satisfactory. The invention thus allows designs with a built-in margin that can be relatively modest. Consequently, the invention allows a relatively easy design. What is more, the invention allows a relatively good performance in terms of power consumption and other specification points. A further advantage of the invention relates to the following aspects. A frequency tunable arrangement in accordance with the invention does not require elements of relatively great precision. For example, the frequency tunable arrangement may be implemented in the form of an integrated circuit. For those reasons, the invention allows cost efficient implementations. - Another aspect of the invention relates to a method of programming a frequency tunable arrangement that comprises the following elements: a tunable oscillator arranged to provide a basic oscillator signal; a frequency scaling circuit arranged to provide a scaled oscillator signal on the basis of the basic oscillator signal, the scaled oscillator signal having a frequency that is equal to the frequency of the basic oscillator signal divided by a scaling factor; and a tuning control circuit arranged to set the scaling factor and to tune the tunable oscillator so that the frequency of the scaled oscillator signal is at a target value. The method of programming comprises the following steps. In a measurement step, a useable mning range is measured. The useable tuning range is a range of frequencies of the basic oscillator signal in which, at any frequency, an operating parameter of the tunable oscillator has a satisfactory value. In a calculation step, a preferred value for the scaling factor is calculated. The preferred value is such that when the scaling factor is multiplied with the target value for the frequency of the scaled oscillator signal, a frequency is obtained that lies within the useable tuning range. In a programming step, the tuning control circuit is programmed to set the scaling factor to the preferred value when the frequency of the scaled oscillator signal needs to be tuned to the target value. The method does not require the frequency tunable arrangement to have a detection circuit. In effect, the method measures the effect of tolerances and production spread on the tunable oscillator and, in particular, the operating parameter of interest, and compensates for those effects by suitably programming the tuning control circuit. The method provides the advantages that have been described hereinbefore. These and other aspects of the invention will be described in greater detail hereinafter with reference to drawings.

BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a block diagram that illustrates a receiver. Fig. 2 is a circuit diagram that illustrates a tuning circuit within the receiver. Fig. 3 is a flow chart diagram that illustrates a method of controlling the tuning circuit. Fig. 4 is a graph that illustrates a frequency scaling within the tuning circuit.

DETAILED DESCRIPTION Fig. 1 illustrates a receiver REC that receives a radio frequency signal RF and provides in response thereto a video signal VID for display on a display device DPL. The receiver REC comprises a front-end circuit FEC, a mixer circuit MIX, a tuning circuit TUC, a backend circuit BEC, and a control circuit CTRL. The control circuit CTRL may interact, for example, with a remote-control RCD. The receiver REC operates as follows. The front-end circuit FEC filters and amplifies the radio frequency signal RF so as to obtain a mixer input signal. The control circuit CTRL applies mning values to the tuning circuit TUC. Those tuning values depend on the frequency, or channel, to which the receiver needs to be tuned. The tuning circuit TUC generates a mixer oscillator signal on the basis of the tuning values. The mixer oscillator signal has a frequency that can be varied throughout a frequency band between approximately 300 and 900 MHz. The mixer circuit MIX multiplies the mixer input signal, which is derived from the radio frequency signal RF, with the mixer oscillator signal so as to obtain a mixer output signal. In effect, the mixer circuit MIX carries out a frequency shift: the mixer output signal is a frequency shifted version of the mixer input signal. The frequency shift is determined by the frequency Fmo of the mixer oscillator signal. The backend circuit BEC selects a certain portion of the frequency spectrum of the mixer output signal. The backend circuit BEC processes that portion of the frequency spectrum processes so as to obtain the video signal to be displayed on the display device. Fig. 2 illustrates the tuning circuit TUC that forms part of the receiver illustrated in Fig. 1. The tuning circuit TUC comprises a voltage controlled oscillator VCO, a frequency division circuit FDC, a phase lock loop circuit PLC, an upper limit detector ULD, and a lower limit detector LLD. The tuning circuit TUC receives the following tuning values from the control circuit CTRL: a phase lock loop control value Cpl, which is applied to the phase lock loop circuit PLC, and a divider control value Cfd, which is applied to the frequency division circuit FDC. The mixer oscillator signal, which is applied to the mixer circuit MIX illustrated in FIG. 1, is obtained from an output of the frequency division circuit FDC. The tuning circuit TUC operates as follows. The voltage controlled oscillator VCO generates a voltage controlled oscillator signal. The voltage controlled oscillator signal has a frequency Fvco that can be tuned throughout a frequency range that is nominally between 6.60 and 7.42 GHz. The frequency Fvco varies as a function of a tuning voltage Vt applied to a tuning input of the voltage controlled oscillator VCO. The frequency division circuit FDC divides the frequency of the voltage controlled oscillator signal by a division factor N. The frequency division circuit FDC provides the mixer oscillator signal on the basis of the voltage controlled oscillator signal. More specifically, the mixer oscillator signal has a frequency Fmo that is equal to the frequency Fvco of the voltage controlled oscillator signal divided by the division factor N. The phase lock loop circuit PLC provides the tuning voltage Vt on the basis of the mixer oscillator signal and of a tuning control value. More specifically, the phase looked loop circuit PLC divides the frequency Fmo of the mixer oscillator signal. The phase locked loop circuit PLC compares the frequency divided mixer oscillator signal with a reference frequency signal. The tuning voltage Vt is derived from the result of this comparison. The phase locked loop circuit PLC varies the tuning voltage Vt such that the frequency of the mixer oscillator signal is equal to that of the reference frequency signal multiplied by a factor. This factor depends on the phase lock loop control value Cpl from the control circuit CTRL. The phase looked loop control value Cpl thus defines a target value for the mixer oscillator signal. The upper limit detector ULD compares the tuning voltage Vt with an upper limit value Vtmax. The upper limit detector ULD provides an upper limit warning signal Swul if the tuning voltage Vt has a value that is above the upper limit value Vtmax. The lower limit detector LLD compares the tuning voltage Vt with a lower limit value Vtmin. The lower limit detector LLD provides a lower limit warning signal Swll if the tuning voltage Vt has a value that is below the lower limit value Vtmin. The tuning voltage Vt is a reasonably accurate indication of the amount of noise in the voltage controlled oscillator signal and the amount of noise in the mixer oscillator signal. Such noise affects reception quality of the receiver REC illustrated in FIG. 1. In many applications, the noise tends to be relatively high when the tuning voltage Vt is at a relatively low or a relatively high value. The lower limit value Vtmin and upper limit value Vtmax are preferably chosen on the basis of the noise in the voltage controlled oscillator signal, which varies as a function of the tuning voltage Vt. The lower limit value Vtmin and the upper limit value Vtmax define a preferred tuning voltage range for which there is a reasonable assurance that the noise in the mixer oscillator signal is at an acceptable level. If the tuning voltage Vt is not within this tuning voltage Vt range, there is an appreciable risk that the noise in the mixer oscillator signal is to high. In that case, either the lower limit warning signal Swll or the upper limit warning signal Swul is given. The control circuit CTRL receives those warning signals. Fig. 3 illustrates an operation of the control circuit CTRL with respect to the lower limit and the upper limit warning signal Swul. In a first step ST 1, the control circuit CTRL checks whether the lower limit warning signal Swll is present or not. The control circuit CTRL carries out a second step ST2 if the lower limit warning signal Swll is present. In the second step ST2, the control circuit CTRL modifies the divider control value Cfd so as to increment the division factor N of the frequency division circuit FDC. In a third step ST3, the control circuit CTRL modifies the phase lock loop control value Cpl to compensate for the increase in division factor N. If, in the first step ST1, the control circuit CTRL establishes that the lower limit warning signal Swll is not present, the control circuit CTRL carries out a fourth step ST4. In the fourth step ST4, the control circuit CTRL checks whether the upper limit warning signal Swul is present or not. The control circuit CTRL carries out a fifth step ST5 if the upper limit warning signal Swul is present. In the fifth step ST5, the control circuit CTRL modifies the divider control value Cfd so as to decrement the division factor N of the frequency division circuit FDC. In a sixth step ST6, the control circuit CTRL modifies the phase lock loop control value Cpl to compensate for the decrease in division factor N. When the control circuit CTRL modifies the divider control value Cfd and the phase lock loop control value Cpl, the tuning circuit TUC will temporarily be in a transition state before reaching a steady-state for the new control values. Preferably, the control circuit CTRL ignores the lower limit warning signal Swll and the upper limit warning signal Swul during the transition state. Consequently, it is preferable to have a waiting step after the third step ST3 has been carried out and after the sixth step ST6 has been carried out. Such a waiting step introduces a delay before the first step ST1 is carried out anew. The delay should preferably be sufficiently long for the tuning circuit TUC to have reached the steady-state when the first step ST1 is carried out anew. Referring again to Fig. 2, the tuning circuit TUC is made to operate in a new context when the division factor N of the frequency division circuit FDC has changed. Whatever is the context, the phase lock loop circuit PLC will strive for a phase lock condition. That is, the phase lock loop circuit PLC will vary the tuning voltage Vt so that the mixer oscillator signal has a frequency that is equal to the target value. Since the division factor N of the frequency division circuit FDC has changed, the tuning voltage Vt for which the phase lock condition is achieved will be different from the tuning voltage Vt for which the phase lock condition was achieved in the previous context. In the new context, the tuning voltage Vt may lie within the preferred tuning voltage range, which is between the lower limit value Vtmin and the upper limit value Vtmax. If this is not the case, the division factor N of the frequency division circuit FDC will be changed anew until the phase lock condition is achieved with the tuning voltage Vt being in the preferred tuning voltage range. Fig. 4 illustrates a set of suitable division factors N for the frequency division circuit FDC. The horizontal axis represents the frequency Fmo of the mixer oscillator signal. The vertical axis represents the division factor N. Fig. 4 illustrates a situation in which the voltage controlled oscillator VCO is mned throughout a frequency range between 7.2 and 8.1 GHz. This is the nominal tuning range of the voltage controlled oscillator VCO: the voltage controlled oscillator VCO has been designed such that when all elements are at their nominal value, the voltage controlled oscillator VCO is tunable between 7.2 and 8.1 GHz, while the tuning voltage Vt remains in the preferred tuning voltage range. As explained hereinbefore, although the voltage controlled oscillator VCO has been designed to operate in that manner, the voltage controlled oscillator VCO may have a mning range that is different due to tolerances and production spread. As explained hereinbefore, the division factor N of the frequency division circuit FDC is set to a value for which the tuning voltage Vt is in the preferred tuning voltage range at the given target value for the frequency of the mixer oscillator signal. The control circuit CTRL is preferably programmed to operate as follows. Let it be assumed that the frequency of the mixer oscillator signal needs to be tuned to a certain target value. The control circuit CTRL then sets the division factor N of the frequency division circuit FDC to a value for which the tuning voltage Vt is likely to be within the preferred tuning voltage range. This can be achieved, for example, by programming the control circuit CTRL to set the division factor N in accordance with the graph illustrated in Fig. 4. For example, when the frequency Fmo of the mixer oscillator signal should be 900MHz, the control circuit CTRL sets the division factor N to 8. When the frequency Fmo of the mixer oscillator signal should be 600MHz, the control circuit CTRL sets the division factor N to 12. When the frequency Fmo of the mixer oscillator signal should be 300MHz, the control circuit CTRL sets the division factor N to 24. In each case, the voltage controlled oscillator VCO is at a frequency of 7.2 GHz. Nominally, the mning voltage Vt will be within the preferred tuning voltage range. If this is not the case, either the upper limit detector ULD or the lower limit detector LLD will detect this. The control circuit CTRL will take appropriate action: the division factor N of the frequency division circuit FDC is set at a different value for which the tuning voltage Vt is within the preferred tuning voltage range. Preferably, the control circuit CTRL is programmed to recognize that it has taken the aforementioned action and, furthermore, is programmed to take this into account a next time when setting the division factor N. For example, let it be assumed that the mixer oscillator signal needs to be tuned to 600 MHz. Let it further be assumed that the control circuit CTRL initially sets the division factor N to 12. The phase lock loop circuit PLC will control the tuning voltage Vt so that the voltage controlled oscillator signal has a frequency of 7.2 GHz. Let it now be assumed that the tuning voltage Vt is below the lower limit value Vtmin. The lower limit detector LLD will detect this and, in response, the control circuit CTRL will set the division factor N to 13. The phase locked loop circuit PLC will control the tuning voltage Vt so that the voltage controlled oscillator signal has a frequency of 7.8 GHz. The mning voltage Vt will have a higher value compared with the case where the division factor N was 12. Let it be assumed that the mning voltage Vt is now within the preferred tuning voltage range. The control circuit CTRL may thus recognize this, as it were, and set the division factor N to 13 a next time when the mixer oscillator signal needs to be tuned to 600 MHz. For example, the control circuit CTRL may comprise an EEPROM memory which contains a division factor table. The division factor table defines various different portions of the tuning range. The division factor table associates a preferred division factor N with each portion of the tuning range. The division factor table may initially be identical for each tuning circuit TUC of a plurality of tuning circuits that has been mass-produced. In course of time, the control circuit CTRL will differently modify the division factor table for each respective tuning circuit TUC. The reason for this is that the effects of tolerances and production spread will vary from one mning circuit to another. Eventually, different mning circuits will have different division factor tables. It is possible to achieve a satisfactory operation with a tuning circuit TUC similar to that illustrated in Fig. 2 but that does not comprise limit detectors. In such an embodiment, one or more relevant properties of the mning circuit TUC are measured and the control circuit CTRL is suitably programmed on the basis of that measurement. For example, it is measured what frequencies the voltage controlled oscillator signal has, when the mning voltage Vt is at the lower limit value Vtmin and at the upper limit value Vtmax, respectively. These frequencies are the boundaries of a frequency range within which the tuning voltage Vt is in the preferred tuning voltage range. Knowing this frequency range, the control circuit ^■ CTRL can be programmed so that, for any desired frequency Fmo of the mixer oscillator signal, the division factor N of the frequency division circuit FDC is set to a value for which the tuning voltage Vt is in the preferred tuning voltage range. For example, the control circuit CTRL may have a division factor table that is adapted to the properties of the tuning circuit. An embodiment without detectors as described in the preceding paragraph, does not correct an error that, for example, a variation in temperature, a variation in supply voltage or aging may cause, h contradistinction, the embodiment illustrated in Fig. 2 does correct such errors because it comprises detectors. The tuning circuit TUC described hereinbefore is well suited to be implemented as an integrated circuit. The voltage controlled oscillator VCO may be, for example, an LC oscillator having an inductive resonance part and a capacitive resonance part. The inductive resonance part may comprise a conductive path, which is formed in a metal layer for interconnecting electrical elements of the integrated circuit. The conductive path may have a spiral-like form. The capacitive part of the LC oscillator may comprise a voltage dependent capacitor, which is formed by a PN junction. CONCLUDING REMARKS The detailed description hereinbefore with reference to the drawings illustrates the following characteristics. A tunable oscillator (voltage controlled oscillator VCO) provides a basic oscillator signal. A frequency scaling circuit (frequency division circuit FDC) provides a scaled oscillator signal (mixer oscillator signal) on the basis of the basic oscillator signal. The scaled oscillator signal has a frequency (Fmo) that is equal to the frequency (Fvco) of the basic oscillator signal divided by a scaling factor (N). A tuning control circuit (control circuit CTRL in combination with phase lock loop circuit PLC) sets the scaling factor and tunes the tunable oscillator so that the frequency of the scaled oscillator signal is at a target value. A detection circuit (upper limit detector ULD and lower limit detector LLD) detects whether an operating parameter (tuning voltage Vt) of the tunable oscillator has a satisfactory value (between the lower limit value Vtmin and the upper limit value Vtmax). If not, the scaling factor of the frequency scaling circuit is modified. The aforementioned characteristics can be implemented in numerous different manners. In order to illustrate this, some alternatives are briefly indicated. The frequency tunable arrangement may be, for example, a measurement signal generator. The tunable oscillator may be, for example, a current controlled oscillator. The frequency scaling circuit may be, for example, a frequency multiplier circuit in which case the scaled oscillator signal has a frequency which is higher than the frequency of the oscillator signal. The scaling factor may be a non-integer value. For example, the scaling factor may be Vi or 1 /4. The operating parameter that is detected may be, for example, the amplitude of the basic oscillator signal. The operating parameter may also be a bias current flowing through a component of the tunable oscillator or a leakage current. The operating parameter may be any signal that provides a reasonably accurate indication as to whether the tunable oscillator operates in a satisfactory manner or not. Furthermore, the specific embodiments in the detailed description hereinbefore with reference to the drawings can be implemented in numerous different manners. In order to illustrate this, some alternatives are briefly indicated. The tuning circuit TUC illustrated in Fig. 2 may be modified so that the phase locked loop circuit PLC receives the voltage controlled oscillator signal as an input signal instead of the mixer oscillator signal.

Furthermore, the phase locked loop circuit PLC may be replaced by any suitable type of frequency control circuit. In the yet another alternative, the phase locked loop circuit PLC may be dispensed with if frequency accuracy is of less importance. The voltage controlled oscillator VCO illustrated in Fig. 2 may be designed such that it is tunable throughout a relatively wide frequency range. In that case, fewer different division factors N will be sufficient compared to those illustrated in Fig. 4. Conversely, the voltage controlled oscillator VCO may be designed to have a relatively narrow frequency range. In that case, it is appropriate to have more division factors N than those illustrated in Fig. 4. The mning circuit TUC illustrated in Fig. 2 may comprise an internal control circuit for controlling the division factor N of the frequency division circuit FDC. The internal control circuit may comprise, for example, an up-down counter having a count value that determines the division factor N. The upper limit warning signal causes the up-down counter to decrement the count value and thus to decrement the division factor N. The lower limit warning signal causes the up-down counter to increment the count value and thus to increment the division factor N. There are numerous ways of implementing functions by means of items of hardware or software, or both. In this respect, the drawings are very diagrammatic, each representing only one possible embodiment of the invention. Thus, although a drawing shows different functions as different blocks, this by no means excludes that a single item of hardware or software carries out several functions. Nor does it exclude that an assembly of items of hardware or software or both carry out a function. The remarks made herein before demonstrate that the detailed description with reference to the drawings, illustrate rather than limit the invention. There are numerous alternatives, which fall within the scope of the appended claims. Any reference sign in a claim should not be construed as limiting the claim. The word "comprising" does not exclude the presence of other elements or steps than those listed in a claim. The word "a" or "an" preceding an element or step does not exclude the presence of a plurality of such elements or steps.

Claims

CLAIMS:

1. A frequency tunable arrangement (REC) comprising: a tunable oscillator (VCO) arranged to provide a basic oscillator signal; a frequency scaling circuit (FDC) arranged to provide a scaled oscillator signal on the basis of the basic oscillator signal, the scaled oscillator signal having a frequency (Fmo) that is equal to the frequency (Fvco) of the basic oscillator signal divided by a scaling factor (N); a tuning control circuit (CTRL, PLC) arranged to set the scaling factor and to tune the tunable oscillator so that the frequency of the scaled oscillator signal is at a target value; and - a detection circuit (ULD, LLD) arranged to detect whether an operating parameter (Vt) of the tunable oscillator has a satisfactory value (Vtmin <→ Vtmax) and, if not, to modify the scaling factor of the frequency scaling circuit.

2. A frequency tunable arrangement as claimed in claim 1, wherein the detection circuit (ULD, LLD) is arranged to detect a tuning control signal (Vt) as a function of which the frequency (Fvco) of the basic oscillator signal varies, the detection circuit being further arranged to modify the scaling factor (N) of the frequency scaling circuit (FDC) if the tuning control signal does not have a satisfactory value.

3. A frequency tunable arrangement as claimed in claim 1, wherein the tuning control circuit (CTRL, PLC) comprises a memory for storing a scaling factor table, which defines various different portions of a toning range, and which associates a preferred scaling factor to a portion of the tuning range.

4. A method of tuning a frequency tunable arrangement (REC) that comprises a tunable oscillator arranged (VCO) arranged to provide a basic oscillator signal, and a frequency scaling circuit (FDC) arranged to provide a scaled oscillator signal on the basis of the basic oscillator signal, the scaled oscillator signal having a frequency (Fmo) that is equal to the frequency of the basic oscillator signal (Fvco) divided by a scaling factor (N), the method comprising: a mning step in which the scaling factor is set and the mnable oscillator is tuned so that the frequency of the scaled oscillator signal is at a target value, - an evaluation step (ST1, ST4) in which an evaluation is made as to whether an operating parameter (Vt) of the tunable oscillator has a satisfactory value (Vtmin → Vtmax); and, if not, an adjustment step (ST2, ST5) in which the scaling factor of the frequency scaling circuit is modified, after which the tunable oscillator is tuned anew and the evaluation step is carried out anew.

5. A method of programming a frequency mnable arrangement (REC) that comprises: a mnable oscillator (VCO) arranged to provide a basic oscillator signal; - a frequency scaling circuit (FDC) arranged to provide a scaled oscillator signal on the basis of the basic oscillator signal, the scaled oscillator signal having a frequency (Fmo) that is equal to the frequency (Fvco) of the basic oscillator signal divided by a scaling factor (N); and a mning control circuit (CTRL, PLC) arranged to set the scaling factor and to mne the tunable oscillator so that the frequency of the scaled oscillator signal is at a target value, the method comprising: a measurement step in which a useable tuning range is measured, the useable mning range being a range of frequencies of the basic oscillator signal in which, at any frequency, an operating parameter (Vt) of the mnable oscillator has a satisfactory value (Vtmin <→ Vtmax); a calculation step in which a preferred value for the scaling factor is calculated, the preferred value being such that when the scaling factor is multiplied with the target value for the frequency of the scaled oscillator signal, a frequency is obtained that lies within the useable tuning range; and a programming step in which the tuning control circuit is programmed to set the scaling factor to the preferred value when the frequency of the scaled oscillator signal needs to be tuned to the target value.

6. A signal display arrangement comprising a frequency mnable arrangement

(REC) as claimed in claim 1, and a display device (DPL) for displaying a signal that has been selected by means of the frequency mnable arrangement.