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WO2005117121B1 - Reseaux de memoire, procede de formation de reseaux de memoire et procede de formation de contacts avec des lignes de bits - Google Patents

Reseaux de memoire, procede de formation de reseaux de memoire et procede de formation de contacts avec des lignes de bits

Info

Publication number
WO2005117121B1
WO2005117121B1 PCT/US2005/014466 US2005014466W WO2005117121B1 WO 2005117121 B1 WO2005117121 B1 WO 2005117121B1 US 2005014466 W US2005014466 W US 2005014466W WO 2005117121 B1 WO2005117121 B1 WO 2005117121B1
Authority
WO
WIPO (PCT)
Prior art keywords
canceled
forming
trenches
electrically insulative
conductive
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US2005/014466
Other languages
English (en)
Other versions
WO2005117121A2 (fr
WO2005117121A3 (fr
Inventor
Luan C Tran
Fred D Fishburn
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Micron Technology Inc
Original Assignee
Micron Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Micron Technology Inc filed Critical Micron Technology Inc
Priority to JP2007509746A priority Critical patent/JP2007535150A/ja
Publication of WO2005117121A2 publication Critical patent/WO2005117121A2/fr
Publication of WO2005117121A3 publication Critical patent/WO2005117121A3/fr
Publication of WO2005117121B1 publication Critical patent/WO2005117121B1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
    • H10B12/0335—Making a connection between the transistor and the capacitor, e.g. plug
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/09—Manufacture or treatment with simultaneous manufacture of the peripheral circuit region and memory cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
    • H10B12/315—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor with the capacitor higher than a bit line
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/482—Bit lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/485—Bit line contacts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/50—Peripheral circuit region structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H10B41/42—Simultaneous manufacture of periphery and memory cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • H10B63/10—Phase change RAM [PCRAM, PRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S257/00—Active solid-state devices, e.g. transistors, solid-state diodes
    • Y10S257/906—Dram with capacitor electrodes used for accessing, e.g. bit line is capacitor plate
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S257/00—Active solid-state devices, e.g. transistors, solid-state diodes
    • Y10S257/908—Dram configuration with transistors and capacitors of pairs of cells along a straight line between adjacent bit lines

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Memories (AREA)

Abstract

Cette invention concerne des réseaux de mémoire, ainsi que des procédés pouvant être utilisés pour former des réseaux de mémoire. Un arrêt de gravure structuré peut être utilisé pendant la fabrication de réseaux de mémoire, l'arrêt de gravure recouvrant les points de contact des noeuds de stockage et laissant des ouvertures jusqu'aux points de contact des lignes de bits. Un matériau isolant peut être appliqué sur l'arrêt de gravure et sur les points de contact des lignes de bits, tandis que des tranchées peuvent être formées dans le matériau isolant. Un matériau conducteur peut être disposé à l'intérieur des tranchées pour former des lignes d'interconnexion de lignes de bits qui sont en contact électrique avec les points de contact des lignes de bits et qui sont électriquement isolées des points de contact des noeuds de stockage par l'arrêt de gravure. Dans un traitement ultérieur, des ouvertures peuvent être formées à travers l'arrêt de gravure vers les points de contact des noeuds de stockage. Des dispositifs de stockage de mémoire peuvent ensuite être formés dans les ouvertures et en contact électrique avec les points de contact des noeuds de stockage.
PCT/US2005/014466 2004-04-26 2005-04-26 Reseaux de memoire, procede de formation de reseaux de memoire et procede de formation de contacts avec des lignes de bits Ceased WO2005117121A2 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2007509746A JP2007535150A (ja) 2004-04-26 2005-04-26 メモリ・アレイ、メモリ・アレイを形成する方法、及びビット線に対するコンタクトを形成する方法

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/832,543 2004-04-26
US10/832,543 US7279379B2 (en) 2004-04-26 2004-04-26 Methods of forming memory arrays; and methods of forming contacts to bitlines

Publications (3)

Publication Number Publication Date
WO2005117121A2 WO2005117121A2 (fr) 2005-12-08
WO2005117121A3 WO2005117121A3 (fr) 2006-04-06
WO2005117121B1 true WO2005117121B1 (fr) 2006-05-18

Family

ID=34973256

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2005/014466 Ceased WO2005117121A2 (fr) 2004-04-26 2005-04-26 Reseaux de memoire, procede de formation de reseaux de memoire et procede de formation de contacts avec des lignes de bits

Country Status (5)

Country Link
US (4) US7279379B2 (fr)
JP (1) JP2007535150A (fr)
KR (1) KR100821451B1 (fr)
CN (1) CN100495709C (fr)
WO (1) WO2005117121A2 (fr)

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Also Published As

Publication number Publication date
CN100495709C (zh) 2009-06-03
US20050236649A1 (en) 2005-10-27
WO2005117121A2 (fr) 2005-12-08
JP2007535150A (ja) 2007-11-29
US20050239244A1 (en) 2005-10-27
KR20070012395A (ko) 2007-01-25
US7659161B2 (en) 2010-02-09
US7384847B2 (en) 2008-06-10
US7279379B2 (en) 2007-10-09
KR100821451B1 (ko) 2008-04-11
CN1947252A (zh) 2007-04-11
US20050239243A1 (en) 2005-10-27
US20050236656A1 (en) 2005-10-27
US7288806B2 (en) 2007-10-30
WO2005117121A3 (fr) 2006-04-06

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