WO2005109733A1

WO2005109733A1 - Clock frequency reduction in communications receiver with coding

Info

Publication number: WO2005109733A1
Application number: PCT/RU2005/000250
Authority: WO
Inventors: Igor Anatolievich Abrosimov; Alexander Roger Deas; David Coyne
Original assignee: Igor Anatolievich Abrosimov
Priority date: 2004-05-06
Filing date: 2005-05-06
Publication date: 2005-11-17

Abstract

The present invention relates to the reduction of the clock frequency in an over-sampling high-speed receiver and a method of the same. The receiver comprises a signal processor for processing encoded data with a minimum run-length greater than one bit, which selects data value from the over-sampled data in the middle of a two-bit period. The receiver further comprises a transition processor, a clock recovery unit, an eye-tracker which selects the centre of the two-bit period data cells and transition two-bit period cells; and an output data processor which decodes the data from the two-bit periods through the control signals from the transition processor and generates an output data word of single-bit data cells.

Description

CLOCK FREQUENCY REDUCTION IN COMMUNICATIONS RECEIVER WITH CODING

Technical Field The present invention relates to the communication of signals, in particular, to the reception of digital signals. More specifically, the present invention relates to the reduction of the clock frequency in a communications receiver where coding has been applied to the data, the code having a minimum run length greater then one data bit. The present invention is particularly applicable to interfaces between integrated circuits and for high-speed communications networks.

Background of the Invention In communications systems it is generally known that coding of data may be used to provide some of the following benefits: - improve the error detecting and checking capabilities - reduce the spectral bandwidth of data - improve the bit error rate (BER) of a system - increase the length of the communications channel - increase the data rate in a communications system - define a maximum run-length of logical ones or zeros. A further use of a code may be described with reference to the XAUI communications standard. In this scheme an 8b10b code is utilised where the run- length is one bit. The 8b10b code selected has the property of dc balance. That is, the encoded data over every code word contains an equal number of ones and zeros. A benefit of this code is that the signals interfacing the transmitter and receiver may be ac coupled to the communications medium and the transmitter and receiver operate at different common mode voltage levels. However, it should be noted that coding does not come without drawbacks. By means of example, the timing of a code with a minimum run-length of 2 bits is now discussed. A code such as an 8b 12b code can be generated where every 8 bits of input data are mapped into 12 bits of coded, output data. There are 4096 possible output code words in an 8b12b code. It is possible to map the 256 possible code words from the original data into 256 of the possible 4096 output code words in such a way that the minimum spacing between transitions is 2 data bits. These 12 bits must be transmitted in the same period as the original 8 bits of non-coded data. That is, the data rate in the communications medium must be increased. In a 10Gbps communications system where non-coded data is used, one bit period is 100ps. When data is passed through a coder such as the 8b12b described above then the bit period cell is reduced in direct relation to the ratio of the number of input code bits to the number of output code bits. Figure 1A shows a serial input data word 10 of eight bits being passed into an 8b12b coder 20 that generates a twelve bit output word 30 at 15Gbps. In this example the bit period reduces from 100ps to 66.6ps. Figure 1 B shows the eye patterns that would be obtained with a 10Gbps non-coded serial data stream 11 and an 8b12b coded serial data stream 12 using a conventional receiver decoding technique. For a given channel, where the same transmitter generated non-coded 10Gbps and 8b12b coded 10Gbps data it would at first seem that the eye opening decreases. However, what needs to be taken into account is that the minimum spacing between transitions has been increased through the application of the code to the data. Figure 1 C depicts a waveform 13 obtained from triggering an oscilloscope from the edges of the data. It can be seen that the first eye opening is wider and subsequent eye openings are smaller. However, the second eye opening occurs as a result of separation between transitions occurring at three bit periods intervals from the trigger point and not as a result of separation between transitions of one bit period. It can be seen that the spacing between transitions increases from 100ps to 133.2ps for non-coded 10Gbps and 8b12b coded data streams. As a result of the increased spacing between transitions the spectral bandwidth of the encoded data is reduced. Reducing the spectral content of the data means that the eye at the receiver-end of a communications channel may be increased in width and height. This may allow either more robust communication, that is, lower bit error rate or, an increase in the length of the communications channel or, an increase in the data rate, or a combination of these features. The drawback associated with coding is the increased frequency of the oscillators used in the transmitter and receiver. It is widely accepted that the clock source for transmission and reception of encoded data must be increased in direct relation to the code ratio. It is common to operate a receiver with a half-rate clock that, in this example, would mean a clock increase from 5GHz to 7.5GHz when employing 8b12b coded data for a 10Gbps communications system. The generation of a higher frequency clock and routing of the said clock around a system whether it be an ASIC or other communications system can significantly increase the power consumption of the system. Further, consider the following 10Gbps communications system that utilises several, alternate coding schemes (only one coding scheme being operational at any one time): - 64b66b, minimum run-length of one bit, with a half-rate clock of 5.15625GHz. - 8b12b, minimum run-length of two bits, with a half-rate clock of 7.5GHz. - 8b16b, minimum run-length of three bits, with a half-rate clock of 10GHz. In this communications system it would be necessary to design a clock oscillator that would cover the frequency range 5GHz to 10GHz. Further, it may be necessary to design the oscillator with an increased frequency range to cope with component tolerances, supply voltages and temperature variations. Without consideration of component tolerances, supply and temperature variations, the ratio of the maximum frequency to minimum frequency of such an oscillator is almost 2X. It is the purpose of the current invention to reduce the oscillator frequency of a receiver for data coded with run-lengths greater than one bit by a factor of 2 times, giving: - 64b66b half-rate clock frequency of 5.15625GHz. - 8b12b quarter-rate clock frequency of 3.75GHz. - 8b16b quarter rate clock frequency of 5GHz. The ratio of maximum to minimum clock frequency in this system is now reduced to 1.33X compared to 2X previously. In a conventional data recovery circuit the data is sampled by a clock locked to the data in a clock and data recovery (CDR) phase locked loop (PLL). The data is sampled in the centre of the bit-cell. Often, quadrature clocks operating at half the data rate are used in a clock and data recovery circuit one clock being aligned to the bit-cell boundaries and the other to the bit-cell centre. Decoding of the data is accomplished by the clock positioned at the centre of the bit-cell latching the data. Figure 1 D shows a timing diagram with serial data stream 100, quadrature clocks l_CLK 41 and Q_CLK 42 along with a schematic of the re-timing element 40, producing the serial output data stream 101. This technique could be applied to coded data as well as non-coded data. However, reducing the clock rate by a factor of two, to reduce power consumption, would not allow this simple data re- timer to operate correctly with coded data. One technique used in a high performance serial communications receiver is over-sampling the serial data and processing the over-sampled data to track low frequency random jitter, see for example, WO 02/078228 and US provisional application 60/552,723 filed on 15.03.2004. In an over-sampling receiver many samples are taken per bit period and these samples processed to determine the optimum sampling position in the bit-cell. A typical over-sampling ratio is 16X that is, 16 samples are taken per bit. Processing is generally performed over multiple bit-periods to reduce the speed of the circuitry performing the processing. The process of reducing the clock frequency is called deserialisation where the serial over-sampled data bits are converted to a larger parallel data word at a lower clock rate. Figure 2A shows an example of a receiver based on the over-sampling technique disclosed in WO 02/078228. The serial data stream 100 is conditioned by methods of amplification and equalisation by buffer 110, to an amplitude level where it is able to drive the input of a number of samplers 120 with their inputs connected in parallel. The clock input of each sampler is connected to one of the outputs of a sampling clock generator PLL 130. The sampling clock generator PLL 130 generally operates at a frequency of one-half of the data rate for example, 5GHz for a 10Gbps data stream. The multi-phase clock outputs 135 of the sampling clock generator PLL 130 are nominally equally-spaced in time and in this example, for a 5GHz oscillation frequency and an over-sampling ratio of 16X, each output is separated by 1/16^th of the period i.e. 6.25ps. The multi-phase clock outputs 135 of the sampling clock generator PLL 130 are connected to the clock inputs of samplers 120. Each phase samples the received data in the samplers 120. The outputs of the samplers 120 are passed to a deserialising circuit 140 that converts the serial data stream into a parallel data word 150. The parallel data word 150 represents 16 bits of the input signal sampled at 16X per bit, giving a total of 256 data. The parallel output word 150 from the deserialiser 140 is passed to a signal processor block 180 that performs data recovery, eye tracking and other such functions. The over-sampling receiver may also perform clock recovery as described in patent application "Clock Recovery in an Over-sampled Serial Communications System, US 60/558,154 filed on 01.04.04 by the inventors of the present application. The RX PLL 130 uses a dual phase detector architecture that initially locks the sampling clock generator PLL 130 to a reference frequency 160 of frequency 156.25MHz that may be asynchronous to the data frequency. During the initial lock the RX PLL 130 is configured with a feedback divider connected to one of the multi-phase clock outputs. The VCO frequency is divided by a ratio of 32X from 5GHz to 156.25MHz. The feedback clock and the reference clock are compared in a traditional phase and frequency detector that generates signals to drive the charge pump in the RX PLL. Once lock is attained, the architecture of the RXPLL is changed to include the clock recovery phase detector inside the signal-processing block 180. The clock recovery phase detector generates signals 170 to drive the RX PLL charge pump and locks the RX PLL 130 and the multi-phase clocks 135 to the data. The basic over-sampling receiver architecture described above and depicted in Figure 2A may be used with coded data with increased minimum run- length. To use the over-sampling receiver as depicted in Figure 2A with a data 8b12b coded would require that the RX PLL and multi-phase clocks operate at 50% higher speed than non-coded data at the same raw data rate. A significant increase in power dissipation would result. However, having the ability to reduce the clock frequency could result in lower power dissipation. Using a given transmitter and communications channel for comparing the received signals of coded and non-coded data, the effective eye opening is increased in amplitude and time due to the lower spectral content of the coded data. No use of the spectral content reduction is currently made. Thus, it has been shown that it would be highly advantageous in a communications receiver to use coding techniques to have the means to reduce the clock frequency, power dissipation and VCO tuning range or obtain improvements in BER, communication distance or increased data rate in a given communications medium. OBJECT OF THE PRESENT INVENTION It is therefore a primary objective of the present invention to provide a system that can be used to lower the clock frequency over conventional techniques in an over-sampling receiver. It is another primary objective of the present invention to use coding of the data where the code has a minimum run-length greater than one bit. It is another primary objective to operate an over-sampling receiver with a quarter-rate clock. It is another primary objective to reduce the sampling rate from 16 samples per bit to 16 samples per pair of bits. It is another primary objective of the present invention to reduce the power dissipation of an over-sampling receiver. It is another primary objective of the present invention to reduce the VCO tuning range when used in an over-sampling receiver with multiple codes applied to the data. It is another primary objective of the present invention to provide an over- sampling receiver that can be economically implemented in a semiconductor integrated circuit. It is another primary objective to increase the communication channel length with coding. It is another primary objective to decrease the bit error rate (BER) of a communications system through coding. A method by which through a combination of over-sampling and coding the opening of the effective eye is increased. The method, proposed in this invention, is applicable to all coded data where the minimum run-length of the code is 2 or more bits. BRIEF SUMMARY OF THE INVENTION The present invention relates to a device and method that uses coding of data to reduce clock rates, while increasing performance either through lower bit error rate or, increased communications channel length or a combination of both lower error rate and increased communications channel length. The present invention also lowers power dissipation and reduces the RX PLL VCO tuning range. According to one aspect of the invention, a signal processor for processing encoded data with a minimum run-length greater than one bit is provided, comprising: - an input data processor which comprises data selectors for selecting the data value from the over-sampled data in the middle of a two-bit period; - a transition processor for detecting transitions in a binary data stream; - a clock recovery unit, - an eye-tracker which selects the centre of the two-bit period data cells and transition two-bit period cells; and - an output data processor which decodes the data from the two-bit periods through the control signals from the transition processor and generates an output data word of single-bit data cells. According to another aspect of the invention, a high-speed receiver for coded data comprises: a sampling system which over-samples the data and provides a set of samples of the received signal; provided with a voltage controlled oscillator (VCO) generating multiple clocks for spreading the samples in time so that each bit interval is covered by several samples; the receiver further comprising a dual phase detector phase locked loop configured with a clock recovery phase detector, a phase and frequency detector and a lock detector; wherein locks the VCO to an external reference frequency that is close to, but not exactly equal to, the frequency of the sampled data, and within the capture range of the clock recovery phase detector, wherein the frequency lock detector determines when lock is achieved, and once achieved, switches the phase detector to the clock recovery phase detector which extracts the frequency of the data from the over-sampled data to generate signals to achieve clock recovery; the receiver further comprising a signal processor for decoding the over- sampled data into parallel data words at a lower clock rate than the sampling rate. Preferably the signal processor comprises a transition processor, a data input processor, a clock recovery unit, an eye-tracker and an output data processor; Preferably, the transition processor comprises a transition detector, transition expander and a data selection control bits generator, wherein the transition detector outputs a number of logical ones at every transition in the serial over-sampled data, wherein the transition expander increases the run-length of the output of the logical ones from the transition detector to reduce the susceptibility to jitter, wherein the selection-bits decoder generates control bits to indicate the presence of a transition to the output data processor. Preferably the data input processor includes a means of sampling the over-sampled data in the middle of each two-bit period. Preferably the clock recovery unit extracts information from the over- sampled data to generate control signals that are fed to the charge pump and lock the VCO to the data, Preferably the eye-tracker generates quadrature phase selection control signals for selecting the centre of the two-bit period data cells and transition two-bit period cells. Preferably the output data processor comprises a means of decoding the data from two-bit periods though the control signals from the transition processor to generate an output data word of single-bit data cells. According to still another aspect of the invention, a signal processor for processing encoded data with a minimum run-length greater than one bit is provided, comprising: - an input data processor which comprises data selectors for selecting the data value from a serial data steam in the middle of a two-bit period; - a transition processor for detecting transitions; - a clock recovery unit, - an eye-tracker which selects the centre of the two-bit period data cells and transition two-bit period cells; and - an output data processor which decodes the data from the two-bit periods through the control signals from the transition processor and generates an output data word of single-bit data cells. According to still one more aspect of the invention, a method for processing encoded data with a minimum run-length greater than one bit is provided, comprising the steps of: - selecting a data value from a data steam in the middle of a two-bit period; - detecting bit transitions; - selecting the centre of the two-bit period data cells and transition two-bit period cells; and - decoding data from the two-bit periods and generating output data word of single-bit data cells.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS For a better understanding of the present invention and the advantages thereof and to show how the same may be carried into effect, reference will now be made, by way of example, without loss of generality to the accompanying drawings in which: Figure 1A shows the 8b12b encoding of a 10Gbps serial data stream. Eight bits of single-bit data cells at 10Gbps are coded into 12 bits of output single- bit data cells at a rate of 15Gbps. Figure 1 B shows the eye patterns for waveforms at 10Gbps for non-coded and 8b12b coded data single-bit data cells. Figure 1 C shows the pattern that would be obtained from an oscilloscope for 10Gbps 8b12b coded data. The data edges being used to trigger the oscilloscope time-base. Figure 1 D shows the timing waveforms and circuitry of a serial data re- timer. Figure 2A shows an over-sampling receiver based on patent WO 02/078228. Figure 2B shows a timing diagram detailing the concept behind the quarter-clock rate sampling. Figure 3A shows a block diagram of a signal-processing block that contains several processing blocks that form the overall function to decode over- sampled data. Figure 4A shows a block diagram of the transition processor block from the signal processor block. Figure 4B shows a gate-level implementation of the transition detector. Figure 4C shows a gate-level implementation of the transition expander. Figure 4D shows a block diagram of the select-bits decoder. Figure 5A shows a timing diagram for the operation of the transition processor block with the transition in the middle of the even two-bit period. Figure 5B shows a timing diagram for the operation of the transition processor block with the transition moved to the left of middle in the even two-bit period. Figure 5C shows a timing diagram for the operation of the transition processor block with the transition moved to the right of middle in the even two-bit period. Figure 6 shows a block diagram of the input data processor. Figure 7A shows a timing diagram detailing the operation of the output data processor. Figure 7B shows a gate-level implementation of the output data processor.

DETAILED DESCRIPTION OF THE INVENTION The invention will now be described in detail without limitation to the generality of the present invention with the aid of example embodiments and accompanying drawings. Figure 2B shows a timing diagram of the concept encapsulated in this invention. The serial data stream RXDATA 50 is encoded with a minimum spacing between transitions of 2 bits. A PLL locks RXDATA 50 to a quadrature oscillator that produces clocks EVENCLK 51 and ODDCLK 52. The serial data is sampled on each edge of the quarter-rate quadrature clocks EVENCLK 51 and ODDCLK 52 to produce two data streams EVENDATA 53 and ODDDATA 54 respectively. Even 55 and odd 56 two-bit cells are defined as shown with the edges of the even two-bit cells aligned to the edges of the EVENCLK and the edges of the odd two- bit cells aligned to the edges of the ODDCLK. The data value in each two-bit cell may take on the logical value +1 or 0 or X. Here, the value X indicates that a transition has occurred. The output data 57 is reconstituted from the even and odd samples by following the cells that do not have transitions. The line with the arrow moving through the EVENDATA and ODDDATA cells shows the route to take to reconstitute the serial data. It should be noted that each value from the two-bit cells produces two output data bits. In practice, the sampling process will result in a known value of 1 or 0 in EVENDATA and ODDDATA two-bit cells. However, by detecting the presence of a transition in the region of the sampling point this information may be used to indicate the value X. Although the embodiment of the invention is described for an over- sampling receiver where the data is processed in parallel, it is obvious to someone skilled in the art that a serial implementation of the current invention is possible.

Preferred Embodiment Of The Invention Figure 3a shows a block diagram of part of the signal-processing block 180 that pertains to the current invention. The over-sampled data 150 is forwarded to the transition processor block 310, the input data processor block 320 and the clock recovery unit 390. Although these blocks are shown as distinct processing elements, it may be that elements of these blocks may be shared. In the transition processor block 310 transitions are detected and the information passed to the eye tracker 380 to determine the optimum sampling point for the two-bit window eye opening. The eye tracker 380 producing control signals EVENPHASE 470 and ODDPHASE 480 that determine the sampling points of the even and odd two-bit periods. Additionally, the transition processor 310 generates data selection bit buses EVEN2BSEL 340 and ODD2BSEL 350, which are passed to the output data processor 330. In the input data processing block 320 samples from the data bus 150 are selected from the middle of the even and odd two-bit periods defined by the quadrature clocks within the system. The two output data buses EVENDATA 360 and ODDDATA 370, from the input data processor 320, are passed to the output data processor 330. The output data processor 330 validates the contents of the EVENDATA 360 and ODDDATA 370 buses dependent on the values in the data selection bit buses EVEN2BSEL 340 and ODD2BSEL 350 to form the OUTDATA bus 190. Figure 4A shows the block diagram of the preferred embodiment of the transition processor. The over-sampled DATA bus 150 is processed to generate two output buses EVEN2BSEL and ODD2BSEL. In detail, the over-sampled data bus 150 is passed through a transition detector 410, producing the bus TRAN 450. A transition in the over-sampled data 150 results in two adjacent data bits in the TRAN bus being set while all other bits remain reset. Figure 4B shows the preferred embodiment of the transition detector. A transition detector sub-cell 411 is formed from several logic gates. There is one transition detector sub-cell 411 for every data bit in the over-sampled data bus 150 plus additional over-sampled data bits from the previous over-sampled data word 150. The additional transition detector sub-cells allow detection of transitions over boundaries of the data word 150. Each transition detector sub-cell 411 is used to detect the presence of three adjacent bits in the over-sampled data bus 150 that contain the same logic values. AND-gate 412 detects the presence of three adjacent bits containing logic ones. NOR-gate 413 detects the presence of three adjacent bits containing logic zeros. The output of AND-gate 412 and NOR-gate 413 are further conditioned by a NOR gate 414. The output of NOR-gate 414 is low whenever three adjacent bits in the over-sampled data bus 150 are all high or all low. The output of NOR-gate 414 is high whenever one bit is different to the other bits at the input to the transition detector sub-cell 411. In order to improve the performance of the data recovery under jitter conditions, the transition expansion block 420 further processes bus TRAN 450 to expand the run-length of the transition bits producing the bus TRWIN 460. By virtue of the clock recovery unit 390 locking the data to the VCO in the RX PLL 130, the EVENPHASE bus 470 phase selection pointer is positioned at a point that is the nominal centre of the even data two-bit period. Similarly, the sample selection pointer generated by the ODDPHASE bus 480 is also locked to the odd data two-bit period. Due to jitter, the centre of the two-bit period may not be same as the location of any given data transition. It is necessary to expand the width of the transition so that it falls within the sampling point as determined by the phase selection pointer 470. Otherwise, with only two bits denoting the presence of a transition in the 2-bit bit-cell period it would be necessary to contain the jitter to less than ±1 sample bit. The outputs of all of the transition detector sub-cells are collected together in bus TRAN 450 and pass to the transition expander 420. In order to increase the robustness of the invention to jitter or inter-symbol interference, the two consecutive bits denoting the detection of a transition in the bus TRAN 450 are expanded to eight bits in the transition expansion block 420. Three additional bits are added to each side of the TRAN pulse. Figure 4C shows the preferred embodiment of the transition expansion block 420 that uses a plurality of seven- input OR-gates 421. For each OR-gate 421 , one of its inputs connects to the TRAN data bit corresponding to the output position of the OR-gate in the TRWIN bus 460. The other six inputs also connect to the TRAN data bits, three either side of the current TRAN data bit. With the transition expansion scheme it is possible to tolerate jitter between a transition and the phase selection pointer of up to ±3 or ±4 sample bits at any moment. This is equivalent to ±0.5UI (Unit Interval) where 1 UI is one bit of the coded data stream. This makes the current invention very robust to high frequency jitter components in the serial data stream 100. In conjunction with the ODDPHASE and EVENPHASE pointers samples from the TRWIN bus are selected to provide information on the presence or absence of a transition in the corresponding ODDDATA and EVENDATA two-bit periods. The EVEN2BSEL bus 340 is generated from the EVENPHASE pointer bus and the TRWIN bus 460, while ODD2BSEL bus 350 is generated from the ODDPHASE pointer bus 480 and the TRWIN bus 460. The TRWIN bus 150, EVENPHASE bus and ODDPHASE bus are the inputs to the select-bits decoder 430. The outputs of the select-bits decoder 430 are the EVEN2BSEL bus 340 and ODD2BSEL bus 350. The EVENPHASE bus and ODDPHASE bus select one bit from the TRWIN bus data for every two-bit period. The EVENPHASE bus selects one bit from the TRWIN bus corresponding to each even two-bit period. The ODDPHASE bus selects one bit from the TRWIN bus corresponding to each odd two-bit period. The data bits selected by the EVENPHASE bus from the TRWIN bus form the EVEN2BSEL bus 340. The data buts selected by the ODDPHASE bus from the TRWIN bus form the ODD2BSEL bus 350. Consequently, the preferred embodiment of the select-bits decoder 430 is that of a plurality of data selectors controlled by the EVENPHASE and ODDPHASE buses. Figure 4D shows the preferred embodiment of the select-bits decoder 430. In Figure 4D, data selectors 431 and 432 select one bit out of every 16 adjacent bits from the TRWIN bus. Data selector 431 selects one bit from bits TRWIN<0:15>, TRWIN<16:31> and so forth to form the bus EVEN2BSEL 340. Data selector 432 selects one bit from bits TRWIN<8:23>, TRWIN<24:39> and so forth to form the bus ODD2BSEL 350. In addition, in order to ensure that all data bits are compared in a contiguous manner it is necessary to use some data bits from the previous over- sampled data word 150. The method of such implementation is obvious to someone skilled in the art. By means of an example, to illustrate the operation of the transition detector and transition expander, Figure 5A shows the contents of the DATA, TRAN and TRWIN buses for a two-bit period with a transition in the centre of the bit-cell, the bit-cell defined by the sampling phases. In this instance the VCO clock is aligned to the data such that the transition occurs in the middle of the two-bit period. This situation would occur, for example, when there was no jitter on the data or VCO clock. The EVENPHASE pointer is positioned at sample 8 of the two- bit period. Although the data sampled by the EVENPHASE pointer is a logical zero there is in fact a transition present in the two-bit period. Accordingly, the two-bit period must be marked as having a transition present in order to be able to decode the data correctly. The transition, which in this example, is placed in the middle of the bit-cell is detected through the action of the transition detector 410 producing two adjacent logical one samples in the TRAN bus. This is expanded into eight adjacent samples of value logical one in the TRWIN bus. The EVENPHASE pointer selects one of the logic one samples. A logical one in the TRWIN bus indicates that the following processing block should process the data selected by the EVENPHASE pointer as a transition. Figure 5B shows the same timing diagram as Figure 5A but with the transition moved 4 samples to the left. This may occur in the presence of data- dependent jitter or inter-symbol interference. It can be clearly seen that the EVENPHASE pointer still picks up a value of logical one from the TRWIN bus, indicating the presence of a transition in the two-bit cell period. Should the jitter be increased such that the transition was moved 5 samples to the left then one of the bits in the TRWIN bus would be selected by the ODDPHASE pointer erroneously marking the previous two-bit cell as having a transition. Figure 5C shows the same timing diagram as Figure 5A but with the transition moved 3 samples to the right. This is the maximum extent to which jitter may move the transition before it will be picked up by the ODDPHASE pointer from the following two-bit period. The embodiment described in Figures 4A, 4B, 4C, 4D, 5A, 5B and 5C has been shown to be capable of coping with jitter up to ±3 or ±4 sampling bits. 'Lower frequency random jitter is tracked by the eye-tracker 380, as described in US provisional patent application 60/ filed 15.04.04 (GB0406843.3, filed 26.03.04). Figure 6 shows a block diagram of the input data processor. The DATA bus 150 is sampled in the middle of the even and odd two-bit periods. As the data has been over-sampled at a rate of 16X, one bit is selected from every adjacent sixteen bits of the DATA bus starting at bits zero and eight to generate the EVENDATA and ODDDATA buses 360 and 370. Data selectors 610 and 620 each select one data bit from the DATA bus 150. Data selectors 610 select data from the bits 0 to 15, 16 to 31 and so forth. Data selectors 620 select data from the bits 8 to 23, 24 to 39 and so forth. The control signals for the data selectors 610 and 620 are the EVENPHASE and ODDPHASE buses 470 and 480 respectively which come from the eye tracker 380. The output data processor is now described. The timing diagram in figure 2B showed that the output data could be reconstituted by following the even and odd sampled data bits from every pair of input data bits. The presence of a transition in the two-bit period is used to switch the output data selection between the EVENDATA and ODDDATA bits. Figure 7A shows a timing diagram for the output data processor 330 of the preferred embodiment of this invention. The data from the transition processor 310 is used to validate the corresponding data from the input data processor 320. The

EVEN2BSEL signal validates the EVENDATA signal, while the ODD2BSEL signal validates the ODDDATA signal. A logical one in EVEN2BSEL or ODD2BSEL indicates the presence of a transition in the corresponding two-bit period and disables the generation of output data bits. A logical zero in EVEN2BSEL bus or ODD2BSEL bus routes the EVENDATA bus and ODDDATA bus to the OUTDATA bus. Figure 7B shows the preferred embodiment of the output data processor

330. Each output data bit has two possible sources, as shown in figure 7A.

Additionally, since the data has been sampled in two-bit periods, each valid data bit produces two output data bits: - Bit (n) of the EVENDATA bus is routed to bit (2*n) of the OUTPUT data bus when bit (n) of the EVEN2BSEL is low. - Bit (n) of the EVENDATA bus is routed to bit (2*n-1) of the OUTPUT data bus when bit (n) of the EVEN2BSEL is low. - Bit (n) of the ODDDATA bus is routed to bit (2*n) of the OUTPUT data bus when bit (n) of the ODD2BSEL is low. - Bit (n) of the ODDDATA bus is routed to bit (2*n+1) of the OUTPUT data bus when bit (n) of the ODD2BSEL is low. A plurality of data selectors 710 is formed by three NOR-gates 711 , 712 and 713. A total of 32 data selectors are used to generate the 32-bit OUTPUT data word 190.

It is obvious to someone skilled in the art that the transition processor may be enhanced to eliminate spurious bits arising from, for example, metastability in the samplers 120. The generation of an over-sampled data stream that contains a sequence such as 00000101111 needs to be handled in such a way that the output signals from the transition processor do not overlap. The above data sequence would produce the TRAN sequence 001111000 i.e. an increase from two bits to four bits. The transition expander would then increase this sequence to 12-bits in width, causing some bits to potentially overflow into the preceding or following EVEN2BSEL or ODD2BSEL data bits. A system that limits the length of the pulses in the TRWIN bus is now described. Figure 8A shows a timing diagram of the signals in a modified transition processor. In the modified transition processor there are two masking signals that are used to limit the propagation of the TRAN bits and maintain them within the required boundaries. There are 16 samples in the even two-bit period that contains samples 0 through 15 inclusive. Figure 8A shows one of the two masking signals EVENMASK that contains a sequence of logical ones in the sample bit positions 4 through 11 inclusive. Another masking signal is ODDMASK that contains logical ones in sample positions 4 through 11 inclusive of the samples 0 through 15 inclusive of the odd two-bit periods. It can be seen that the EVENMASK and ODDMASK buses provide a windowing function centred on the EVENPHASE pointer and ODDPHASE pointer respectively. The transition detector is now modified to take the exclusive-OR of adjacent bits in the data bus producing the TRAN bus. The implementation of this is obvious to someone skilled in the art. Figure 8A shows the case for an even two-bit period where the data bus

150 shows a transition in a sequence 00010111. This input data sequence results in three adjacent bits in the TRAN bus. A modified transition expander limits the propagation of the TRAN bits to fill the region defined by the window in the EVENMASK and ODDMASK buses. Figure 8B shows the preferred implementation of the modified transition processor. Two rotating shift registers 820 and 830 contain the EVENMASK and ODDMASK data bits. The registers 820 and 830 are initialised so that they contain a sequence 00001111111110000 for every two-bit period. The data bits sequence for the ODDMASK is offset by 8 samples with respect to the EVENMASK data bits. It is apparent to someone skilled in the art means to initialise these shift registers. The data bits within the EVENMASK 820 and ODDMASK 830 register are shifted left or right in conjunction with changes in the EVENPHASE and ODDPHASE control buses. The EVENPHASE and ODDPHASE control buses move in single steps controlled by the eye-tracker 380 in response to positioning of the optimum sampling points in the data eye. The eye-tracker 380 generates signals INC_PHASE and DEC_PHASE which are used to shift the EVENMASK and ODDMASK data bits right and left respectively. Each modified transition expander consists of a plurality of cells each with a first input from the TRAN bus and a second input from the EVENMASK or ODDMASK bus. The modified transition expander has a first output that is combined with other outputs from other modified transition expander cells to form the EVENTRWIN and ODDTRWIN buses. Additional outputs from the modified transition expander cell propagate the transition bits left and right depending on the state of the TRAN and MASK inputs. The logical ones in the EVENMASK and ODDMASK registers are used to indicate to the modified transition expander that a transition bit should be propagated towards the edges of the even and odd two-bit cell periods. A logical zero in the EVENMASK and ODDMASK registers indicate to the modified transition expander that propagation of a transition should stop as the cell boundary of the two-bit period has been reached. Figure 8C shows the implementation of the modified transition expander cell. The signals FILL_LEFT_OUT, FILL_LEFT_IN, FILL_RIGHT_OUT and FILL_RIGHT_IN allow propagation of the transition when the MASK input bit has the value of logical one. Propagation stops when the MASK bit takes on the value of logical zero. The Boolean equations governing the operation of the modified transition expander cell can be clearly determined from the drawing in figure 8C. The cell is intended to abut to other like-cells such that the FILL_LEFT_OUT signal of cell (n) in the plurality of cells connects to the signal FILL_LEFT_IN of cell (n-1). Similarly, the signal FILL_RIGHT_OUT of cell (n) connects to the signal FILL_RIGHT_IN of cell (n+1). It is apparent to someone skilled in the art that there are many other logically equivalent implementations of this circuit. The modified select bits decoders 845 and 855 are similar in design to the select bit decoder in Figure 4D, with the exception that there are two input buses. Buses EVENTRWIN 893 and ODDTRWIN 894 connect to the modified select-bits decoders 845 and 855 respectively. Each modified select-bits decoder 845 and 855 contain a plurality of 16-bits to 1-bit data selectors. Each of the data selectors are controlled by the EVENPHASE 470 and ODDPHASE 480 buses, selecting the data bit corresponding to the centre of the even and odd two-bit periods from the EVENTRWIN bus 893 and ODDTRWIN 894 bus respectively. Although the preferred embodiment only has been described in detail, it should be understood that various changes, substitutions and alterations can be made therein without departing from the spirit and scope of the invention as defined by the appended claims.

Claims

1. A signal processor for processing encoded data with a minimum run- length greater than one bit, comprising: - an input data processor which comprises data selectors for selecting the data value from the over-sampled data in the middle of a two-bit period; - a transition processor for detecting transitions in a binary data stream; - a clock recovery unit, - an eye-tracker which selects the centre of the two-bit period data cells and transition two-bit period cells; and - an output data processor which decodes the data from the two-bit periods through the control signals from the transition processor and generates an output data word of single-bit data cells.

2. A signal processor of claim 1 , wherein the input data is encoded with a minimum spacing between transitions of 2 bits.

3. A signal processor of claim 1 , wherein the input serial data is sampled on each edge of the quarter-rate quadrature clocks to produce even and odd data streams.

4. A signal processor of claim 3, wherein the input data processor selects samples from the even and odd data streams by analyzing even and odd two-bit cells defined by the respective even and odd clocks.

5. A signal processor of claim 1 , wherein the transition processor comprises a transition detector, a transition expander and a bit selection decoder.

6. A signal processor of claim 5, wherein the transition detector comprises a means to detect the presence of at least three adjacent bits that contain same logic values.

7. A signal processor of claim 5, wherein the transition expander comprises a means to expand the width of a transition pulse generated in the transition detector to maximal possible number of samples which is half of a two bit interval.

8. A signal processor of claim 5, wherein the selection-bits decoder generates output signals indicating the presence or absence of transitions in each pair of data bits.

9. A signal processor of claim 1 wherein the clock recovery unit extracts information from the over-sampled data to generate control phase signals to lock the RX PLL to the data.

10. A signal processor of claim 1 , wherein the clock recovery unit comprises a dual phase detector phase locked loop configured with a clock recovery phase detector, a phase and frequency detector and a frequency lock detector; wherein the lock detector locks the VCO to an external reference frequency that is close to, but not exactly equal to, the frequency of the sampled data, and within the capture range of the clock recovery phase detector.

11. A signal processor of claim 1 , wherein the_eye-tracker generates quadrature phase selection control signals for selecting the centre of the two-bit period data cells and transition two-bit period cells.

12. A signal processor of claim 1 wherein the data output processor further comprises a means of selecting valid data bits using the transition processor and input data processor information.

13. A signal processor of claim 1 wherein the output data processor comprises a means of decoding data from two-bit periods though the control signals from the transition processor to generate an output data word of single-bit data cells.

14. A signal processor according to claim 1 wherein thetransition processor comprises two transition window-definition shift registers, two modified transition expanders and two modified select-bits decoders.

15. A signal processor according to claim 14 wherein the transition detector comprises a plurality of exclusive OR logic gates with inputs connected to adjacent samples in the over-sampled data bus.

16. A signal processor according to claim 14 wherein the pair of transition window-definition shift registers comprises a plurality of shift register elements with the output from the final stage of each register connected to the corresponding input of the first stage of each shift register.

17. A signal processor according to claim 14 wherein the pair of transition window-definition shift registers comprises shift registers that are preloaded with a window pattern, wherein the data may be shifted left and right under the control of signals from the eye-tracker where the centre of the window defined by the data bits is located at the centre of the two-bit period.

18. A signal processor according to claim 14 wherein the data pattern loaded into each window-definition shift register is offset by eight samples in the case of a 16X over-sampling ratio.

19. A signal processor according to claim 14 wherein the pair of modified select-bits decoders comprises a plurality of 16 bits to 1-bit data selectors controlled by signals from the eye-tracker.

20. A method of reducing the clock frequency and power reduction of an over-sampling receiver using coded data where the minimum run-length of the data is greater than one bit, wherein the receiver comprises a signal processor according to claims 1 through 19.

21. A receiver comprising a sampling system which over-samples the data and provides a set of samples of the received signal; provided with a voltage controlled oscillator (VCO) generating multiple clocks for spreading the samples in time so that each pair of bit intervals is covered by several samples, wherein the sampled data are further, processed in a signal processor of claim 1.